mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
add support for initializing registers and memories to the functional backend
This commit is contained in:
Emily Schmidt
parent
bdb59ffc8e
commit
99effb6789
10 changed files with 418 additions and 282 deletions
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@ -69,35 +69,48 @@ struct CxxType {
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using CxxWriter = FunctionalTools::Writer;
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struct CxxStruct {
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std::string name;
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dict<IdString, CxxType> types;
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CxxScope<IdString> scope;
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CxxStruct(std::string name)
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: name(name) {
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scope.reserve("fn");
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scope.reserve("visit");
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}
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void insert(IdString name, CxxType type) {
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scope(name, name);
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types.insert({name, type});
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}
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void print(CxxWriter &f) {
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f.print("\tstruct {} {{\n", name);
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for (auto p : types) {
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f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first));
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}
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f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
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for (auto p : types) {
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f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first));
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}
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f.print("\t\t}}\n");
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f.print("\t}};\n\n");
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};
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std::string operator[](IdString field) {
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return scope(field, field);
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}
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std::string name;
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dict<IdString, CxxType> types;
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CxxScope<IdString> scope;
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CxxStruct(std::string name) : name(name)
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{
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scope.reserve("fn");
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scope.reserve("visit");
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}
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void insert(IdString name, CxxType type) {
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scope(name, name);
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types.insert({name, type});
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}
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void print(CxxWriter &f) {
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f.print("\tstruct {} {{\n", name);
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for (auto p : types) {
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f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first));
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}
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f.print("\n\t\ttemplate <typename T> void visit(T &&fn) {{\n");
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for (auto p : types) {
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f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first));
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}
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f.print("\t\t}}\n");
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f.print("\t}};\n\n");
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};
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std::string operator[](IdString field) {
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return scope(field, field);
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}
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};
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std::string cxx_const(RTLIL::Const const &value) {
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std::stringstream ss;
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ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
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if(value.size() > 32) ss << "{";
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for(int i = 0; i < value.size(); i += 32) {
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if(i > 0) ss << ", ";
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ss << value.extract(i, 32).as_int();
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}
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if(value.size() > 32) ss << "}";
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ss << ")";
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return ss.str();
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}
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template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor<void> {
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using Node = FunctionalIR::Node;
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CxxWriter &f;
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@ -136,20 +149,7 @@ template<class NodePrinter> struct CxxPrintVisitor : public FunctionalIR::Abstra
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void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); }
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void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); }
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void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); }
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void constant(Node, RTLIL::Const value) override {
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std::stringstream ss;
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bool multiple = value.size() > 32;
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ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase;
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if(multiple) ss << "{";
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while(value.size() > 32) {
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ss << value.as_int() << ", ";
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value = value.extract(32, value.size() - 32);
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}
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ss << value.as_int();
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if(multiple) ss << "}";
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ss << ")";
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print("{}", ss.str());
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}
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void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); }
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void input(Node, IdString name) override { print("input.{}", input_struct[name]); }
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void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); }
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void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); }
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@ -184,8 +184,24 @@ struct CxxModule {
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output_struct.print(f);
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state_struct.print(f);
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f.print("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n");
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f.print("\tstatic void initialize(State &);\n");
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f.print("}};\n\n");
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}
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void write_initial_def(CxxWriter &f) {
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f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name);
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for (auto [name, sort] : ir.state()) {
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if (sort.is_signal())
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f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name)));
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else if (sort.is_memory()) {
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const auto &contents = ir.get_initial_state_memory(name);
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f.print("\tstate.{}.fill({});\n", state_struct[name], cxx_const(contents.default_value()));
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for(auto range : contents)
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for(auto addr = range.base(); addr < range.limit(); addr++)
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f.print("\tstate.{}[{}] = {};\n", state_struct[name], addr, cxx_const(range[addr]));
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}
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}
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f.print("}}\n\n");
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}
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void write_eval_def(CxxWriter &f) {
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f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const ¤t_state, {0}::State &next_state)\n{{\n", module_name);
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CxxScope<int> locals;
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@ -204,7 +220,7 @@ struct CxxModule {
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f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name)));
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for (auto [name, sort] : ir.outputs())
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f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name)));
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f.print("}}\n");
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f.print("}}\n\n");
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}
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};
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@ -225,6 +241,7 @@ struct FunctionalCxxBackend : public Backend
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mod.write_header(f);
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mod.write_struct_def(f);
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mod.write_eval_def(f);
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mod.write_initial_def(f);
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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@ -410,6 +410,9 @@ public:
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ret._contents[addr.template as_numeric<size_t>()] = data;
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return ret;
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}
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// mutating methods for initializing a state
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void fill(Signal<d> data) { _contents.fill(data); }
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Signal<d> &operator[](Signal<a> addr) { return _contents[addr.template as_numeric<size_t>()]; }
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};
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#endif
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@ -109,6 +109,13 @@ public:
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}
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};
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std::string smt_const(RTLIL::Const const &c) {
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std::string s = "#b";
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for(int i = c.size(); i-- > 0; )
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s += c[i] == State::S1 ? '1' : '0';
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return s;
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}
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struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
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using Node = FunctionalIR::Node;
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std::function<SExpr(Node)> n;
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@ -117,13 +124,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
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SmtPrintVisitor(SmtStruct &input_struct, SmtStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {}
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std::string literal(RTLIL::Const c) {
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std::string s = "#b";
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for(int i = c.size(); i-- > 0; )
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s += c[i] == State::S1 ? '1' : '0';
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return s;
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}
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SExpr from_bool(SExpr &&arg) {
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return list("ite", std::move(arg), "#b1", "#b0");
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}
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@ -149,8 +149,8 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
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SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); }
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SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); }
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SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); }
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SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); }
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SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); }
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SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), smt_const(RTLIL::Const(State::S1, a.width())))); }
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SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), smt_const(RTLIL::Const(State::S0, a.width())))); }
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SExpr reduce_xor(Node, Node a) override {
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vector<SExpr> s { "bvxor" };
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for(int i = 0; i < a.width(); i++)
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@ -174,7 +174,7 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor<SExpr> {
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SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); }
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SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); }
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SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); }
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SExpr constant(Node, RTLIL::Const value) override { return literal(value); }
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SExpr constant(Node, RTLIL::Const const &value) override { return smt_const(value); }
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SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); }
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SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); }
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@ -199,6 +199,7 @@ struct SmtModule {
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, output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope)
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, state_struct(scope.unique_name(module->name.str() + "_State"), scope)
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{
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scope.reserve(name + "-initial");
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for (const auto &input : ir.inputs())
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input_struct.insert(input.first, input.second);
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for (const auto &output : ir.outputs())
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@ -207,18 +208,8 @@ struct SmtModule {
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state_struct.insert(state.first, state.second);
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}
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void write(std::ostream &out)
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{
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SExprWriter w(out);
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input_struct.write_definition(w);
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output_struct.write_definition(w);
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state_struct.write_definition(w);
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w << list("declare-datatypes",
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list(list("Pair", 2)),
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list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
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void write_eval(SExprWriter &w)
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{
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w.push();
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w.open(list("define-fun", name,
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list(list("inputs", input_struct.name),
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@ -245,6 +236,39 @@ struct SmtModule {
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state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); });
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w.pop();
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}
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void write_initial(SExprWriter &w)
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{
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std::string initial = name + "-initial";
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w << list("declare-const", initial, state_struct.name);
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for (const auto &[name, sort] : ir.state()) {
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if(sort.is_signal())
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w << list("assert", list("=", state_struct.access(initial, name), smt_const(ir.get_initial_state_signal(name))));
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else if(sort.is_memory()) {
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auto contents = ir.get_initial_state_memory(name);
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for(int i = 0; i < 1<<sort.addr_width(); i++) {
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auto addr = smt_const(RTLIL::Const(i, sort.addr_width()));
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w << list("assert", list("=", list("select", state_struct.access(initial, name), addr), smt_const(contents[i])));
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}
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}
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}
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}
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void write(std::ostream &out)
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{
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SExprWriter w(out);
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input_struct.write_definition(w);
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output_struct.write_definition(w);
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state_struct.write_definition(w);
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w << list("declare-datatypes",
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list(list("Pair", 2)),
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list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y"))))));
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write_eval(w);
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write_initial(w);
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}
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};
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struct FunctionalSmtBackend : public Backend {
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@ -19,10 +19,100 @@
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#include "kernel/yosys.h"
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#include "kernel/functionalir.h"
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#include <random>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemContentsTest {
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int addr_width, data_width;
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MemContents state;
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using addr_t = MemContents::addr_t;
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std::map<addr_t, RTLIL::Const> reference;
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MemContentsTest(int addr_width, int data_width) : addr_width(addr_width), data_width(data_width), state(addr_width, data_width, RTLIL::Const(State::S0, data_width)) {}
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void check() {
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state.check();
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for(auto addr = 0; addr < (1<<addr_width); addr++) {
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auto it = reference.find(addr);
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if(it != reference.end()) {
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if(state.count_range(addr, addr + 1) != 1) goto error;
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if(it->second != state[addr]) goto error;
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} else {
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if(state.count_range(addr, addr + 1) != 0) goto error;
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}
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}
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return;
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error:
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printf("FAIL\n");
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int digits = (data_width + 3) / 4;
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for(auto addr = 0; addr < (1<<addr_width); addr++) {
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if(addr % 8 == 0) printf("%.8x ", addr);
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auto it = reference.find(addr);
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bool ref_def = it != reference.end();
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RTLIL::Const ref_value = ref_def ? it->second : state.default_value();
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std::string ref_string = stringf("%.*x", digits, ref_value.as_int());
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bool sta_def = state.count_range(addr, addr + 1) == 1;
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RTLIL::Const sta_value = state[addr];
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std::string sta_string = stringf("%.*x", digits, sta_value.as_int());
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if(ref_def && sta_def) {
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if(ref_value == sta_value) printf("%s%s", ref_string.c_str(), string(digits, ' ').c_str());
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else printf("%s%s", ref_string.c_str(), sta_string.c_str());
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} else if(ref_def) {
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printf("%s%s", ref_string.c_str(), string(digits, 'M').c_str());
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} else if(sta_def) {
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printf("%s%s", sta_string.c_str(), string(digits, 'X').c_str());
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} else {
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printf("%s", string(2*digits, ' ').c_str());
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}
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printf(" ");
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if(addr % 8 == 7) printf("\n");
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}
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printf("\n");
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//log_abort();
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}
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void clear_range(addr_t begin_addr, addr_t end_addr) {
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for(auto addr = begin_addr; addr != end_addr; addr++)
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reference.erase(addr);
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state.clear_range(begin_addr, end_addr);
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check();
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}
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void insert_concatenated(addr_t addr, RTLIL::Const const &values) {
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addr_t words = ((addr_t) values.size() + data_width - 1) / data_width;
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for(addr_t i = 0; i < words; i++) {
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reference.erase(addr + i);
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reference.emplace(addr + i, values.extract(i * data_width, data_width));
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}
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state.insert_concatenated(addr, values);
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check();
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}
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template<typename Rnd> void run(Rnd &rnd, int n) {
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std::uniform_int_distribution<addr_t> addr_dist(0, (1<<addr_width) - 1);
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std::poisson_distribution<addr_t> length_dist(10);
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std::uniform_int_distribution<uint64_t> data_dist(0, ((uint64_t)1<<data_width) - 1);
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while(n-- > 0) {
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addr_t low = addr_dist(rnd);
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//addr_t length = std::min((1<<addr_width) - low, length_dist(rnd));
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//addr_t high = low + length - 1;
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addr_t high = addr_dist(rnd);
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if(low > high) std::swap(low, high);
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if((rnd() & 7) == 0) {
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log_debug("clear %.2x to %.2x\n", (int)low, (int)high);
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clear_range(low, high + 1);
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} else {
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log_debug("insert %.2x to %.2x\n", (int)low, (int)high);
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RTLIL::Const values;
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for(addr_t addr = low; addr <= high; addr++) {
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RTLIL::Const word(data_dist(rnd), data_width);
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values.bits.insert(values.bits.end(), word.bits.begin(), word.bits.end());
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}
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insert_concatenated(low, values);
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}
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}
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}
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};
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struct FunctionalTestGeneric : public Pass
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{
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FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {}
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@ -40,6 +130,14 @@ struct FunctionalTestGeneric : public Pass
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size_t argidx = 1;
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extra_args(args, argidx, design);
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MemContentsTest test(8, 16);
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std::random_device seed_dev;
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std::mt19937 rnd(23); //seed_dev());
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test.run(rnd, 1000);
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/*
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for (auto module : design->selected_modules()) {
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log("Dumping module `%s'.\n", module->name.c_str());
|
||||
auto fir = FunctionalIR::from_module(module);
|
||||
|
|
@ -50,6 +148,7 @@ struct FunctionalTestGeneric : public Pass
|
|||
for(auto [name, sort] : fir.state())
|
||||
std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n";
|
||||
}
|
||||
*/
|
||||
}
|
||||
} FunctionalCxxBackend;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
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Reference in a new issue