Merge branch 'main' into make_excl

Makefile

@@ -171,7 +171,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.48+51
+YOSYS_VER := 0.48+57
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -735,6 +735,7 @@ OBJS += passes/sat/sim.o
 OBJS += passes/techmap/bufnorm.o
 OBJS += passes/cmds/rename.o
 OBJS += passes/cmds/segv.o
+OBJS += passes/cmds/delete.o
 
 include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc
 include $(YOSYS_SRC)/passes/memory/Makefile.inc
@@ -1013,6 +1014,8 @@ ifneq ($(filter $(PROGRAM_PREFIX)yosys-filterlib,$(TARGETS)),)
 endif
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys
 	$(INSTALL_SUDO) cp -r share $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys
+	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(DATDIR)
+	$(INSTALL_SUDO) cp -r share $(DESTDIR)$(DATDIR)/
 ifeq ($(ENABLE_LIBYOSYS),1)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(LIBDIR)
 	$(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR)/

docs/source/index.rst

@@ -7,17 +7,6 @@ see :doc:`/introduction`.  For a quick guide on how to get started using Yosys,
 check out :doc:`/getting_started/index`.  For the complete list of commands
 available, go to :ref:`commandindex`.
 
-.. note::
-
-   This documentation recently went through a major restructure.  If you're
-   looking for something from the previous version and can't find it here,
-   please `let us know`_.  Documentation from before the restructure can still
-   be found by switching to `version 0.36`_ or earlier.  Note that the previous
-   theme does not include a version switcher.
-
-.. _let us know: https://github.com/YosysHQ/yosys/issues/new/choose
-.. _version 0.36: https://yosyshq.readthedocs.io/projects/yosys/en/0.36/
-
 .. todo:: look into command ref improvements
 
    - Search bar with live drop down suggestions for matching on title /

kernel/yosys.cc

@@ -561,8 +561,8 @@ void yosys_setup()
 		PyImport_AppendInittab((char*)"libyosys", INIT_MODULE);
 		Py_Initialize();
 		PyRun_SimpleString("import sys");
-		signal(SIGINT, SIG_DFL);
 	}
+	signal(SIGINT, SIG_DFL);
 #endif
 
 	init_share_dirname();

passes/cmds/reconstructbusses.cc

@@ -47,6 +47,8 @@ struct ReconstructBusses : public ScriptPass {
 		log("Running reconstructbusses pass\n");
 		log_flush();
 		for (auto module : design->modules()) {
+			if (module->get_bool_attribute("\\blackbox"))
+				continue;
 			log("Creating bus groups for module %s\n", module->name.str().c_str());
 			log_flush();
 			// Collect all wires with a common prefix
@@ -104,7 +106,7 @@ struct ReconstructBusses : public ScriptPass {
 			}
 			log("Found %ld groups\n", wire_groups.size());
 			if (wire_groups.size() == 0) {
-				std::cout << "No busses to reconstruct. Done." << std::endl;
+				log("No busses to reconstruct. Done.\n");
 				continue;
 			}
 			log("Creating busses\n");

passes/cmds/splitfanout.cc

@@ -136,7 +136,7 @@ struct SplitfanoutWorker
 			// Configure the driver cell
 			IdString new_name;
 			Cell *new_cell;
-			if (bit_user_i-- != 0) { // create a new cell
+			if (bit_user_i != 0) { // create a new cell
 				new_name = module->uniquify(stringf("%s_splfo%d", cell->name.c_str(), bit_user_i));
 				new_cell = module->addCell(new_name, cell);
 				// Add new cell to the bit_users_db
@@ -173,6 +173,9 @@ struct SplitfanoutWorker
 				new_cell->setPort(outport, new_wire);
 			}
 
+			// Decrement bit user index
+			bit_user_i--;
+
 			// Log the new cell
 			log_debug("  slice %d: %s => %s\n", foi++, log_id(new_name), log_signal(new_cell->getPort(outport)));
 		}

passes/opt/wreduce.cc

@@ -263,6 +263,19 @@ struct WreduceWorker
 		}
 	}
 
+	int reduced_opsize(const SigSpec &inp, bool signed_)
+	{
+		int size = GetSize(inp);
+		if (signed_) {
+			while (size >= 2 && inp[size - 1] == inp[size - 2])
+				size--;
+		} else {
+			while (size >= 1 && inp[size - 1] == State::S0)
+				size--;
+		}
+		return size;
+	}
+
 	void run_cell(Cell *cell)
 	{
 		bool did_something = false;
@@ -295,6 +308,45 @@ struct WreduceWorker
 		bool port_a_signed = false;
 		bool port_b_signed = false;
 
+		// For some operations if the output is no wider than either of the inputs
+		// we are free to choose the signedness of the operands
+		if (cell->type.in(ID($mul), ID($add), ID($sub)) &&
+				max_port_a_size == GetSize(sig) &&
+				max_port_b_size == GetSize(sig)) {
+			SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B));
+
+			// Remove top bits from sig_a and sig_b which are not visible on the output
+			sig_a.extend_u0(max_port_a_size);
+			sig_b.extend_u0(max_port_b_size);
+
+			int signed_cost, unsigned_cost;
+			if (cell->type == ID($mul)) {
+				signed_cost = reduced_opsize(sig_a, true) * reduced_opsize(sig_b, true);
+				unsigned_cost = reduced_opsize(sig_a, false) * reduced_opsize(sig_b, false);
+			} else {
+				signed_cost = max(reduced_opsize(sig_a, true), reduced_opsize(sig_b, true));
+				unsigned_cost = max(reduced_opsize(sig_a, false), reduced_opsize(sig_b, false));
+			}
+
+			if (!port_a_signed && !port_b_signed && signed_cost < unsigned_cost) {
+				log("Converting cell %s.%s (%s) from unsigned to signed.\n",
+						log_id(module), log_id(cell), log_id(cell->type));
+				cell->setParam(ID::A_SIGNED, 1);
+				cell->setParam(ID::B_SIGNED, 1);
+				port_a_signed = true;
+				port_b_signed = true;
+				did_something = true;
+			} else if (port_a_signed && port_b_signed && unsigned_cost < signed_cost) {
+				log("Converting cell %s.%s (%s) from signed to unsigned.\n",
+						log_id(module), log_id(cell), log_id(cell->type));
+				cell->setParam(ID::A_SIGNED, 0);
+				cell->setParam(ID::B_SIGNED, 0);
+				port_a_signed = false;
+				port_b_signed = false;
+				did_something = true;
+			}
+		}
+
 		if (max_port_a_size >= 0 && cell->type != ID($shiftx))
 			run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
 

passes/techmap/bufnorm.cc

@@ -391,7 +391,7 @@ struct BufnormPass : public Pass {
 					}
 
 					if (w->name.isPublic())
-						log("  directly driven by cell %s port %s: %s\n",
+						log_debug("  directly driven by cell %s port %s: %s\n",
 								log_id(cell), log_id(conn.first), log_id(w));
 
 					for (auto bit : SigSpec(w))

tests/various/wreduce2.ys

@@ -0,0 +1,22 @@
+read_verilog <<EOF
+module top(a, b, y);
+	parameter awidth = 6;
+	parameter bwidth = 8;
+	parameter ywidth = 14;
+
+	input [awidth-1:0] a;
+	input [bwidth-1:0] b;
+	output [ywidth-1:0] y;
+
+	wire [ywidth-1:0] aext = {{(ywidth-awidth){a[awidth-1]}}, a};
+	wire [ywidth-1:0] bext = {{(ywidth-bwidth){b[bwidth-1]}}, b};
+
+	assign y = aext*bext;
+endmodule
+EOF
+
+opt_clean
+wreduce
+select -assert-count 1 t:$mul
+select -assert-count 1 t:$mul r:A_SIGNED=1 r:B_SIGNED=1 %i %i
+select -assert-count 1 t:$mul r:A_WIDTH=6 r:B_WIDTH=8 %i %i