mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

Add "min bits" and "min wports" to xilinx dram rules

Browse source
This commit is contained in:
Eddie Hung 2019-05-23 11:32:28 -07:00
parent ca46947354
commit 99a3fee8f4
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/drams.txt
View file

@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D
endbram endbram
match $__XILINX_RAM64X1D match $__XILINX_RAM64X1D
min bits 5
min wports 1
make_outreg make_outreg
or_next_if_better or_next_if_better
endmatch endmatch
match $__XILINX_RAM128X1D match $__XILINX_RAM128X1D
min bits 9
min wports 1
make_outreg make_outreg
endmatch endmatch