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Merge pull request #1340 from YosysHQ/eddie/abc_no_clean

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abc9 to not call "clean" at end of run (often called outside)
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Eddie Hung 2019-08-30 12:27:09 -07:00 • committed by GitHub
commit 999fb33fd0
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4 changed files with 35 additions and 35 deletions
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26
passes/techmap/abc9.cc
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@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module
for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second;
if (!w->port_input && !w->port_output)
continue;
RTLIL::Wire *wire = module->wire(w->name);
for (auto port : mapped_mod->ports) {
RTLIL::Wire *w = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
log_assert(w->port_input || w->port_output);
RTLIL::SigSig conn;
if (w->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
module->connect(conn);
}
if (w->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
else if (w->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
module->connect(conn);
}
}
for (auto &it : bit_users)
@ -1300,9 +1297,6 @@ struct Abc9Pass : public Pass {
assign_map.clear();
// The "clean" pass also contains a design->check() call
Pass::call(design, "clean");
log_pop();
}
} Abc9Pass;