mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 10:50:25 +00:00
Code Activity

genrtlil: fix mux2rtlil generated wire signedness

Browse source
This commit is contained in:
Zachary Snow 2020-12-22 17:38:51 -07:00
parent d15c63effc
commit 999eec5617
2 changed files with 10 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/ast/genrtlil.cc
View file

@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column);
wire->is_signed = that->is_signed;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)