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Squelch a little more trailing whitespace

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Larry Doolittle 2018-12-28 08:24:31 -08:00 committed by Clifford Wolf
parent 245724a504
commit 99706b3bf4
2 changed files with 4 additions and 4 deletions
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6
backends/simplec/test00_uut.v
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@ -3,12 +3,12 @@ module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y)); unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
assign z = a ^ b ^ c, w = z; assign z = a ^ b ^ c, w = z;
endmodule endmodule
module unit_x(input [31:0] a, b, c, output [31:0] x); module unit_x(input [31:0] a, b, c, output [31:0] x);
assign x = (a & b) | c; assign x = (a & b) | c;
endmodule endmodule
module unit_y(input [31:0] a, b, c, output [31:0] y); module unit_y(input [31:0] a, b, c, output [31:0] y);
assign y = a & (b | c); assign y = a & (b | c);
endmodule endmodule

2
tests/sva/basic01.sv
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@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
write <= ctrl; write <= ctrl;
ready <= write; ready <= write;
end end
a_rw: assert property ( @(posedge clock) !(read && write) ); a_rw: assert property ( @(posedge clock) !(read && write) );
`ifdef FAIL `ifdef FAIL
a_wr: assert property ( @(posedge clock) write |-> ready ); a_wr: assert property ( @(posedge clock) write |-> ready );