3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-03 12:51:23 +00:00

xaiger: do not promote output wires

This commit is contained in:
Eddie Hung 2019-11-26 19:03:02 -08:00
parent 739f530906
commit 99702efaba

View file

@ -155,11 +155,6 @@ struct XAigerWriter
if (wire->port_input) if (wire->port_input)
sigmap.add(wire); sigmap.add(wire);
// promote output wires
for (auto wire : module->wires())
if (wire->port_output)
sigmap.add(wire);
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count("\\init")) { if (wire->attributes.count("\\init")) {