mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-03 12:51:23 +00:00
xaiger: do not promote output wires
This commit is contained in:
parent
739f530906
commit
99702efaba
1 changed files with 0 additions and 5 deletions
|
@ -155,11 +155,6 @@ struct XAigerWriter
|
||||||
if (wire->port_input)
|
if (wire->port_input)
|
||||||
sigmap.add(wire);
|
sigmap.add(wire);
|
||||||
|
|
||||||
// promote output wires
|
|
||||||
for (auto wire : module->wires())
|
|
||||||
if (wire->port_output)
|
|
||||||
sigmap.add(wire);
|
|
||||||
|
|
||||||
for (auto wire : module->wires())
|
for (auto wire : module->wires())
|
||||||
{
|
{
|
||||||
if (wire->attributes.count("\\init")) {
|
if (wire->attributes.count("\\init")) {
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue