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tests: CXX may be e.g. gcc, so use CC and link stdc++ explicitly

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Charlotte 2023-06-28 11:51:28 +10:00 • committed by Marcelina Kościelnicka
parent 4e94f62116
commit 992a728ec7
2 changed files with 4 additions and 4 deletions
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4
frontends/ast/genrtlil.cc
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@ -700,7 +700,7 @@ struct AST_INTERNAL::ProcessGenerator
sstr << ast->str << "$" << ast->filename << ":" << ast->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
set_src_attr(cell, ast);
RTLIL::SigSpec triggers;
RTLIL::Const polarity;
@ -719,7 +719,7 @@ struct AST_INTERNAL::ProcessGenerator
cell->setPort(ID::TRG, triggers);
Wire *wire = current_module->addWire(sstr.str() + "_EN", 1);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
set_src_attr(wire, ast);
cell->setPort(ID::EN, wire);
proc->root_case.actions.push_back(SigSig(wire, false));