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Add comment on why we have to match for clock-enable/reset muxes

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Eddie Hung 2019-10-05 08:56:37 -07:00
parent ebb059896a
commit 991c2ca95b
3 changed files with 11 additions and 3 deletions
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5
passes/pmgen/xilinx_dsp.pmg
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@ -441,7 +441,10 @@ endcode
// ####################### // #######################
// Subpattern for matching against input registers, based on knowledge of the // Subpattern for matching against input registers, based on knowledge of the
// 'Q' input. // 'Q' input. Typically, identifying registers with clock-enable and reset
// capability would be a task would be handled by other Yosys passes such as
// dff2dffe, but since DSP inference happens much before this, these patterns
// have to be manually identified.
// At a high level: // At a high level:
// (1) Starting from a $dff cell that (partially or fully) drives the given // (1) Starting from a $dff cell that (partially or fully) drives the given
// 'Q' argument // 'Q' argument

4
passes/pmgen/xilinx_dsp_CREG.pmg
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@ -105,7 +105,9 @@ endcode
// ####################### // #######################
// Subpattern for matching against input registers, based on knowledge of the // Subpattern for matching against input registers, based on knowledge of the
// 'Q' input. // 'Q' input. Typically, this task would be handled by other Yosys passes
// such as dff2dffe, but since DSP inference happens much before this, these
// patterns have to be manually identified.
// At a high level: // At a high level:
// (1) Starting from a $dff cell that (partially or fully) drives the given // (1) Starting from a $dff cell that (partially or fully) drives the given
// 'Q' argument // 'Q' argument

5
passes/pmgen/xilinx_dsp_cascade.pmg
View file

@ -298,7 +298,10 @@ endcode
// ####################### // #######################
// Subpattern for matching against input registers, based on knowledge of the // Subpattern for matching against input registers, based on knowledge of the
// 'Q' input. // 'Q' input. Typically, identifying registers with clock-enable and reset
// capability would be a task would be handled by other Yosys passes such as
// dff2dffe, but since DSP inference happens much before this, these patterns
// have to be manually identified.
// At a high level: // At a high level:
// (1) Starting from a $dff cell that (partially or fully) drives the given // (1) Starting from a $dff cell that (partially or fully) drives the given
// 'Q' argument // 'Q' argument