From 6f7f71fe038cc95df77b5efbe978ce1af5e2997e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 9 Jan 2024 19:31:11 +0100 Subject: [PATCH 001/188] read_blif: Represent sequential elements with gate cells When reading the BLIF input, represent the native sequential elements with fine-grained cells like `$_FF_` instead of the coarse-grained cells like `$ff` which we were using up to now. There are two reasons for this: * The sequential elements in BLIF are always single-bit, so the gate cells are a better fit. * This makes it symmetrical to the BLIF backend which only understands the fine-grained cells, and only translates those to the native BLIF features. --- frontends/blif/blifparse.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index ebbe082a2..72f942425 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -352,17 +352,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto no_latch_clock; if (!strcmp(edge, "re")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "fe")) - cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); else if (!strcmp(edge, "ah")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "al")) - cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); else { no_latch_clock: if (dff_name.empty()) { - cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); + cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q)); } else { cell = module->addCell(NEW_ID, dff_name); cell->setPort(ID::D, blif_wire(d)); From 672c89498a1e21065b2d3624cb705134656783e5 Mon Sep 17 00:00:00 2001 From: Zapta Date: Sat, 2 Mar 2024 11:20:53 -0800 Subject: [PATCH 002/188] Added to the Show command a -wireshape flag. This allows to control the shape of wire nodes, for example, -wireshape plaintext. The motivation is to allow the user to reduce visual loads of wires. This does not change the default behavior of using a diamond shape. --- passes/cmds/show.cc | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 82b5c6bcf..9383aafcd 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -60,6 +60,7 @@ struct ShowWorker RTLIL::Module *module; uint32_t currentColor; bool genWidthLabels; + std::string wireshape; bool genSignedLabels; bool stretchIO; bool enumerateIds; @@ -429,16 +430,19 @@ struct ShowWorker std::map wires_on_demand; for (auto wire : module->selected_wires()) { - const char *shape = "diamond"; + std::string shape = wireshape; if (wire->port_input || wire->port_output) shape = "octagon"; + const bool is_borderless = (shape == "plaintext") || (shape == "plain") || (shape == "none"); if (wire->name.isPublic()) { std::string src_href; if (href && wire->attributes.count(ID::src) > 0) src_href = stringf(", href=\"%s\" ", escape(wire->attributes.at(ID::src).decode_string())); - fprintf(f, "n%d [ shape=%s, label=\"%s\", %s%s];\n", - id2num(wire->name), shape, findLabel(wire->name.str()), - nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(), + fprintf(f, "n%d [ shape=%s,%s label=\"%s\", %s%s];\n", + id2num(wire->name), shape.c_str(), is_borderless? " margin=0, width=0" : "", findLabel(wire->name.str()), + is_borderless + ? "color=\"none\", fontcolor=\"black\"" + : nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(), src_href.c_str()); if (wire->port_input) all_sources.insert(stringf("n%d", id2num(wire->name))); @@ -617,10 +621,10 @@ struct ShowWorker } ShowWorker(FILE *f, RTLIL::Design *design, std::vector &libs, uint32_t colorSeed, bool genWidthLabels, - bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href, + const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href, const std::vector> &color_selections, const std::vector> &label_selections, RTLIL::IdString colorattr) : - f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), + f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape), genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds), notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr) { @@ -708,6 +712,9 @@ struct ShowPass : public Pass { log(" Use the specified attribute to assign colors. A unique color is\n"); log(" assigned to each unique value of this attribute.\n"); log("\n"); + log(" -wireshape \n"); + log(" Use the specified shape for wire nodes. E.g. plaintext.\n"); + log("\n"); log(" -width\n"); log(" annotate buses with a label indicating the width of the bus.\n"); log("\n"); @@ -766,6 +773,7 @@ struct ShowPass : public Pass { std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : "."); #endif std::string viewer_exe; + std::string flag_wireshape = "diamond"; std::vector libfiles; std::vector libs; uint32_t colorSeed = 0; @@ -830,6 +838,10 @@ struct ShowPass : public Pass { format = args[++argidx]; continue; } + if (arg == "-wireshape" && argidx+1 < args.size()) { + flag_wireshape = args[++argidx]; + continue; + } if (arg == "-width") { flag_width= true; continue; @@ -912,7 +924,7 @@ struct ShowPass : public Pass { delete lib; log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); } - ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); + ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); fclose(f); for (auto lib : libs) From 1bf9530fcc0a83938c69ef95b8f960c2c930f74c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 6 Aug 2025 16:51:14 +1200 Subject: [PATCH 003/188] cutpoint_blackbox.ys: Add verific-style unknown module --- tests/various/cutpoint_blackbox.ys | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tests/various/cutpoint_blackbox.ys b/tests/various/cutpoint_blackbox.ys index ee479b968..61001d6b6 100644 --- a/tests/various/cutpoint_blackbox.ys +++ b/tests/various/cutpoint_blackbox.ys @@ -70,3 +70,20 @@ design -load gold select -read cutpoint.gate.sel # nothing in gold but not gate select -assert-none % %n + +# replacing the blackbox with a verific-style unknown module should work too +# (note this specific example loses the values of SOME_PARAM which would +# normally be retained by verific) +design -load hier +delete =bb +read_rtlil << EOT +attribute \blackbox 1 +module \bb + parameter \SOME_PARAM 0 + wire inout 3 \o + wire inout 2 \b + wire inout 1 \a +end +EOT +cutpoint -blackbox +check -assert From 4ac100fe137e79baf50363e94aa088854c21838f Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 6 Aug 2025 18:11:05 +1200 Subject: [PATCH 004/188] cutpoint: Track wire drivers Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`). If any bits of an inout port have a known driver, treat the port as an input. If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver. --- passes/sat/cutpoint.cc | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 485e44fd6..41fa9fac4 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -109,13 +109,43 @@ struct CutpointPass : public Pass { SigMap sigmap(module); pool cutpoint_bits; + pool wire_drivers; + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + if (cell->output(conn.first) && !cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + if (bit.wire) + wire_drivers.insert(bit); + + for (auto wire : module->wires()) + if (wire->port_input) + for (auto bit : sigmap(wire)) + wire_drivers.insert(bit); + for (auto cell : module->selected_cells()) { if (cell->type == ID($anyseq)) continue; log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); for (auto &conn : cell->connections()) { - if (cell->output(conn.first)) - module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); + if (cell->output(conn.first)) { + bool do_cut = true; + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + if (wire_drivers.count(bit)) { + log_debug(" Treating inout port '%s' as input.\n", id2cstr(conn.first)); + do_cut = false; + break; + } + + if (do_cut) { + module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); + if (cell->input(conn.first)) { + log_debug(" Treating inout port '%s' as output.\n", id2cstr(conn.first)); + for (auto bit : sigmap(conn.second)) + wire_drivers.insert(bit); + } + } + } } RTLIL::Cell *scopeinfo = nullptr; From af7d1d3f4f44c82986e70d7188f7fe24e85b5154 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 6 Aug 2025 18:11:35 +1200 Subject: [PATCH 005/188] cutpoint_blackbox.ys: Extra edge case --- tests/various/cutpoint_blackbox.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/various/cutpoint_blackbox.ys b/tests/various/cutpoint_blackbox.ys index 61001d6b6..1ba9a95df 100644 --- a/tests/various/cutpoint_blackbox.ys +++ b/tests/various/cutpoint_blackbox.ys @@ -87,3 +87,27 @@ end EOT cutpoint -blackbox check -assert + +# also concatenated signals, and signals between two inout ports +design -load hier +delete top =bb +read_verilog << EOT +module top(input [1:0] a, b, output [1:0] o); + wire [1:0] c, d, e; + bb #(.SOME_PARAM(1)) bb1 (.a ({a[0], e[1]}), .b (b), .o (c)); + bb #(.SOME_PARAM(2)) bb2 (.a ({c[1], a[0]}), .b (c), .o (d)); + wb wb1 (.a (a), .b (b), .o (e)); + some_mod some_inst (.a (c), .b (d), .c (e), .o (o)); +endmodule +EOT +read_rtlil << EOT +attribute \blackbox 1 +module \bb + parameter \SOME_PARAM 0 + wire inout 3 width 2 \o + wire inout 2 width 2 \b + wire inout 1 width 2 \a +end +EOT +cutpoint -blackbox +check -assert From c41ba912d887bf2bef09880efcff1bbabae18c34 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 19 Aug 2025 22:21:08 +0000 Subject: [PATCH 006/188] Support IdString parameters in stringf --- kernel/io.cc | 11 +++++++++++ kernel/io.h | 18 ++++++++++++++++-- tests/unit/kernel/ioTest.cc | 7 +++++++ 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/kernel/io.cc b/kernel/io.cc index ef73a3b3d..62cf6b7f4 100644 --- a/kernel/io.cc +++ b/kernel/io.cc @@ -575,6 +575,17 @@ void format_emit_string_view(std::string &result, std::string_view spec, int *dy format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, std::string(arg).c_str()); } +void format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const IdString &arg) +{ + if (spec == "%s") { + // Format checking will have guaranteed num_dynamic_ints == 0. + result += arg.c_str(); + return; + } + format_emit_stringf(result, spec, dynamic_ints, num_dynamic_ints, arg.c_str()); +} + void format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints, DynamicIntCount num_dynamic_ints, const void *arg) { diff --git a/kernel/io.h b/kernel/io.h index dafef8bfa..08c234d6e 100644 --- a/kernel/io.h +++ b/kernel/io.h @@ -8,6 +8,10 @@ YOSYS_NAMESPACE_BEGIN +namespace RTLIL { + struct IdString; +} + inline std::string vstringf(const char *fmt, va_list ap) { // For the common case of strings shorter than 128, save a heap @@ -240,7 +244,8 @@ constexpr void check_format(std::string_view fmt, int fmt_start, bool *has_escap case CONVSPEC_CHAR_PTR: if constexpr (!std::is_convertible_v && !std::is_convertible_v && - !std::is_convertible_v) { + !std::is_convertible_v && + !std::is_convertible_v) { YOSYS_ABORT("Expected type convertible to char *"); } *specs = found; @@ -279,6 +284,10 @@ void format_emit_string(std::string &result, std::string_view spec, int *dynamic void format_emit_string_view(std::string &result, std::string_view spec, int *dynamic_ints, DynamicIntCount num_dynamic_ints, std::string_view arg); +// Emit the string representation of `arg` that has been converted to a `RTLIL::IdString'. +void format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints, + DynamicIntCount num_dynamic_ints, const RTLIL::IdString &arg); + // Emit the string representation of `arg` that has been converted to a `double'. void format_emit_void_ptr(std::string &result, std::string_view spec, int *dynamic_ints, DynamicIntCount num_dynamic_ints, const void *arg); @@ -329,6 +338,11 @@ inline void format_emit_one(std::string &result, std::string_view fmt, const Fou format_emit_string_view(result, spec, dynamic_ints, num_dynamic_ints, s); return; } + if constexpr (std::is_convertible_v) { + const RTLIL::IdString &s = arg; + format_emit_idstring(result, spec, dynamic_ints, num_dynamic_ints, s); + return; + } break; case CONVSPEC_VOID_PTR: if constexpr (std::is_convertible_v) { @@ -433,7 +447,7 @@ template struct WrapType { using type = T; }; template using TypeIdentity = typename WrapType::type; template -inline std::string stringf(FmtString...> fmt, Args... args) +inline std::string stringf(FmtString...> fmt, const Args &... args) { return fmt.format(args...); } diff --git a/tests/unit/kernel/ioTest.cc b/tests/unit/kernel/ioTest.cc index 43a71eb79..6186c34cb 100644 --- a/tests/unit/kernel/ioTest.cc +++ b/tests/unit/kernel/ioTest.cc @@ -1,6 +1,7 @@ #include #include "kernel/io.h" +#include "kernel/rtlil.h" YOSYS_NAMESPACE_BEGIN @@ -44,6 +45,12 @@ TEST(KernelStringfTest, stringViewParam) EXPECT_EQ(stringf("%s", std::string_view("hello")), "hello"); } +TEST(KernelStringfTest, idStringParam) +{ + RTLIL::IdString id("$hello"); + EXPECT_EQ(stringf("%s", id), "$hello"); +} + TEST(KernelStringfTest, escapePercent) { EXPECT_EQ(stringf("%%"), "%"); From c7df6954b98b7c6d58513dbd2c5a0afd7e6ede52 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 19 Aug 2025 22:45:26 +0000 Subject: [PATCH 007/188] Remove .c_str() from stringf parameters --- backends/blif/blif.cc | 50 +-- backends/edif/edif.cc | 12 +- backends/firrtl/firrtl.cc | 64 ++-- backends/jny/jny.cc | 16 +- backends/json/json.cc | 28 +- backends/rtlil/rtlil_backend.cc | 68 ++-- backends/smt2/smt2.cc | 64 ++-- backends/smv/smv.cc | 50 +-- backends/verilog/verilog_backend.cc | 414 +++++++++++----------- frontends/aiger/aigerparse.cc | 14 +- frontends/ast/ast.cc | 4 +- frontends/ast/genrtlil.cc | 16 +- frontends/ast/simplify.cc | 32 +- frontends/rpc/rpc_frontend.cc | 2 +- frontends/verific/verific.cc | 10 +- frontends/verific/verificsva.cc | 4 +- frontends/verilog/preproc.cc | 2 +- frontends/verilog/verilog_parser.y | 2 +- kernel/fstdata.cc | 4 +- kernel/io.cc | 4 +- kernel/log.cc | 2 +- kernel/mem.cc | 14 +- kernel/rtlil.cc | 2 +- kernel/satgen.h | 2 +- kernel/tclapi.cc | 2 +- kernel/yosys.cc | 6 +- libs/subcircuit/subcircuit.cc | 4 +- passes/cmds/bugpoint.cc | 12 +- passes/cmds/check.cc | 12 +- passes/cmds/dft_tag.cc | 10 +- passes/cmds/glift.cc | 10 +- passes/cmds/portarcs.cc | 2 +- passes/cmds/rename.cc | 8 +- passes/cmds/show.cc | 30 +- passes/cmds/stat.cc | 10 +- passes/cmds/timeest.cc | 4 +- passes/cmds/viz.cc | 14 +- passes/cmds/wrapcell.cc | 4 +- passes/cmds/xprop.cc | 8 +- passes/fsm/fsm_extract.cc | 4 +- passes/hierarchy/flatten.cc | 4 +- passes/hierarchy/submod.cc | 2 +- passes/memory/memory_bram.cc | 2 +- passes/memory/memory_libmap.cc | 18 +- passes/memory/memory_map.cc | 2 +- passes/opt/opt_expr.cc | 4 +- passes/proc/proc_mux.cc | 2 +- passes/sat/clk2fflogic.cc | 6 +- passes/sat/cutpoint.cc | 2 +- passes/sat/eval.cc | 2 +- passes/sat/fmcombine.cc | 2 +- passes/sat/freduce.cc | 4 +- passes/sat/mutate.cc | 4 +- passes/sat/qbfsat.cc | 6 +- passes/sat/recover_names.cc | 4 +- passes/sat/sim.cc | 50 +-- passes/techmap/abc.cc | 38 +- passes/techmap/abc9.cc | 20 +- passes/techmap/abc9_exe.cc | 32 +- passes/techmap/abc9_ops.cc | 12 +- passes/techmap/abc_new.cc | 6 +- passes/techmap/booth.cc | 2 +- passes/techmap/dfflibmap.cc | 4 +- passes/techmap/extract.cc | 2 +- passes/techmap/techmap.cc | 14 +- passes/tests/test_autotb.cc | 66 ++-- passes/tests/test_cell.cc | 26 +- techlibs/achronix/synth_achronix.cc | 2 +- techlibs/anlogic/synth_anlogic.cc | 6 +- techlibs/common/prep.cc | 2 +- techlibs/common/synth.cc | 6 +- techlibs/coolrunner2/synth_coolrunner2.cc | 4 +- techlibs/easic/synth_easic.cc | 16 +- techlibs/ecp5/synth_ecp5.cc | 10 +- techlibs/efinix/synth_efinix.cc | 6 +- techlibs/fabulous/synth_fabulous.cc | 6 +- techlibs/gatemate/synth_gatemate.cc | 6 +- techlibs/gowin/synth_gowin.cc | 4 +- techlibs/greenpak4/synth_greenpak4.cc | 4 +- techlibs/ice40/ice40_wrapcarry.cc | 4 +- techlibs/ice40/synth_ice40.cc | 12 +- techlibs/intel/synth_intel.cc | 10 +- techlibs/intel_alm/synth_intel_alm.cc | 20 +- techlibs/lattice/synth_lattice.cc | 10 +- techlibs/microchip/synth_microchip.cc | 8 +- techlibs/nanoxplore/synth_nanoxplore.cc | 8 +- techlibs/nexus/synth_nexus.cc | 10 +- techlibs/quicklogic/synth_quicklogic.cc | 14 +- techlibs/sf2/synth_sf2.cc | 8 +- techlibs/xilinx/synth_xilinx.cc | 14 +- 90 files changed, 773 insertions(+), 773 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 5a5b9219f..1ce1ac955 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -157,14 +157,14 @@ struct BlifDumper f << stringf("%c", ch); f << stringf("\"\n"); } else - f << stringf("%s\n", param.second.as_string().c_str()); + f << stringf("%s\n", param.second.as_string()); } } void dump() { f << stringf("\n"); - f << stringf(".model %s\n", str(module->name).c_str()); + f << stringf(".model %s\n", str(module->name)); std::map inputs, outputs; @@ -179,7 +179,7 @@ struct BlifDumper for (auto &it : inputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str()); + f << stringf(" %s", str(RTLIL::SigSpec(wire, i))); } f << stringf("\n"); @@ -187,7 +187,7 @@ struct BlifDumper for (auto &it : outputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str()); + f << stringf(" %s", str(RTLIL::SigSpec(wire, i))); } f << stringf("\n"); @@ -200,7 +200,7 @@ struct BlifDumper if (!config->impltf_mode) { if (!config->false_type.empty()) { if (config->false_type == "+") - f << stringf(".names %s\n", config->false_out.c_str()); + f << stringf(".names %s\n", config->false_out); else if (config->false_type != "-") f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type), config->false_type.c_str(), config->false_out.c_str()); @@ -208,7 +208,7 @@ struct BlifDumper f << stringf(".names $false\n"); if (!config->true_type.empty()) { if (config->true_type == "+") - f << stringf(".names %s\n1\n", config->true_out.c_str()); + f << stringf(".names %s\n1\n", config->true_out); else if (config->true_type != "-") f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type), config->true_type.c_str(), config->true_out.c_str()); @@ -216,7 +216,7 @@ struct BlifDumper f << stringf(".names $true\n1\n"); if (!config->undef_type.empty()) { if (config->undef_type == "+") - f << stringf(".names %s\n", config->undef_out.c_str()); + f << stringf(".names %s\n", config->undef_out); else if (config->undef_type != "-") f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type), config->undef_type.c_str(), config->undef_out.c_str()); @@ -331,31 +331,31 @@ struct BlifDumper } if (!config->icells_mode && cell->type == ID($_FF_)) { - f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(), + f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), str_init(cell->getPort(ID::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DFF_N_)) { - f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(), + f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DFF_P_)) { - f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(), + f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) { - f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(), + f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); goto internal_cell; } if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) { - f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(), + f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)), str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str()); goto internal_cell; } @@ -366,10 +366,10 @@ struct BlifDumper auto width = cell->parameters.at(ID::WIDTH).as_int(); log_assert(inputs.size() == width); for (int i = width-1; i >= 0; i--) - f << stringf(" %s", str(inputs.extract(i, 1)).c_str()); + f << stringf(" %s", str(inputs.extract(i, 1))); auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); - f << stringf(" %s", str(output).c_str()); + f << stringf(" %s", str(output)); f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at(ID::LUT); for (int i = 0; i < (1 << width); i++) @@ -392,10 +392,10 @@ struct BlifDumper table.push_back(State::S0); log_assert(inputs.size() == width); for (int i = 0; i < width; i++) - f << stringf(" %s", str(inputs.extract(i, 1)).c_str()); + f << stringf(" %s", str(inputs.extract(i, 1))); auto &output = cell->getPort(ID::Y); log_assert(output.size() == 1); - f << stringf(" %s", str(output).c_str()); + f << stringf(" %s", str(output)); f << stringf("\n"); for (int i = 0; i < depth; i++) { for (int j = 0; j < width; j++) { @@ -410,11 +410,11 @@ struct BlifDumper goto internal_cell; } - f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type).c_str()); + f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type)); for (auto &conn : cell->connections()) { if (conn.second.size() == 1) { - f << stringf(" %s=%s", str(conn.first).c_str(), str(conn.second[0]).c_str()); + f << stringf(" %s=%s", str(conn.first), str(conn.second[0])); continue; } @@ -423,11 +423,11 @@ struct BlifDumper if (w == nullptr) { for (int i = 0; i < GetSize(conn.second); i++) - f << stringf(" %s[%d]=%s", str(conn.first).c_str(), i, str(conn.second[i]).c_str()); + f << stringf(" %s[%d]=%s", str(conn.first), i, str(conn.second[i])); } else { for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) { SigBit sig(w, i); - f << stringf(" %s[%d]=%s", str(conn.first).c_str(), sig.wire->upto ? + f << stringf(" %s[%d]=%s", str(conn.first), sig.wire->upto ? sig.wire->start_offset+sig.wire->width-sig.offset-1 : sig.wire->start_offset+sig.offset, str(conn.second[i]).c_str()); } @@ -436,7 +436,7 @@ struct BlifDumper f << stringf("\n"); if (config->cname_mode) - f << stringf(".cname %s\n", str(cell->name).c_str()); + f << stringf(".cname %s\n", str(cell->name)); if (config->attr_mode) dump_params(".attr", cell->attributes); if (config->param_mode) @@ -445,7 +445,7 @@ struct BlifDumper if (0) { internal_cell: if (config->iname_mode) - f << stringf(".cname %s\n", str(cell->name).c_str()); + f << stringf(".cname %s\n", str(cell->name)); if (config->iattr_mode) dump_params(".attr", cell->attributes); } @@ -461,12 +461,12 @@ struct BlifDumper continue; if (config->conn_mode) - f << stringf(".conn %s %s\n", str(rhs_bit).c_str(), str(lhs_bit).c_str()); + f << stringf(".conn %s %s\n", str(rhs_bit), str(lhs_bit)); else if (!config->buf_type.empty()) - f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type.c_str(), + f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type, config->buf_in.c_str(), str(rhs_bit).c_str(), config->buf_out.c_str(), str(lhs_bit).c_str()); else - f << stringf(".names %s %s\n1 1\n", str(rhs_bit).c_str(), str(lhs_bit).c_str()); + f << stringf(".names %s %s\n1 1\n", str(rhs_bit), str(lhs_bit)); } f << stringf(".end\n"); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 581590287..cda017059 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -48,8 +48,8 @@ struct EdifNames if (define) { std::string new_id = operator()(id, false); if (port_rename) - return stringf("(rename %s \"%s%c%d:%d%c\")", new_id.c_str(), id.c_str(), delim_left, range_left, range_right, delim_right); - return new_id != id ? stringf("(rename %s \"%s\")", new_id.c_str(), id.c_str()) : id; + return stringf("(rename %s \"%s%c%d:%d%c\")", new_id, id, delim_left, range_left, range_right, delim_right); + return new_id != id ? stringf("(rename %s \"%s\")", new_id, id) : id; } if (name_map.count(id) > 0) @@ -334,7 +334,7 @@ struct EdifBackend : public Backend { auto add_prop = [&](IdString name, Const val) { if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0) - *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str()); + *f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string()); else if (val.size() <= 32 && RTLIL::SigSpec(val).is_fully_def()) *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int()); else { @@ -348,7 +348,7 @@ struct EdifBackend : public Backend { char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; hex_string = std::string(digit_str) + hex_string; } - *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val), hex_string.c_str()); + *f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val), hex_string); } }; for (auto module : sorted_modules) @@ -536,7 +536,7 @@ struct EdifBackend : public Backend { } *f << stringf(" (net %s (joined\n", EDIF_DEF(netname)); for (auto &ref : it.second) - *f << stringf(" %s\n", ref.first.c_str()); + *f << stringf(" %s\n", ref.first); if (sig.wire == NULL) { if (nogndvcc) log_error("Design contains constant nodes (map with \"hilomap\" first).\n"); @@ -577,7 +577,7 @@ struct EdifBackend : public Backend { auto &refs = net_join_db.at(mapped_sig); for (auto &ref : refs) if (ref.second) - *f << stringf(" %s\n", ref.first.c_str()); + *f << stringf(" %s\n", ref.first); *f << stringf(" )"); if (attr_properties && raw_sig.wire != NULL) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 7c9feebb1..cda3d4618 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -565,12 +565,12 @@ struct FirrtlWorker { if (wire->port_input && wire->port_output) log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire)); - port_decls.push_back(stringf("%s%s %s: UInt<%d> %s\n", indent.c_str(), wire->port_input ? "input" : "output", + port_decls.push_back(stringf("%s%s %s: UInt<%d> %s\n", indent, wire->port_input ? "input" : "output", wireName, wire->width, wireFileinfo.c_str())); } else { - wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), wireName, wire->width, wireFileinfo.c_str())); + wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, wireName, wire->width, wireFileinfo)); } } @@ -885,7 +885,7 @@ struct FirrtlWorker string a_expr = make_expr(cell->getPort(ID::A)); string b_expr = make_expr(cell->getPort(ID::B)); string s_expr = make_expr(cell->getPort(ID::S)); - wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent.c_str(), y_id.c_str(), width, cellFileinfo.c_str())); + wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, width, cellFileinfo)); string expr = stringf("mux(%s, %s, %s)", s_expr, b_expr, a_expr); @@ -926,7 +926,7 @@ struct FirrtlWorker string a_expr = make_expr(cell->getPort(ID::A)); // Get the initial bit selector string b_expr = make_expr(cell->getPort(ID::B)); - wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width)); + wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); if (cell->getParam(ID::B_SIGNED).as_bool()) { // Use validif to constrain the selection (test the sign bit) @@ -936,7 +936,7 @@ struct FirrtlWorker } string expr = stringf("dshr(%s, %s)", a_expr, b_expr); - cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str())); + cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr)); register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -948,21 +948,21 @@ struct FirrtlWorker string b_expr = make_expr(cell->getPort(ID::B)); auto b_string = b_expr.c_str(); string expr; - wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width)); + wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); if (cell->getParam(ID::B_SIGNED).as_bool()) { // We generate a left or right shift based on the sign of b. - std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width); - std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); + std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr, gen_dshl(b_expr, b_width), y_width); + std::string dshr = stringf("dshr(%s, %s)", a_expr, b_string); expr = stringf("mux(%s < 0, %s, %s)", b_string, dshl.c_str(), dshr.c_str() ); } else { - expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); + expr = stringf("dshr(%s, %s)", a_expr, b_string); } - cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str())); + cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr)); register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -975,8 +975,8 @@ struct FirrtlWorker if (a_width < y_width) { a_expr = stringf("pad(%s, %d)", a_expr, y_width); } - wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width)); - cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), a_expr.c_str())); + wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); + cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr)); register_reverse_wire_map(y_id, cell->getPort(ID::Y)); continue; } @@ -999,7 +999,7 @@ struct FirrtlWorker for (int i = 0; i < GetSize(mem.rd_ports); i++) { auto &port = mem.rd_ports[i]; - string port_name(stringf("%s.r%d", mem_id.c_str(), i)); + string port_name(stringf("%s.r%d", mem_id, i)); if (port.clk_enable) log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); @@ -1010,17 +1010,17 @@ struct FirrtlWorker string ena_expr = make_expr(State::S1); string clk_expr = make_expr(State::S0); - rpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str()); - rpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str()); - rpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str()); + rpe << stringf("%s%s.addr <= %s\n", indent, port_name, addr_expr); + rpe << stringf("%s%s.en <= %s\n", indent, port_name, ena_expr); + rpe << stringf("%s%s.clk <= asClock(%s)\n", indent, port_name, clk_expr); cell_exprs.push_back(rpe.str()); - register_reverse_wire_map(stringf("%s.data", port_name.c_str()), port.data); + register_reverse_wire_map(stringf("%s.data", port_name), port.data); } for (int i = 0; i < GetSize(mem.wr_ports); i++) { auto &port = mem.wr_ports[i]; - string port_name(stringf("%s.w%d", mem_id.c_str(), i)); + string port_name(stringf("%s.w%d", mem_id, i)); if (!port.clk_enable) log_error("Unclocked write port %d on memory %s.%s.\n", i, log_id(module), log_id(mem.memid)); @@ -1037,18 +1037,18 @@ struct FirrtlWorker string ena_expr = make_expr(port.en[0]); string clk_expr = make_expr(port.clk); string mask_expr = make_expr(State::S1); - wpe << stringf("%s%s.data <= %s\n", indent.c_str(), port_name.c_str(), data_expr.c_str()); - wpe << stringf("%s%s.addr <= %s\n", indent.c_str(), port_name.c_str(), addr_expr.c_str()); - wpe << stringf("%s%s.en <= %s\n", indent.c_str(), port_name.c_str(), ena_expr.c_str()); - wpe << stringf("%s%s.clk <= asClock(%s)\n", indent.c_str(), port_name.c_str(), clk_expr.c_str()); - wpe << stringf("%s%s.mask <= %s\n", indent.c_str(), port_name.c_str(), mask_expr.c_str()); + wpe << stringf("%s%s.data <= %s\n", indent, port_name, data_expr); + wpe << stringf("%s%s.addr <= %s\n", indent, port_name, addr_expr); + wpe << stringf("%s%s.en <= %s\n", indent, port_name, ena_expr); + wpe << stringf("%s%s.clk <= asClock(%s)\n", indent, port_name, clk_expr); + wpe << stringf("%s%s.mask <= %s\n", indent, port_name, mask_expr); cell_exprs.push_back(wpe.str()); } std::ostringstream me; - me << stringf(" mem %s:\n", mem_id.c_str()); + me << stringf(" mem %s:\n", mem_id); me << stringf(" data-type => UInt<%d>\n", mem.width); me << stringf(" depth => %d\n", mem.size); for (int i = 0; i < GetSize(mem.rd_ports); i++) @@ -1068,8 +1068,8 @@ struct FirrtlWorker int y_width = GetSize(conn.first); string expr = make_expr(conn.second); - wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent.c_str(), y_id.c_str(), y_width)); - cell_exprs.push_back(stringf("%s%s <= %s\n", indent.c_str(), y_id.c_str(), expr.c_str())); + wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width)); + cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr)); register_reverse_wire_map(y_id, conn.first); } @@ -1112,7 +1112,7 @@ struct FirrtlWorker chunk_width++; } - new_expr = stringf("bits(%s, %d, %d)", start_map.first.c_str(), + new_expr = stringf("bits(%s, %d, %d)", start_map.first, start_map.second + chunk_width - 1, start_map.second); is_valid = true; } @@ -1135,13 +1135,13 @@ struct FirrtlWorker if (is_valid) { if (make_unconn_id) { - wire_decls.push_back(stringf("%swire %s: UInt<1> %s\n", indent.c_str(), unconn_id.c_str(), wireFileinfo.c_str())); + wire_decls.push_back(stringf("%swire %s: UInt<1> %s\n", indent, unconn_id, wireFileinfo)); // `invalid` is a firrtl construction for simulation so we will not // tag it with a @[fileinfo] tag as it doesn't directly correspond to // a specific line of verilog code. - wire_decls.push_back(stringf("%s%s is invalid\n", indent.c_str(), unconn_id.c_str())); + wire_decls.push_back(stringf("%s%s is invalid\n", indent, unconn_id)); } - wire_exprs.push_back(stringf("%s%s <= %s %s\n", indent.c_str(), make_id(wire->name), expr.c_str(), wireFileinfo.c_str())); + wire_exprs.push_back(stringf("%s%s <= %s %s\n", indent, make_id(wire->name), expr, wireFileinfo)); } else { if (make_unconn_id) { unconn_id.clear(); @@ -1149,7 +1149,7 @@ struct FirrtlWorker // `invalid` is a firrtl construction for simulation so we will not // tag it with a @[fileinfo] tag as it doesn't directly correspond to // a specific line of verilog code. - wire_decls.push_back(stringf("%s%s is invalid\n", indent.c_str(), make_id(wire->name))); + wire_decls.push_back(stringf("%s%s is invalid\n", indent, make_id(wire->name))); } } @@ -1249,7 +1249,7 @@ struct FirrtlBackend : public Backend { log_cmd_error("There is no top module in this design!\n"); std::string circuitFileinfo = getFileinfo(top); - *f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str()); + *f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo); emit_elaborated_extmodules(design, *f); diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 4aacb4e20..001492e40 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -125,7 +125,7 @@ struct JnyWriter f << "{\n"; f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n"; - f << stringf(" \"generator\": \"%s\",\n", escape_string(yosys_maybe_version()).c_str()); + f << stringf(" \"generator\": \"%s\",\n", escape_string(yosys_maybe_version())); f << " \"version\": \"0.0.1\",\n"; f << " \"invocation\": \"" << escape_string(invk) << "\",\n"; f << " \"features\": ["; @@ -232,7 +232,7 @@ struct JnyWriter const auto _indent = gen_indent(indent_level); f << _indent << "{\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent.c_str(), escape_string(RTLIL::unescape_id(mod->name)).c_str()); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(RTLIL::unescape_id(mod->name))); f << _indent << " \"cell_sorts\": [\n"; bool first_sort{true}; @@ -280,7 +280,7 @@ struct JnyWriter f << ",\n"; f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent.c_str(), escape_string(RTLIL::unescape_id(con.first)).c_str()); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(RTLIL::unescape_id(con.first))); f << _indent << " \"direction\": \""; if (port_cell->input(con.first)) f << "i"; @@ -290,7 +290,7 @@ struct JnyWriter if (con.second.size() == 1) f << _indent << " \"range\": [0, 0]\n"; else - f << stringf(" %s\"range\": [%d, %d]\n", _indent.c_str(), con.second.size(), 0); + f << stringf(" %s\"range\": [%d, %d]\n", _indent, con.second.size(), 0); f << _indent << " }"; first_port = false; @@ -304,7 +304,7 @@ struct JnyWriter const auto _indent = gen_indent(indent_level); f << _indent << "{\n"; - f << stringf(" %s\"type\": \"%s\",\n", _indent.c_str(), sort.first.c_str()); + f << stringf(" %s\"type\": \"%s\",\n", _indent, sort.first); f << _indent << " \"ports\": [\n"; write_cell_ports(port_cell, indent_level + 2); @@ -351,10 +351,10 @@ struct JnyWriter f << stringf(",\n"); const auto param_val = param.second; if (!param_val.empty()) { - f << stringf(" %s\"%s\": ", _indent.c_str(), escape_string(RTLIL::unescape_id(param.first)).c_str()); + f << stringf(" %s\"%s\": ", _indent, escape_string(RTLIL::unescape_id(param.first))); write_param_val(param_val); } else { - f << stringf(" %s\"%s\": true", _indent.c_str(), escape_string(RTLIL::unescape_id(param.first)).c_str()); + f << stringf(" %s\"%s\": true", _indent, escape_string(RTLIL::unescape_id(param.first))); } first_param = false; @@ -366,7 +366,7 @@ struct JnyWriter log_assert(cell != nullptr); f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\"", _indent.c_str(), escape_string(RTLIL::unescape_id(cell->name)).c_str()); + f << stringf(" %s\"name\": \"%s\"", _indent, escape_string(RTLIL::unescape_id(cell->name))); if (_include_connections) { f << ",\n" << _indent << " \"connections\": [\n"; diff --git a/backends/json/json.cc b/backends/json/json.cc index 98e929dfa..f7b80d53d 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -135,7 +135,7 @@ struct JsonWriter bool first = true; for (auto ¶m : parameters) { f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s%s: ", for_module ? "" : " ", get_name(param.first).c_str()); + f << stringf(" %s%s: ", for_module ? "" : " ", get_name(param.first)); write_parameter_value(param.second); first = false; } @@ -155,7 +155,7 @@ struct JsonWriter log_error("Module %s contains processes, which are not supported by JSON backend (run `proc` first).\n", log_id(module)); } - f << stringf(" %s: {\n", get_name(module->name).c_str()); + f << stringf(" %s: {\n", get_name(module->name)); f << stringf(" \"attributes\": {"); write_parameters(module->attributes, /*for_module=*/true); @@ -174,7 +174,7 @@ struct JsonWriter if (use_selection && !module->selected(w)) continue; f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(n).c_str()); + f << stringf(" %s: {\n", get_name(n)); f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output"); if (w->start_offset) f << stringf(" \"offset\": %d,\n", w->start_offset); @@ -182,7 +182,7 @@ struct JsonWriter f << stringf(" \"upto\": 1,\n"); if (w->is_signed) f << stringf(" \"signed\": %d,\n", w->is_signed); - f << stringf(" \"bits\": %s\n", get_bits(w).c_str()); + f << stringf(" \"bits\": %s\n", get_bits(w)); f << stringf(" }"); first = false; } @@ -196,13 +196,13 @@ struct JsonWriter if (!scopeinfo_mode && c->type == ID($scopeinfo)) continue; f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(c->name).c_str()); + f << stringf(" %s: {\n", get_name(c->name)); f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0"); - f << stringf(" \"type\": %s,\n", get_name(c->type).c_str()); + f << stringf(" \"type\": %s,\n", get_name(c->type)); if (aig_mode) { Aig aig(c); if (!aig.name.empty()) { - f << stringf(" \"model\": \"%s\",\n", aig.name.c_str()); + f << stringf(" \"model\": \"%s\",\n", aig.name); aig_models.insert(aig); } } @@ -220,7 +220,7 @@ struct JsonWriter if (c->input(conn.first)) direction = c->output(conn.first) ? "inout" : "input"; f << stringf("%s\n", first2 ? "" : ","); - f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str()); + f << stringf(" %s: \"%s\"", get_name(conn.first), direction); first2 = false; } f << stringf("\n },\n"); @@ -229,7 +229,7 @@ struct JsonWriter bool first2 = true; for (auto &conn : c->connections()) { f << stringf("%s\n", first2 ? "" : ","); - f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str()); + f << stringf(" %s: %s", get_name(conn.first), get_bits(conn.second)); first2 = false; } f << stringf("\n }\n"); @@ -245,7 +245,7 @@ struct JsonWriter if (use_selection && !module->selected(it.second)) continue; f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(it.second->name).c_str()); + f << stringf(" %s: {\n", get_name(it.second->name)); f << stringf(" \"hide_name\": %s,\n", it.second->name[0] == '$' ? "1" : "0"); f << stringf(" \"attributes\": {"); write_parameters(it.second->attributes); @@ -265,9 +265,9 @@ struct JsonWriter if (use_selection && !module->selected(w)) continue; f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(w->name).c_str()); + f << stringf(" %s: {\n", get_name(w->name)); f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0"); - f << stringf(" \"bits\": %s,\n", get_bits(w).c_str()); + f << stringf(" \"bits\": %s,\n", get_bits(w)); if (w->start_offset) f << stringf(" \"offset\": %d,\n", w->start_offset); if (w->upto) @@ -291,7 +291,7 @@ struct JsonWriter design->sort(); f << stringf("{\n"); - f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version()).c_str()); + f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version())); f << stringf(" \"modules\": {\n"); vector modules = use_selection ? design->selected_modules() : design->modules(); bool first_module = true; @@ -308,7 +308,7 @@ struct JsonWriter for (auto &aig : aig_models) { if (!first_model) f << stringf(",\n"); - f << stringf(" \"%s\": [\n", aig.name.c_str()); + f << stringf(" \"%s\": [\n", aig.name); int node_idx = 0; for (auto &node : aig.nodes) { if (node_idx != 0) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index adde37356..215e0d366 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -96,11 +96,11 @@ void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, dump_const(f, chunk.data, chunk.width, chunk.offset, autoint); } else { if (chunk.width == chunk.wire->width && chunk.offset == 0) - f << stringf("%s", chunk.wire->name.c_str()); + f << stringf("%s", chunk.wire->name); else if (chunk.width == 1) - f << stringf("%s [%d]", chunk.wire->name.c_str(), chunk.offset); + f << stringf("%s [%d]", chunk.wire->name, chunk.offset); else - f << stringf("%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset); + f << stringf("%s [%d:%d]", chunk.wire->name, chunk.offset+chunk.width-1, chunk.offset); } } @@ -121,15 +121,15 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { for (auto &it : wire->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); + f << stringf("%s" "attribute %s ", indent, it.first); dump_const(f, it.second); f << stringf("\n"); } if (wire->driverCell_) { - f << stringf("%s" "# driver %s %s\n", indent.c_str(), + f << stringf("%s" "# driver %s %s\n", indent, wire->driverCell()->name.c_str(), wire->driverPort().c_str()); } - f << stringf("%s" "wire ", indent.c_str()); + f << stringf("%s" "wire ", indent); if (wire->width != 1) f << stringf("width %d ", wire->width); if (wire->upto) @@ -144,36 +144,36 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: f << stringf("inout %d ", wire->port_id); if (wire->is_signed) f << stringf("signed "); - f << stringf("%s\n", wire->name.c_str()); + f << stringf("%s\n", wire->name); } void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { for (auto &it : memory->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); + f << stringf("%s" "attribute %s ", indent, it.first); dump_const(f, it.second); f << stringf("\n"); } - f << stringf("%s" "memory ", indent.c_str()); + f << stringf("%s" "memory ", indent); if (memory->width != 1) f << stringf("width %d ", memory->width); if (memory->size != 0) f << stringf("size %d ", memory->size); if (memory->start_offset != 0) f << stringf("offset %d ", memory->start_offset); - f << stringf("%s\n", memory->name.c_str()); + f << stringf("%s\n", memory->name); } void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { for (auto &it : cell->attributes) { - f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); + f << stringf("%s" "attribute %s ", indent, it.first); dump_const(f, it.second); f << stringf("\n"); } - f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str()); + f << stringf("%s" "cell %s %s\n", indent, cell->type, cell->name); for (auto &it : cell->parameters) { - f << stringf("%s parameter%s%s %s ", indent.c_str(), + f << stringf("%s parameter%s%s %s ", indent, (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", it.first.c_str()); @@ -181,18 +181,18 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } for (auto &it : cell->connections()) { - f << stringf("%s connect %s ", indent.c_str(), it.first.c_str()); + f << stringf("%s connect %s ", indent, it.first); dump_sigspec(f, it.second); f << stringf("\n"); } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, it->first); f << stringf(" "); dump_sigspec(f, it->second); @@ -206,23 +206,23 @@ void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, con void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); + f << stringf("%s" "attribute %s ", indent, it->first); dump_const(f, it->second); f << stringf("\n"); } - f << stringf("%s" "switch ", indent.c_str()); + f << stringf("%s" "switch ", indent); dump_sigspec(f, sw->signal); f << stringf("\n"); for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) { - f << stringf("%s attribute %s ", indent.c_str(), ait->first.c_str()); + f << stringf("%s attribute %s ", indent, ait->first); dump_const(f, ait->second); f << stringf("\n"); } - f << stringf("%s case ", indent.c_str()); + f << stringf("%s case ", indent); for (size_t i = 0; i < (*it)->compare.size(); i++) { if (i > 0) f << stringf(" , "); @@ -233,12 +233,12 @@ void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const dump_proc_case_body(f, indent + " ", *it); } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy) { - f << stringf("%s" "sync ", indent.c_str()); + f << stringf("%s" "sync ", indent); switch (sy->type) { case RTLIL::ST0: f << stringf("low "); if (0) case RTLIL::ST1: f << stringf("high "); @@ -254,7 +254,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT } for (auto &it: sy->actions) { - f << stringf("%s update ", indent.c_str()); + f << stringf("%s update ", indent); dump_sigspec(f, it.first); f << stringf(" "); dump_sigspec(f, it.second); @@ -263,11 +263,11 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT for (auto &it: sy->mem_write_actions) { for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) { - f << stringf("%s attribute %s ", indent.c_str(), it2->first.c_str()); + f << stringf("%s attribute %s ", indent, it2->first); dump_const(f, it2->second); f << stringf("\n"); } - f << stringf("%s memwr %s ", indent.c_str(), it.memid.c_str()); + f << stringf("%s memwr %s ", indent, it.memid); dump_sigspec(f, it.address); f << stringf(" "); dump_sigspec(f, it.data); @@ -282,20 +282,20 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); + f << stringf("%s" "attribute %s ", indent, it->first); dump_const(f, it->second); f << stringf("\n"); } - f << stringf("%s" "process %s\n", indent.c_str(), proc->name.c_str()); + f << stringf("%s" "process %s\n", indent, proc->name); dump_proc_case_body(f, indent + " ", &proc->root_case); for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it) dump_proc_sync(f, indent + " ", *it); - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { - f << stringf("%s" "connect ", indent.c_str()); + f << stringf("%s" "connect ", indent); dump_sigspec(f, left); f << stringf(" "); dump_sigspec(f, right); @@ -310,12 +310,12 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_header) { for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str()); + f << stringf("%s" "attribute %s ", indent, it->first); dump_const(f, it->second); f << stringf("\n"); } - f << stringf("%s" "module %s\n", indent.c_str(), module->name.c_str()); + f << stringf("%s" "module %s\n", indent, module->name); if (!module->avail_parameters.empty()) { if (only_selected) @@ -323,9 +323,9 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu for (const auto &p : module->avail_parameters) { const auto &it = module->parameter_default_values.find(p); if (it == module->parameter_default_values.end()) { - f << stringf("%s" " parameter %s\n", indent.c_str(), p.c_str()); + f << stringf("%s" " parameter %s\n", indent, p); } else { - f << stringf("%s" " parameter %s ", indent.c_str(), p.c_str()); + f << stringf("%s" " parameter %s ", indent, p); dump_const(f, it->second); f << stringf("\n"); } @@ -385,7 +385,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu } if (print_header) - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 87f5a08c8..089e73715 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -82,27 +82,27 @@ struct Smt2Worker if (statebv) { if (width == 0) { - decl_str = stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name.c_str(), get_id(module), statebv_width, statebv_width); + decl_str = stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name, get_id(module), statebv_width, statebv_width); statebv_width += 1; } else { - decl_str = stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name.c_str(), get_id(module), width, statebv_width+width-1, statebv_width); + decl_str = stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name, get_id(module), width, statebv_width+width-1, statebv_width); statebv_width += width; } } else if (statedt) { if (width == 0) { - decl_str = stringf(" (|%s| Bool)", name.c_str()); + decl_str = stringf(" (|%s| Bool)", name); } else { - decl_str = stringf(" (|%s| (_ BitVec %d))", name.c_str(), width); + decl_str = stringf(" (|%s| (_ BitVec %d))", name, width); } } else { if (width == 0) { - decl_str = stringf("(declare-fun |%s| (|%s_s|) Bool)", name.c_str(), get_id(module)); + decl_str = stringf("(declare-fun |%s| (|%s_s|) Bool)", name, get_id(module)); } else { - decl_str = stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name.c_str(), get_id(module), width); + decl_str = stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name, get_id(module), width); } } @@ -383,7 +383,7 @@ struct Smt2Worker } if (fcache.count(sig[i]) && fcache.at(sig[i]).second == -1) { - subexpr.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig[i], state_name).c_str())); + subexpr.push_back(stringf("(ite %s #b1 #b0)", get_bool(sig[i], state_name))); continue; } @@ -495,7 +495,7 @@ struct Smt2Worker } if (width != GetSize(sig_y) && type != 'b') - processed_expr = stringf("((_ extract %d 0) %s)", GetSize(sig_y)-1, processed_expr.c_str()); + processed_expr = stringf("((_ extract %d 0) %s)", GetSize(sig_y)-1, processed_expr); if (verbose) log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", log_id(cell)); @@ -617,7 +617,7 @@ struct Smt2Worker string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell); if (cell->attributes.count(ID::reg)) infostr += " " + cell->attributes.at(ID::reg).decode_string(); - decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr.c_str())); + decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr)); if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str().c_str()); @@ -722,7 +722,7 @@ struct Smt2Worker 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) { bool is_and = cell->type == ID($reduce_and); string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0'); - return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b'); + return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b'); } if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true); @@ -746,7 +746,7 @@ struct Smt2Worker get_bv(sig_s); for (int i = 0; i < GetSize(sig_s); i++) - processed_expr = stringf("(ite %s %s %s)", get_bool(sig_s[i]).c_str(), + processed_expr = stringf("(ite %s %s %s)", get_bool(sig_s[i]), get_bv(sig_b.extract(i*width, width)).c_str(), processed_expr.c_str()); if (verbose) @@ -1090,13 +1090,13 @@ struct Smt2Worker use_mask = true; } if (use_mask) - init_list.push_back(stringf("(= (bvand %s #b%s) #b%s) ; %s", get_bv(sig).c_str(), mask.as_string().c_str(), val.as_string().c_str(), get_id(wire))); + init_list.push_back(stringf("(= (bvand %s #b%s) #b%s) ; %s", get_bv(sig), mask.as_string(), val.as_string(), get_id(wire))); else - init_list.push_back(stringf("(= %s #b%s) ; %s", get_bv(sig).c_str(), val.as_string().c_str(), get_id(wire))); + init_list.push_back(stringf("(= %s #b%s) ; %s", get_bv(sig), val.as_string(), get_id(wire))); } else { for (int i = 0; i < GetSize(sig); i++) if (val[i] == State::S0 || val[i] == State::S1) - init_list.push_back(stringf("(= %s %s) ; %s", get_bool(sig[i]).c_str(), val[i] == State::S1 ? "true" : "false", get_id(wire))); + init_list.push_back(stringf("(= %s %s) ; %s", get_bool(sig[i]), val[i] == State::S1 ? "true" : "false", get_id(wire))); } } @@ -1131,7 +1131,7 @@ struct Smt2Worker } if (private_name && cell->attributes.count(ID::src)) - decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), cell->attributes.at(ID::src).decode_string().c_str())); + decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), cell->attributes.at(ID::src).decode_string())); else decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell))); @@ -1180,11 +1180,11 @@ struct Smt2Worker SigSpec sig = sigmap(conn.second); if (bvmode || GetSize(w) == 1) { - hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(), + hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)), get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w))); } else { for (int i = 0; i < GetSize(w); i++) - hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(), + hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]), get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i)); } } @@ -1204,25 +1204,25 @@ struct Smt2Worker { std::string expr_d = get_bool(cell->getPort(ID::D)); std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q)))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)).c_str(), get_bool(cell->getPort(ID::Q), "other_state").c_str())); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)), get_bool(cell->getPort(ID::Q), "other_state"))); } if (cell->type.in(ID($ff), ID($dff), ID($anyinit))) { std::string expr_d = get_bv(cell->getPort(ID::D)); std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q)))); - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)).c_str(), get_bv(cell->getPort(ID::Q), "other_state").c_str())); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q)))); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)), get_bv(cell->getPort(ID::Q), "other_state"))); } if (cell->type.in(ID($anyconst), ID($allconst))) { std::string expr_d = get_bv(cell->getPort(ID::Y)); std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state"); - trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y)))); + trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Y)))); if (cell->type == ID($anyconst)) - ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str())); + ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)), get_bv(cell->getPort(ID::Y), "other_state"))); } } @@ -1341,11 +1341,11 @@ struct Smt2Worker std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, GetSize(mem->wr_ports)); std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid); - trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(mem->memid))); + trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d, expr_q, get_id(mem->memid))); ex_state_eq.push_back(stringf("(= (|%s#%d#0| state) (|%s#%d#0| other_state))", get_id(module), arrayid, get_id(module), arrayid)); if (has_async_wr) - hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(mem->memid))); + hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d, final_memstate, get_id(mem->memid))); Const init_data = mem->get_init_data(); @@ -1402,7 +1402,7 @@ struct Smt2Worker expr = "\n " + ex_state_eq.front() + "\n"; } else { for (auto &str : ex_state_eq) - expr += stringf("\n %s", str.c_str()); + expr += stringf("\n %s", str); expr += "\n)"; } } @@ -1415,7 +1415,7 @@ struct Smt2Worker expr = "\n " + ex_input_eq.front() + "\n"; } else { for (auto &str : ex_input_eq) - expr += stringf("\n %s", str.c_str()); + expr += stringf("\n %s", str); expr += "\n)"; } } @@ -1429,7 +1429,7 @@ struct Smt2Worker assert_expr = "\n " + assert_list.front() + "\n"; } else { for (auto &str : assert_list) - assert_expr += stringf("\n %s", str.c_str()); + assert_expr += stringf("\n %s", str); assert_expr += "\n)"; } } @@ -1442,7 +1442,7 @@ struct Smt2Worker assume_expr = "\n " + assume_list.front() + "\n"; } else { for (auto &str : assume_list) - assume_expr += stringf("\n %s", str.c_str()); + assume_expr += stringf("\n %s", str); assume_expr += "\n)"; } } @@ -1455,7 +1455,7 @@ struct Smt2Worker init_expr = "\n " + init_list.front() + "\n"; } else { for (auto &str : init_list) - init_expr += stringf("\n %s", str.c_str()); + init_expr += stringf("\n %s", str); init_expr += "\n)"; } } @@ -1846,7 +1846,7 @@ struct Smt2Backend : public Backend { *f << stringf("; yosys-smt2-stdt\n"); for (auto &it : solver_options) - *f << stringf("; yosys-smt2-solver-option %s %s\n", it.first.c_str(), it.second.c_str()); + *f << stringf("; yosys-smt2-solver-option %s %s\n", it.first, it.second); std::vector sorted_modules; @@ -1913,7 +1913,7 @@ struct Smt2Backend : public Backend { } if (topmod) - *f << stringf("; yosys-smt2-topmod %s\n", topmod_id.c_str()); + *f << stringf("; yosys-smt2-topmod %s\n", topmod_id); *f << stringf("; end of yosys output\n"); diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 1c2b2a224..55eadca00 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -59,7 +59,7 @@ struct SmvWorker { if (!idcache.count(id)) { - string name = stringf("_%s", id.c_str()); + string name = stringf("_%s", id); if (name.compare(0, 2, "_\\") == 0) name = "_" + name.substr(2); @@ -163,15 +163,15 @@ struct SmvWorker if (width >= 0) { if (is_signed) { if (GetSize(sig) > width) - s = stringf("signed(resize(%s, %d))", s.c_str(), width); + s = stringf("signed(resize(%s, %d))", s, width); else - s = stringf("resize(signed(%s), %d)", s.c_str(), width); + s = stringf("resize(signed(%s), %d)", s, width); } else - s = stringf("resize(%s, %d)", s.c_str(), width); + s = stringf("resize(%s, %d)", s, width); } else if (is_signed) - s = stringf("signed(%s)", s.c_str()); + s = stringf("signed(%s)", s); else if (count_chunks > 1) - s = stringf("(%s)", s.c_str()); + s = stringf("(%s)", s); strbuf.push_back(s); return strbuf.back().c_str(); @@ -262,7 +262,7 @@ struct SmvWorker if (cell->type == ID($sshr) && signed_a) { expr_a = rvalue_s(sig_a, width); - expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a.c_str(), op.c_str(), rvalue(sig_b.extract(0, shift_b_width)), width_y); + expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a, op, rvalue(sig_b.extract(0, shift_b_width)), width_y); if (shift_b_width < GetSize(sig_b)) expr = stringf("%s != 0ud%d_0 ? (bool(%s) ? !0ud%d_0 : 0ud%d_0) : %s", rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width, @@ -278,8 +278,8 @@ struct SmvWorker // f << stringf(" %s : unsigned word[%d]; -- neg(%s)\n", b_shl, GetSize(sig_b), log_signal(sig_b)); definitions.push_back(stringf("%s := unsigned(-%s);", b_shl, rvalue_s(sig_b))); - string expr_shl = stringf("resize(%s << %s[%d:0], %d)", expr_a.c_str(), b_shl, shift_b_width-1, width_y); - string expr_shr = stringf("resize(%s >> %s[%d:0], %d)", expr_a.c_str(), b_shr, shift_b_width-1, width_y); + string expr_shl = stringf("resize(%s << %s[%d:0], %d)", expr_a, b_shl, shift_b_width-1, width_y); + string expr_shr = stringf("resize(%s >> %s[%d:0], %d)", expr_a, b_shr, shift_b_width-1, width_y); if (shift_b_width < GetSize(sig_b)) { expr_shl = stringf("%s[%d:%d] != 0ud%d_0 ? 0ud%d_0 : %s", b_shl, GetSize(sig_b)-1, shift_b_width, @@ -288,7 +288,7 @@ struct SmvWorker GetSize(sig_b)-shift_b_width, width_y, expr_shr.c_str()); } - expr = stringf("bool(%s) ? %s : %s", rvalue(sig_b[GetSize(sig_b)-1]), expr_shl.c_str(), expr_shr.c_str()); + expr = stringf("bool(%s) ? %s : %s", rvalue(sig_b[GetSize(sig_b)-1]), expr_shl, expr_shr); } else { @@ -297,13 +297,13 @@ struct SmvWorker else expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width); - expr = stringf("resize(%s %s %s[%d:0], %d)", expr_a.c_str(), op.c_str(), rvalue_u(sig_b), shift_b_width-1, width_y); + expr = stringf("resize(%s %s %s[%d:0], %d)", expr_a, op, rvalue_u(sig_b), shift_b_width-1, width_y); if (shift_b_width < GetSize(sig_b)) expr = stringf("%s[%d:%d] != 0ud%d_0 ? 0ud%d_0 : %s", rvalue_u(sig_b), GetSize(sig_b)-1, shift_b_width, GetSize(sig_b)-shift_b_width, width_y, expr.c_str()); } - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr)); continue; } @@ -426,7 +426,7 @@ struct SmvWorker if (cell->type == ID($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a); if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a); - definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); + definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y)); continue; } @@ -445,7 +445,7 @@ struct SmvWorker if (cell->type == ID($reduce_xnor)) expr = "!(" + expr + ")"; - definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y)); + definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr, width_y)); continue; } @@ -463,7 +463,7 @@ struct SmvWorker if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b; if (cell->type == ID($logic_or)) expr = expr_a + " | " + expr_b; - definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); + definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr, width_y)); continue; } @@ -475,7 +475,7 @@ struct SmvWorker string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a); const char *expr_y = lvalue(cell->getPort(ID::Y)); - definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y)); + definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a, width_y)); continue; } @@ -491,7 +491,7 @@ struct SmvWorker expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width))); expr += rvalue(sig_a); - definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr.c_str())); + definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr)); continue; } @@ -505,7 +505,7 @@ struct SmvWorker if (cell->type.in(ID($_BUF_), ID($_NOT_))) { string op = cell->type == ID($_NOT_) ? "!" : ""; - definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A)))); + definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op, rvalue(cell->getPort(ID::A)))); continue; } @@ -650,7 +650,7 @@ struct SmvWorker for (int k = GetSize(sig)-1; k >= 0; k--) bits += sig[k] == State::S1 ? '1' : '0'; - expr = stringf("0ub%d_%s", GetSize(bits), bits.c_str()) + expr; + expr = stringf("0ub%d_%s", GetSize(bits), bits) + expr; } else if (sigmap(SigBit(wire, i)) == SigBit(wire, i)) { @@ -683,36 +683,36 @@ struct SmvWorker } } - definitions.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str())); + definitions.push_back(stringf("%s := %s;", cid(wire->name), expr)); } if (!inputvars.empty()) { f << stringf(" IVAR\n"); for (const string &line : inputvars) - f << stringf(" %s\n", line.c_str()); + f << stringf(" %s\n", line); } if (!vars.empty()) { f << stringf(" VAR\n"); for (const string &line : vars) - f << stringf(" %s\n", line.c_str()); + f << stringf(" %s\n", line); } if (!definitions.empty()) { f << stringf(" DEFINE\n"); for (const string &line : definitions) - f << stringf(" %s\n", line.c_str()); + f << stringf(" %s\n", line); } if (!assignments.empty()) { f << stringf(" ASSIGN\n"); for (const string &line : assignments) - f << stringf(" %s\n", line.c_str()); + f << stringf(" %s\n", line); } if (!invarspecs.empty()) { for (const string &line : invarspecs) - f << stringf(" INVARSPEC %s\n", line.c_str()); + f << stringf(" INVARSPEC %s\n", line); } } }; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 525ab5bcf..b1ed2b1f0 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -158,7 +158,7 @@ void reset_auto_counter(RTLIL::Module *module) std::string next_auto_id() { - return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_counter++); + return stringf("%s_%0*d_", auto_prefix, auto_name_digits, auto_name_offset + auto_name_counter++); } std::string id(RTLIL::IdString internal_id, bool may_rename = true) @@ -166,7 +166,7 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true) const char *str = internal_id.c_str(); if (may_rename && auto_name_map.count(internal_id) != 0) - return stringf("%s_%0*d_", auto_prefix.c_str(), auto_name_digits, auto_name_offset + auto_name_map[internal_id]); + return stringf("%s_%0*d_", auto_prefix, auto_name_digits, auto_name_offset + auto_name_map[internal_id]); if (*str == '\\') str++; @@ -351,19 +351,19 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal); } else { if (chunk.width == chunk.wire->width && chunk.offset == 0) { - f << stringf("%s", id(chunk.wire->name).c_str()); + f << stringf("%s", id(chunk.wire->name)); } else if (chunk.width == 1) { if (chunk.wire->upto) - f << stringf("%s[%d]", id(chunk.wire->name).c_str(), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + f << stringf("%s[%d]", id(chunk.wire->name), (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); else - f << stringf("%s[%d]", id(chunk.wire->name).c_str(), chunk.offset + chunk.wire->start_offset); + f << stringf("%s[%d]", id(chunk.wire->name), chunk.offset + chunk.wire->start_offset); } else { if (chunk.wire->upto) - f << stringf("%s[%d:%d]", id(chunk.wire->name).c_str(), + f << stringf("%s[%d:%d]", id(chunk.wire->name), (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); else - f << stringf("%s[%d:%d]", id(chunk.wire->name).c_str(), + f << stringf("%s[%d:%d]", id(chunk.wire->name), (chunk.offset + chunk.width - 1) + chunk.wire->start_offset, chunk.offset + chunk.wire->start_offset); } @@ -399,7 +399,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictfirst == ID::single_bit_vector) continue; if (it->first == ID::init && regattr) continue; - f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); + f << stringf("%s" "%s %s", indent, as_comment ? "/*" : "(*", id(it->first)); f << stringf(" = "); if (modattr && (it->second == State::S0 || it->second == Const(0))) f << stringf(" 0 "); @@ -407,7 +407,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictsecond, -1, 0, false, as_comment); - f << stringf(" %s%s", as_comment ? "*/" : "*)", term.c_str()); + f << stringf(" %s%s", as_comment ? "*/" : "*)", term); } } @@ -416,16 +416,16 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) dump_attributes(f, indent, wire->attributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); #if 0 if (wire->port_input && !wire->port_output) - f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "input %s", indent, reg_wires.count(wire->name) ? "reg " : ""); else if (!wire->port_input && wire->port_output) - f << stringf("%s" "output %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "output %s", indent, reg_wires.count(wire->name) ? "reg " : ""); else if (wire->port_input && wire->port_output) - f << stringf("%s" "inout %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); + f << stringf("%s" "inout %s", indent, reg_wires.count(wire->name) ? "reg " : ""); else - f << stringf("%s" "%s ", indent.c_str(), reg_wires.count(wire->name) ? "reg" : "wire"); + f << stringf("%s" "%s ", indent, reg_wires.count(wire->name) ? "reg" : "wire"); if (wire->width != 1) f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset); - f << stringf("%s;\n", id(wire->name).c_str()); + f << stringf("%s;\n", id(wire->name)); #else // do not use Verilog-2k "output reg" syntax in Verilog export std::string range = ""; @@ -439,20 +439,20 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset); } if (wire->port_input && !wire->port_output) - f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name)); if (!wire->port_input && wire->port_output) - f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name)); if (wire->port_input && wire->port_output) - f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name)); if (reg_wires.count(wire->name)) { - f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "reg%s %s", indent, range, id(wire->name)); if (wire->attributes.count(ID::init)) { f << stringf(" = "); dump_const(f, wire->attributes.at(ID::init)); } f << stringf(";\n"); } else - f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name)); #endif } @@ -461,7 +461,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::string mem_id = id(mem.memid); dump_attributes(f, indent, mem.attributes); - f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), mem.width-1, mem_id.c_str(), mem.size+mem.start_offset-1, mem.start_offset); + f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent, mem.width-1, mem_id, mem.size+mem.start_offset-1, mem.start_offset); // for memory block make something like: // reg [7:0] memid [3:0]; @@ -472,7 +472,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) { if (extmem) { - std::string extmem_filename = stringf("%s-%d.mem", extmem_prefix.c_str(), extmem_counter++); + std::string extmem_filename = stringf("%s-%d.mem", extmem_prefix, extmem_counter++); std::string extmem_filename_esc; for (auto c : extmem_filename) @@ -490,7 +490,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) else extmem_filename_esc += c; } - f << stringf("%s" "initial $readmemb(\"%s\", %s);\n", indent.c_str(), extmem_filename_esc.c_str(), mem_id.c_str()); + f << stringf("%s" "initial $readmemb(\"%s\", %s);\n", indent, extmem_filename_esc, mem_id); std::ofstream extmem_f(extmem_filename, std::ofstream::trunc); if (extmem_f.fail()) @@ -519,7 +519,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) } else { - f << stringf("%s" "initial begin\n", indent.c_str()); + f << stringf("%s" "initial begin\n", indent); for (auto &init : mem.inits) { int words = GetSize(init.data) / mem.width; int start = init.addr.as_int(); @@ -536,16 +536,16 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) j++, width++; if (width == mem.width) { - f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i + start); + f << stringf("%s" " %s[%d] = ", indent, mem_id, i + start); } else { - f << stringf("%s" " %s[%d][%d:%d] = ", indent.c_str(), mem_id.c_str(), i + start, j, start_j); + f << stringf("%s" " %s[%d][%d:%d] = ", indent, mem_id, i + start, j, start_j); } dump_const(f, init.data.extract(i*mem.width+start_j, width)); f << stringf(";\n"); } } } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } } @@ -566,11 +566,11 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) { std::ostringstream os; dump_sigspec(os, port.clk); - clk_domain_str = stringf("%sedge %s", port.clk_polarity ? "pos" : "neg", os.str().c_str()); + clk_domain_str = stringf("%sedge %s", port.clk_polarity ? "pos" : "neg", os.str()); if (port.arst != State::S0) { std::ostringstream os2; dump_sigspec(os2, port.arst); - clk_domain_str += stringf(", posedge %s", os2.str().c_str()); + clk_domain_str += stringf(", posedge %s", os2.str()); clk_to_arst_cond[clk_domain_str] = os2.str(); } } @@ -595,13 +595,13 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) // if (rd_en) temp_id <= array_reg[r_addr]; // assign r_data = temp_id; std::string temp_id = next_auto_id(); - lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.data.size() - 1, temp_id.c_str()) ); + lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.data.size() - 1, temp_id) ); bool has_indent = false; if (port.arst != State::S0) { std::ostringstream os; - os << stringf("%s <= ", temp_id.c_str()); + os << stringf("%s <= ", temp_id); dump_sigspec(os, port.arst_value); os << ";\n"; clk_to_arst_body[clk_domain_str].push_back(os.str()); @@ -614,7 +614,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) os << stringf(")\n"); clk_to_lof_body[clk_domain_str].push_back(os.str()); std::ostringstream os2; - os2 << stringf("%s" "%s <= ", indent.c_str(), temp_id.c_str()); + os2 << stringf("%s" "%s <= ", indent, temp_id); dump_sigspec(os2, port.srst_value); os2 << ";\n"; clk_to_lof_body[clk_domain_str].push_back(os2.str()); @@ -646,7 +646,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) os << temp_id; if (port.wide_log2) os << stringf("[%d:%d]", (sub + 1) * mem.width - 1, sub * mem.width); - os << stringf(" <= %s[", mem_id.c_str()); + os << stringf(" <= %s[", mem_id); dump_sigspec(os, addr); os << stringf("];\n"); clk_to_lof_body[clk_domain_str].push_back(os.str()); @@ -721,7 +721,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::ostringstream os2; if (has_indent) os2 << indent; - os2 << stringf("%s" "%s <= ", indent.c_str(), temp_id.c_str()); + os2 << stringf("%s" "%s <= ", indent, temp_id); dump_sigspec(os2, port.srst_value); os2 << ";\n"; clk_to_lof_body[clk_domain_str].push_back(os2.str()); @@ -734,14 +734,14 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) { std::ostringstream os; dump_sigspec(os, port.init_value); - std::string line = stringf("initial %s = %s;\n", temp_id.c_str(), os.str().c_str()); + std::string line = stringf("initial %s = %s;\n", temp_id, os.str()); clk_to_lof_body[""].push_back(line); } { std::ostringstream os; dump_sigspec(os, port.data); - std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str()); + std::string line = stringf("assign %s = %s;\n", os.str(), temp_id); clk_to_lof_body[""].push_back(line); } } @@ -753,11 +753,11 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) // temp_id <= r_addr; // assign r_data = array_reg[temp_id]; std::string temp_id = next_auto_id(); - lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.addr.size() - 1 - port.wide_log2, temp_id.c_str()) ); + lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", port.addr.size() - 1 - port.wide_log2, temp_id) ); { std::ostringstream os; dump_sigspec(os, port.addr.extract_end(port.wide_log2)); - std::string line = stringf("%s <= %s;\n", temp_id.c_str(), os.str().c_str()); + std::string line = stringf("%s <= %s;\n", temp_id, os.str()); clk_to_lof_body[clk_domain_str].push_back(line); } for (int sub = 0; sub < (1 << port.wide_log2); sub++) @@ -765,7 +765,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::ostringstream os; os << "assign "; dump_sigspec(os, port.data.extract(sub * mem.width, mem.width)); - os << stringf(" = %s[", mem_id.c_str());; + os << stringf(" = %s[", mem_id);; if (port.wide_log2) { Const addr_lo; for (int i = 0; i < port.wide_log2; i++) @@ -792,7 +792,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::ostringstream os, os2; dump_sigspec(os, port.data.extract(sub * mem.width, mem.width)); dump_sigspec(os2, addr); - std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str()); + std::string line = stringf("assign %s = %s[%s];\n", os.str(), mem_id, os2.str()); clk_to_lof_body[""].push_back(line); } } @@ -841,11 +841,11 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) } if (root.clk_enable) { - f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", root.clk_polarity ? "pos" : "neg"); + f << stringf("%s" "always%s @(%sedge ", indent, systemverilog ? "_ff" : "", root.clk_polarity ? "pos" : "neg"); dump_sigspec(f, root.clk); f << ") begin\n"; } else { - f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_latch" : " @*"); + f << stringf("%s" "always%s begin\n", indent, systemverilog ? "_latch" : " @*"); } for (int pidx = 0; pidx < GetSize(mem.wr_ports); pidx++) @@ -879,15 +879,15 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) if (wen_bit == State::S0) continue; - f << stringf("%s%s", indent.c_str(), indent.c_str()); + f << stringf("%s%s", indent, indent); if (wen_bit != State::S1) { f << stringf("if ("); dump_sigspec(f, wen_bit); f << stringf(")\n"); - f << stringf("%s%s%s", indent.c_str(), indent.c_str(), indent.c_str()); + f << stringf("%s%s%s", indent, indent, indent); } - f << stringf("%s[", mem_id.c_str()); + f << stringf("%s[", mem_id); dump_sigspec(f, addr); if (width == GetSize(port.en)) f << stringf("] <= "); @@ -899,7 +899,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) } } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } // Output Verilog that looks something like this: // reg [..] _3_; @@ -922,7 +922,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) // the reg ... definitions for(auto ® : lof_reg_declarations) { - f << stringf("%s" "%s", indent.c_str(), reg.c_str()); + f << stringf("%s" "%s", indent, reg); } // the block of expressions by clock domain for(auto &pair : clk_to_lof_body) @@ -931,27 +931,27 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::vector lof_lines = pair.second; if( clk_domain != "") { - f << stringf("%s" "always%s @(%s) begin\n", indent.c_str(), systemverilog ? "_ff" : "", clk_domain.c_str()); + f << stringf("%s" "always%s @(%s) begin\n", indent, systemverilog ? "_ff" : "", clk_domain); bool has_arst = clk_to_arst_cond.count(clk_domain) != 0; if (has_arst) { - f << stringf("%s%s" "if (%s) begin\n", indent.c_str(), indent.c_str(), clk_to_arst_cond[clk_domain].c_str()); + f << stringf("%s%s" "if (%s) begin\n", indent, indent, clk_to_arst_cond[clk_domain]); for(auto &line : clk_to_arst_body[clk_domain]) - f << stringf("%s%s%s" "%s", indent.c_str(), indent.c_str(), indent.c_str(), line.c_str()); - f << stringf("%s%s" "end else begin\n", indent.c_str(), indent.c_str()); + f << stringf("%s%s%s" "%s", indent, indent, indent, line); + f << stringf("%s%s" "end else begin\n", indent, indent); for(auto &line : lof_lines) - f << stringf("%s%s%s" "%s", indent.c_str(), indent.c_str(), indent.c_str(), line.c_str()); - f << stringf("%s%s" "end\n", indent.c_str(), indent.c_str()); + f << stringf("%s%s%s" "%s", indent, indent, indent, line); + f << stringf("%s%s" "end\n", indent, indent); } else { for(auto &line : lof_lines) - f << stringf("%s%s" "%s", indent.c_str(), indent.c_str(), line.c_str()); + f << stringf("%s%s" "%s", indent, indent, line); } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } else { // the non-clocked assignments for(auto &line : lof_lines) - f << stringf("%s" "%s", indent.c_str(), line.c_str()); + f << stringf("%s" "%s", indent, line); } } } @@ -1004,9 +1004,9 @@ no_special_reg_name: void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); - f << stringf(" = %s ", op.c_str()); + f << stringf(" = %s ", op); dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", true); f << stringf(";\n"); @@ -1014,11 +1014,11 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); - f << stringf(" %s ", op.c_str()); + f << stringf(" %s ", op); dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", true); f << stringf(";\n"); @@ -1030,7 +1030,7 @@ void dump_cell_expr_print(std::ostream &f, std::string indent, const RTLIL::Cell fmt.parse_rtlil(cell); std::vector args = fmt.emit_verilog(); - f << stringf("%s" "$write(", indent.c_str()); + f << stringf("%s" "$write(", indent); bool first = true; for (auto &arg : args) { if (first) { @@ -1064,19 +1064,19 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell std::string flavor = cell->getParam(ID(FLAVOR)).decode_string(); std::string label = ""; if (cell->name.isPublic()) { - label = stringf("%s: ", id(cell->name).c_str()); + label = stringf("%s: ", id(cell->name)); } if (flavor == "assert") - f << stringf("%s" "%s" "assert (", indent.c_str(), label.c_str()); + f << stringf("%s" "%s" "assert (", indent, label); else if (flavor == "assume") - f << stringf("%s" "%s" "assume (", indent.c_str(), label.c_str()); + f << stringf("%s" "%s" "assume (", indent, label); else if (flavor == "live") - f << stringf("%s" "%s" "assert (eventually ", indent.c_str(), label.c_str()); + f << stringf("%s" "%s" "assert (eventually ", indent, label); else if (flavor == "fair") - f << stringf("%s" "%s" "assume (eventually ", indent.c_str(), label.c_str()); + f << stringf("%s" "%s" "assume (eventually ", indent, label); else if (flavor == "cover") - f << stringf("%s" "%s" "cover (", indent.c_str(), label.c_str()); + f << stringf("%s" "%s" "cover (", indent, label); else log_abort(); dump_sigspec(f, cell->getPort(ID::A)); @@ -1086,7 +1086,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type == ID($_NOT_)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); f << stringf("~"); @@ -1097,7 +1097,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_BUF_), ID($buf))) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "A", false); @@ -1106,7 +1106,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_))) @@ -1131,7 +1131,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type == ID($_MUX_)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); @@ -1145,7 +1145,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type == ID($_NMUX_)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = !("); dump_cell_expr_port(f, cell, "S", false); @@ -1159,7 +1159,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); @@ -1174,7 +1174,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ~(("); dump_cell_expr_port(f, cell, "A", false); @@ -1259,32 +1259,32 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) int size_max = std::max(size_a, std::max(size_b, size_y)); // intentionally one wider than maximum width - f << stringf("%s" "wire [%d:0] %s, %s, %s;\n", indent.c_str(), size_max, buf_a.c_str(), buf_b.c_str(), buf_num.c_str()); - f << stringf("%s" "assign %s = ", indent.c_str(), buf_a.c_str()); + f << stringf("%s" "wire [%d:0] %s, %s, %s;\n", indent, size_max, buf_a, buf_b, buf_num); + f << stringf("%s" "assign %s = ", indent, buf_a); dump_cell_expr_port(f, cell, "A", true); f << stringf(";\n"); - f << stringf("%s" "assign %s = ", indent.c_str(), buf_b.c_str()); + f << stringf("%s" "assign %s = ", indent, buf_b); dump_cell_expr_port(f, cell, "B", true); f << stringf(";\n"); - f << stringf("%s" "assign %s = ", indent.c_str(), buf_num.c_str()); + f << stringf("%s" "assign %s = ", indent, buf_num); f << stringf("("); dump_sigspec(f, sig_a.extract(sig_a.size()-1)); f << stringf(" == "); dump_sigspec(f, sig_b.extract(sig_b.size()-1)); f << stringf(") || "); dump_sigspec(f, sig_a); - f << stringf(" == 0 ? %s : ", buf_a.c_str()); - f << stringf("$signed(%s - (", buf_a.c_str()); + f << stringf(" == 0 ? %s : ", buf_a); + f << stringf("$signed(%s - (", buf_a); dump_sigspec(f, sig_b.extract(sig_b.size()-1)); - f << stringf(" ? %s + 1 : %s - 1));\n", buf_b.c_str(), buf_b.c_str()); + f << stringf(" ? %s + 1 : %s - 1));\n", buf_b, buf_b); - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); - f << stringf(" = $signed(%s) / ", buf_num.c_str()); + f << stringf(" = $signed(%s) / ", buf_num); dump_attributes(f, "", cell->attributes, " "); - f << stringf("$signed(%s);\n", buf_b.c_str()); + f << stringf("$signed(%s);\n", buf_b); return true; } else { // same as truncating division @@ -1303,22 +1303,22 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) SigSpec sig_b = cell->getPort(ID::B); std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); + f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %% "); dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", true); f << stringf(";\n"); - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = ("); dump_sigspec(f, sig_a.extract(sig_a.size()-1)); f << stringf(" == "); dump_sigspec(f, sig_b.extract(sig_b.size()-1)); - f << stringf(") || %s == 0 ? $signed(%s) : ", temp_id.c_str(), temp_id.c_str()); + f << stringf(") || %s == 0 ? $signed(%s) : ", temp_id, temp_id); dump_cell_expr_port(f, cell, "B", true); - f << stringf(" + $signed(%s);\n", temp_id.c_str()); + f << stringf(" + $signed(%s);\n", temp_id); return true; } else { // same as truncating modulo @@ -1329,7 +1329,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($shift)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); if (cell->getParam(ID::B_SIGNED).as_bool()) @@ -1357,13 +1357,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($shiftx)) { std::string temp_id = next_auto_id(); - f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); + f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id); dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); - f << stringf(" = %s[", temp_id.c_str()); + f << stringf(" = %s[", temp_id); if (cell->getParam(ID::B_SIGNED).as_bool()) f << stringf("$signed("); dump_sigspec(f, cell->getPort(ID::B)); @@ -1376,7 +1376,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($mux)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_sigspec(f, cell->getPort(ID::S)); @@ -1402,44 +1402,44 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_attributes(f, indent + " ", cell->attributes); if (noparallelcase) - f << stringf("%s" " case (s)\n", indent.c_str()); + f << stringf("%s" " case (s)\n", indent); else { if (!noattr) - f << stringf("%s" " (* parallel_case *)\n", indent.c_str()); - f << stringf("%s" " casez (s)", indent.c_str()); + f << stringf("%s" " (* parallel_case *)\n", indent); + f << stringf("%s" " casez (s)", indent); f << (noattr ? " // synopsys parallel_case\n" : "\n"); } for (int i = 0; i < s_width; i++) { - f << stringf("%s" " %d'b", indent.c_str(), s_width); + f << stringf("%s" " %d'b", indent, s_width); for (int j = s_width-1; j >= 0; j--) f << stringf("%c", j == i ? '1' : noparallelcase ? '0' : '?'); f << stringf(":\n"); - f << stringf("%s" " %s = b[%d:%d];\n", indent.c_str(), func_name.c_str(), (i+1)*width-1, i*width); + f << stringf("%s" " %s = b[%d:%d];\n", indent, func_name, (i+1)*width-1, i*width); } if (noparallelcase) { - f << stringf("%s" " %d'b", indent.c_str(), s_width); + f << stringf("%s" " %d'b", indent, s_width); for (int j = s_width-1; j >= 0; j--) f << '0'; f << stringf(":\n"); } else - f << stringf("%s" " default:\n", indent.c_str()); - f << stringf("%s" " %s = a;\n", indent.c_str(), func_name.c_str()); + f << stringf("%s" " default:\n", indent); + f << stringf("%s" " %s = a;\n", indent, func_name); if (noparallelcase) { - f << stringf("%s" " default:\n", indent.c_str()); - f << stringf("%s" " %s = %d'bx;\n", indent.c_str(), func_name.c_str(), width); + f << stringf("%s" " default:\n", indent); + f << stringf("%s" " %s = %d'bx;\n", indent, func_name, width); } - f << stringf("%s" " endcase\n", indent.c_str()); - f << stringf("%s" "endfunction\n", indent.c_str()); + f << stringf("%s" " endcase\n", indent); + f << stringf("%s" "endfunction\n", indent); - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); - f << stringf(" = %s(", func_name.c_str()); + f << stringf(" = %s(", func_name); dump_sigspec(f, cell->getPort(ID::A)); f << stringf(", "); dump_sigspec(f, cell->getPort(ID::B)); @@ -1451,7 +1451,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($tribuf)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_sigspec(f, cell->getPort(ID::EN)); @@ -1463,7 +1463,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($slice)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_sigspec(f, cell->getPort(ID::A)); @@ -1473,7 +1473,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($concat)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = { "); dump_sigspec(f, cell->getPort(ID::B)); @@ -1485,7 +1485,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type == ID($lut)) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); dump_const(f, cell->parameters.at(ID::LUT)); @@ -1509,9 +1509,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!out_is_reg_wire) { if (ff.width == 1) - f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str()); + f << stringf("%s" "reg %s", indent, reg_name); else - f << stringf("%s" "reg [%d:0] %s", indent.c_str(), ff.width-1, reg_name.c_str()); + f << stringf("%s" "reg [%d:0] %s", indent, ff.width-1, reg_name); dump_reg_init(f, ff.sig_q); f << ";\n"; } @@ -1526,7 +1526,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) Const val_arst, val_srst; std::string reg_bit_name, sig_set_name, sig_clr_name, sig_arst_name, sig_aload_name; if (chunky) { - reg_bit_name = stringf("%s[%d]", reg_name.c_str(), i); + reg_bit_name = stringf("%s[%d]", reg_name, i); if (ff.has_gclk || ff.has_clk) sig_d = ff.sig_d[i]; if (ff.has_aload) @@ -1547,14 +1547,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (ff.sig_set[i].wire == NULL) { sig_set_name = next_auto_id(); - f << stringf("%s" "wire %s = ", indent.c_str(), sig_set_name.c_str()); + f << stringf("%s" "wire %s = ", indent, sig_set_name); dump_const(f, ff.sig_set[i].data); f << stringf(";\n"); } if (ff.sig_clr[i].wire == NULL) { sig_clr_name = next_auto_id(); - f << stringf("%s" "wire %s = ", indent.c_str(), sig_clr_name.c_str()); + f << stringf("%s" "wire %s = ", indent, sig_clr_name); dump_const(f, ff.sig_clr[i].data); f << stringf(";\n"); } @@ -1562,7 +1562,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (ff.sig_arst[0].wire == NULL) { sig_arst_name = next_auto_id(); - f << stringf("%s" "wire %s = ", indent.c_str(), sig_arst_name.c_str()); + f << stringf("%s" "wire %s = ", indent, sig_arst_name); dump_const(f, ff.sig_arst[0].data); f << stringf(";\n"); } @@ -1570,7 +1570,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (ff.sig_aload[0].wire == NULL) { sig_aload_name = next_auto_id(); - f << stringf("%s" "wire %s = ", indent.c_str(), sig_aload_name.c_str()); + f << stringf("%s" "wire %s = ", indent, sig_aload_name); dump_const(f, ff.sig_aload[0].data); f << stringf(";\n"); } @@ -1581,90 +1581,90 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (ff.has_clk) { // FFs. - f << stringf("%s" "always%s @(%sedge ", indent.c_str(), systemverilog ? "_ff" : "", ff.pol_clk ? "pos" : "neg"); + f << stringf("%s" "always%s @(%sedge ", indent, systemverilog ? "_ff" : "", ff.pol_clk ? "pos" : "neg"); dump_sigspec(f, ff.sig_clk); if (ff.has_sr) { f << stringf(", %sedge ", ff.pol_set ? "pos" : "neg"); if (ff.sig_set[i].wire == NULL) - f << stringf("%s", sig_set_name.c_str()); + f << stringf("%s", sig_set_name); else dump_sigspec(f, ff.sig_set[i]); f << stringf(", %sedge ", ff.pol_clr ? "pos" : "neg"); if (ff.sig_clr[i].wire == NULL) - f << stringf("%s", sig_clr_name.c_str()); + f << stringf("%s", sig_clr_name); else dump_sigspec(f, ff.sig_clr[i]); } else if (ff.has_arst) { f << stringf(", %sedge ", ff.pol_arst ? "pos" : "neg"); if (ff.sig_arst[0].wire == NULL) - f << stringf("%s", sig_arst_name.c_str()); + f << stringf("%s", sig_arst_name); else dump_sigspec(f, ff.sig_arst); } else if (ff.has_aload) { f << stringf(", %sedge ", ff.pol_aload ? "pos" : "neg"); if (ff.sig_aload[0].wire == NULL) - f << stringf("%s", sig_aload_name.c_str()); + f << stringf("%s", sig_aload_name); else dump_sigspec(f, ff.sig_aload); } f << stringf(")\n"); - f << stringf("%s" " ", indent.c_str()); + f << stringf("%s" " ", indent); if (ff.has_sr) { f << stringf("if (%s", ff.pol_clr ? "" : "!"); if (ff.sig_clr[i].wire == NULL) - f << stringf("%s", sig_clr_name.c_str()); + f << stringf("%s", sig_clr_name); else dump_sigspec(f, ff.sig_clr[i]); - f << stringf(") %s <= 1'b0;\n", reg_bit_name.c_str()); - f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!"); + f << stringf(") %s <= 1'b0;\n", reg_bit_name); + f << stringf("%s" " else if (%s", indent, ff.pol_set ? "" : "!"); if (ff.sig_set[i].wire == NULL) - f << stringf("%s", sig_set_name.c_str()); + f << stringf("%s", sig_set_name); else dump_sigspec(f, ff.sig_set[i]); - f << stringf(") %s <= 1'b1;\n", reg_bit_name.c_str()); - f << stringf("%s" " else ", indent.c_str()); + f << stringf(") %s <= 1'b1;\n", reg_bit_name); + f << stringf("%s" " else ", indent); } else if (ff.has_arst) { f << stringf("if (%s", ff.pol_arst ? "" : "!"); if (ff.sig_arst[0].wire == NULL) - f << stringf("%s", sig_arst_name.c_str()); + f << stringf("%s", sig_arst_name); else dump_sigspec(f, ff.sig_arst); - f << stringf(") %s <= ", reg_bit_name.c_str()); + f << stringf(") %s <= ", reg_bit_name); dump_sigspec(f, val_arst); f << stringf(";\n"); - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } else if (ff.has_aload) { f << stringf("if (%s", ff.pol_aload ? "" : "!"); if (ff.sig_aload[0].wire == NULL) - f << stringf("%s", sig_aload_name.c_str()); + f << stringf("%s", sig_aload_name); else dump_sigspec(f, ff.sig_aload); - f << stringf(") %s <= ", reg_bit_name.c_str()); + f << stringf(") %s <= ", reg_bit_name); dump_sigspec(f, sig_ad); f << stringf(";\n"); - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } if (ff.has_srst && ff.has_ce && ff.ce_over_srst) { f << stringf("if (%s", ff.pol_ce ? "" : "!"); dump_sigspec(f, ff.sig_ce); f << stringf(")\n"); - f << stringf("%s" " if (%s", indent.c_str(), ff.pol_srst ? "" : "!"); + f << stringf("%s" " if (%s", indent, ff.pol_srst ? "" : "!"); dump_sigspec(f, ff.sig_srst); - f << stringf(") %s <= ", reg_bit_name.c_str()); + f << stringf(") %s <= ", reg_bit_name); dump_sigspec(f, val_srst); f << stringf(";\n"); - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } else { if (ff.has_srst) { f << stringf("if (%s", ff.pol_srst ? "" : "!"); dump_sigspec(f, ff.sig_srst); - f << stringf(") %s <= ", reg_bit_name.c_str()); + f << stringf(") %s <= ", reg_bit_name); dump_sigspec(f, val_srst); f << stringf(";\n"); - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } if (ff.has_ce) { f << stringf("if (%s", ff.pol_ce ? "" : "!"); @@ -1673,38 +1673,38 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - f << stringf("%s <= ", reg_bit_name.c_str()); + f << stringf("%s <= ", reg_bit_name); dump_sigspec(f, sig_d); f << stringf(";\n"); } else { // Latches. - f << stringf("%s" "always%s\n", indent.c_str(), systemverilog ? "_latch" : " @*"); + f << stringf("%s" "always%s\n", indent, systemverilog ? "_latch" : " @*"); - f << stringf("%s" " ", indent.c_str()); + f << stringf("%s" " ", indent); if (ff.has_sr) { f << stringf("if (%s", ff.pol_clr ? "" : "!"); dump_sigspec(f, ff.sig_clr[i]); - f << stringf(") %s = 1'b0;\n", reg_bit_name.c_str()); - f << stringf("%s" " else if (%s", indent.c_str(), ff.pol_set ? "" : "!"); + f << stringf(") %s = 1'b0;\n", reg_bit_name); + f << stringf("%s" " else if (%s", indent, ff.pol_set ? "" : "!"); dump_sigspec(f, ff.sig_set[i]); - f << stringf(") %s = 1'b1;\n", reg_bit_name.c_str()); + f << stringf(") %s = 1'b1;\n", reg_bit_name); if (ff.has_aload) - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } else if (ff.has_arst) { f << stringf("if (%s", ff.pol_arst ? "" : "!"); dump_sigspec(f, ff.sig_arst); - f << stringf(") %s = ", reg_bit_name.c_str()); + f << stringf(") %s = ", reg_bit_name); dump_sigspec(f, val_arst); f << stringf(";\n"); if (ff.has_aload) - f << stringf("%s" " else ", indent.c_str()); + f << stringf("%s" " else ", indent); } if (ff.has_aload) { f << stringf("if (%s", ff.pol_aload ? "" : "!"); dump_sigspec(f, ff.sig_aload); - f << stringf(") %s = ", reg_bit_name.c_str()); + f << stringf(") %s = ", reg_bit_name); dump_sigspec(f, sig_ad); f << stringf(";\n"); } @@ -1712,9 +1712,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (!out_is_reg_wire) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, ff.sig_q); - f << stringf(" = %s;\n", reg_name.c_str()); + f << stringf(" = %s;\n", reg_name); } return true; @@ -1722,7 +1722,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($assert), ID($assume), ID($cover))) { - f << stringf("%s" "always%s if (", indent.c_str(), systemverilog ? "_comb" : " @*"); + f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*"); dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(") %s(", cell->type.c_str()+1); dump_sigspec(f, cell->getPort(ID::A)); @@ -1732,7 +1732,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->type.in(ID($specify2), ID($specify3))) { - f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); + f << stringf("%s" "specify\n%s ", indent, indent); SigSpec en = cell->getPort(ID::EN); if (en != State::S1) { @@ -1784,16 +1784,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) decimal = bak_decimal; - f << stringf("%s" "endspecify\n", indent.c_str()); + f << stringf("%s" "endspecify\n", indent); return true; } if (cell->type == ID($specrule)) { - f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); + f << stringf("%s" "specify\n%s ", indent, indent); IdString spec_type = cell->getParam(ID::TYPE).decode_string(); - f << stringf("%s(", spec_type.c_str()); + f << stringf("%s(", spec_type); if (cell->getParam(ID::SRC_PEN).as_bool()) f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge "); @@ -1836,7 +1836,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << ");\n"; decimal = bak_decimal; - f << stringf("%s" "endspecify\n", indent.c_str()); + f << stringf("%s" "endspecify\n", indent); return true; } @@ -1846,9 +1846,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->getParam(ID::TRG_ENABLE).as_bool()) return true; - f << stringf("%s" "always @*\n", indent.c_str()); + f << stringf("%s" "always @*\n", indent); - f << stringf("%s" " if (", indent.c_str()); + f << stringf("%s" " if (", indent); dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(")\n"); @@ -1862,9 +1862,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (cell->getParam(ID::TRG_ENABLE).as_bool()) return true; - f << stringf("%s" "always @*\n", indent.c_str()); + f << stringf("%s" "always @*\n", indent); - f << stringf("%s" " if (", indent.c_str()); + f << stringf("%s" " if (", indent); dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(") begin\n"); @@ -1873,18 +1873,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) Fmt fmt; fmt.parse_rtlil(cell); if (!fmt.parts.empty()) { - f << stringf("%s" " if (!", indent.c_str()); + f << stringf("%s" " if (!", indent); dump_sigspec(f, cell->getPort(ID::A)); f << stringf(")\n"); dump_cell_expr_print(f, indent + " ", cell); } } else { - f << stringf("%s" " /* message omitted */\n", indent.c_str()); + f << stringf("%s" " /* message omitted */\n", indent); } dump_cell_expr_check(f, indent + " ", cell); - f << stringf("%s" " end\n", indent.c_str()); + f << stringf("%s" " end\n", indent); return true; } @@ -1913,26 +1913,26 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } dump_attributes(f, indent, cell->attributes); - f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); + f << stringf("%s" "%s", indent, id(cell->type, false)); if (!defparam && cell->parameters.size() > 0) { f << stringf(" #("); for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { if (it != cell->parameters.begin()) f << stringf(","); - f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); + f << stringf("\n%s .%s(", indent, id(it->first)); if (it->second.size() > 0) dump_const(f, it->second); f << stringf(")"); } - f << stringf("\n%s" ")", indent.c_str()); + f << stringf("\n%s" ")", indent); } std::string cell_name = cellname(cell); if (cell_name != id(cell->name)) - f << stringf(" %s /* %s */ (", cell_name.c_str(), id(cell->name).c_str()); + f << stringf(" %s /* %s */ (", cell_name, id(cell->name)); else - f << stringf(" %s (", cell_name.c_str()); + f << stringf(" %s (", cell_name); bool first_arg = true; std::set numbered_ports; @@ -1945,7 +1945,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!first_arg) f << stringf(","); first_arg = false; - f << stringf("\n%s ", indent.c_str()); + f << stringf("\n%s ", indent); dump_sigspec(f, it->second); numbered_ports.insert(it->first); goto found_numbered_port; @@ -1959,16 +1959,16 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!first_arg) f << stringf(","); first_arg = false; - f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); + f << stringf("\n%s .%s(", indent, id(it->first)); if (it->second.size() > 0) dump_sigspec(f, it->second); f << stringf(")"); } - f << stringf("\n%s" ");\n", indent.c_str()); + f << stringf("\n%s" ");\n", indent); if (defparam && cell->parameters.size() > 0) { for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) { - f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str()); + f << stringf("%sdefparam %s.%s = ", indent, cell_name, id(it->first)); dump_const(f, it->second); f << stringf(";\n"); } @@ -1978,7 +1978,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) std::stringstream ss; dump_reg_init(ss, cell->getPort(ID::Q)); if (!ss.str().empty()) { - f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); + f << stringf("%sinitial %s.Q", indent, cell_name); f << ss.str(); f << ";\n"; } @@ -1988,9 +1988,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector &cells) { if (trg.size() == 0) { - f << stringf("%s" "initial begin\n", indent.c_str()); + f << stringf("%s" "initial begin\n", indent); } else { - f << stringf("%s" "always @(", indent.c_str()); + f << stringf("%s" "always @(", indent); for (int i = 0; i < trg.size(); i++) { if (i != 0) f << " or "; @@ -2007,7 +2007,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int(); }); for (auto cell : cells) { - f << stringf("%s" " if (", indent.c_str()); + f << stringf("%s" " if (", indent); dump_sigspec(f, cell->getPort(ID::EN)); f << stringf(") begin\n"); @@ -2019,22 +2019,22 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec Fmt fmt; fmt.parse_rtlil(cell); if (!fmt.parts.empty()) { - f << stringf("%s" " if (!", indent.c_str()); + f << stringf("%s" " if (!", indent); dump_sigspec(f, cell->getPort(ID::A)); f << stringf(")\n"); dump_cell_expr_print(f, indent + " ", cell); } } else { - f << stringf("%s" " /* message omitted */\n", indent.c_str()); + f << stringf("%s" " /* message omitted */\n", indent); } dump_cell_expr_check(f, indent + " ", cell); } - f << stringf("%s" " end\n", indent.c_str()); + f << stringf("%s" " end\n", indent); } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) @@ -2044,7 +2044,7 @@ void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, if (chunk.is_wire() && reg_wires.count(chunk.wire->name)) all_chunks_wires = false; if (!simple_lhs && all_chunks_wires) { - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, left); f << stringf(" = "); dump_sigspec(f, right); @@ -2053,9 +2053,9 @@ void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, int offset = 0; for (auto &chunk : left.chunks()) { if (chunk.is_wire() && reg_wires.count(chunk.wire->name)) - f << stringf("%s" "always%s\n%s ", indent.c_str(), systemverilog ? "_comb" : " @*", indent.c_str()); + f << stringf("%s" "always%s\n%s ", indent, systemverilog ? "_comb" : " @*", indent); else - f << stringf("%s" "assign ", indent.c_str()); + f << stringf("%s" "assign ", indent); dump_sigspec(f, chunk); f << stringf(" = "); dump_sigspec(f, right.extract(offset, GetSize(chunk))); @@ -2072,7 +2072,7 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs) for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) { if (it->first.size() == 0) continue; - f << stringf("%s ", indent.c_str()); + f << stringf("%s ", indent); dump_sigspec(f, it->first); f << stringf(" = "); dump_sigspec(f, it->second); @@ -2133,28 +2133,28 @@ void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bo int number_of_stmts = cs->switches.size() + cs->actions.size(); if (!omit_trailing_begin && number_of_stmts >= 2) - f << stringf("%s" "begin\n", indent.c_str()); + f << stringf("%s" "begin\n", indent); dump_case_actions(f, indent, cs); for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it) dump_proc_switch(f, indent + " ", *it); if (!omit_trailing_begin && number_of_stmts == 0) - f << stringf("%s /* empty */;\n", indent.c_str()); + f << stringf("%s /* empty */;\n", indent); if (omit_trailing_begin || number_of_stmts >= 2) - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); } void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) { if (sw->signal.size() == 0) { - f << stringf("%s" "begin\n", indent.c_str()); + f << stringf("%s" "begin\n", indent); for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { if ((*it)->compare.size() == 0) dump_case_body(f, indent + " ", *it); } - f << stringf("%s" "end\n", indent.c_str()); + f << stringf("%s" "end\n", indent); return; } @@ -2162,7 +2162,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw return; dump_attributes(f, indent, sw->attributes); - f << stringf("%s" "casez (", indent.c_str()); + f << stringf("%s" "casez (", indent); dump_sigspec(f, sw->signal); f << stringf(")\n"); @@ -2170,10 +2170,10 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw bool got_default = false; dump_attributes(f, indent + " ", (*it)->attributes, "\n", /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { - f << stringf("%s default", indent.c_str()); + f << stringf("%s default", indent); got_default = true; } else { - f << stringf("%s ", indent.c_str()); + f << stringf("%s ", indent); for (size_t i = 0; i < (*it)->compare.size(); i++) { if (i > 0) f << stringf(", "); @@ -2194,10 +2194,10 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw if (sw->cases.empty()) { // Verilog does not allow empty cases. - f << stringf("%s default: ;\n", indent.c_str()); + f << stringf("%s default: ;\n", indent); } - f << stringf("%s" "endcase\n", indent.c_str()); + f << stringf("%s" "endcase\n", indent); } void case_body_find_regs(RTLIL::CaseRule *cs) @@ -2226,7 +2226,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo return; } - f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*"); + f << stringf("%s" "always%s begin\n", indent, systemverilog ? "_comb" : " @*"); if (!systemverilog) f << indent + " " << "if (" << id(initial_id) << ") begin end\n"; dump_case_body(f, indent, &proc->root_case, true); @@ -2239,11 +2239,11 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo indent = backup_indent; if (sync->type == RTLIL::STa) { - f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*"); + f << stringf("%s" "always%s begin\n", indent, systemverilog ? "_comb" : " @*"); } else if (sync->type == RTLIL::STi) { - f << stringf("%s" "initial begin\n", indent.c_str()); + f << stringf("%s" "initial begin\n", indent); } else { - f << stringf("%s" "always%s @(", indent.c_str(), systemverilog ? "_ff" : ""); + f << stringf("%s" "always%s @(", indent, systemverilog ? "_ff" : ""); if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1) f << stringf("posedge "); if (sync->type == RTLIL::STn || sync->type == RTLIL::ST0) @@ -2255,7 +2255,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo indent += " "; if (sync->type == RTLIL::ST0 || sync->type == RTLIL::ST1) { - f << stringf("%s" "if (%s", indent.c_str(), sync->type == RTLIL::ST0 ? "!" : ""); + f << stringf("%s" "if (%s", indent, sync->type == RTLIL::ST0 ? "!" : ""); dump_sigspec(f, sync->signal); f << stringf(") begin\n"); ends = indent + "end\n" + ends; @@ -2266,7 +2266,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo for (size_t j = 0; j < proc->syncs.size(); j++) { RTLIL::SyncRule *sync2 = proc->syncs[j]; if (sync2->type == RTLIL::ST0 || sync2->type == RTLIL::ST1) { - f << stringf("%s" "if (%s", indent.c_str(), sync2->type == RTLIL::ST1 ? "!" : ""); + f << stringf("%s" "if (%s", indent, sync2->type == RTLIL::ST1 ? "!" : ""); dump_sigspec(f, sync2->signal); f << stringf(") begin\n"); ends = indent + "end\n" + ends; @@ -2278,14 +2278,14 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo for (auto it = sync->actions.begin(); it != sync->actions.end(); ++it) { if (it->first.size() == 0) continue; - f << stringf("%s ", indent.c_str()); + f << stringf("%s ", indent); dump_sigspec(f, it->first); f << stringf(" <= "); dump_sigspec(f, it->second); f << stringf(";\n"); } - f << stringf("%s", ends.c_str()); + f << stringf("%s", ends); } } @@ -2356,14 +2356,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); - f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); + f << stringf("%s" "module %s(", indent, id(module->name, false)); int cnt = 0; for (auto port : module->ports) { Wire *wire = module->wire(port); if (wire) { if (port != module->ports[0]) f << stringf(", "); - f << stringf("%s", id(wire->name).c_str()); + f << stringf("%s", id(wire->name)); if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; continue; } @@ -2400,7 +2400,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) for (auto it = module->connections().begin(); it != module->connections().end(); ++it) dump_conn(f, indent + " ", it->first, it->second); - f << stringf("%s" "endmodule\n", indent.c_str()); + f << stringf("%s" "endmodule\n", indent); active_module = NULL; active_sigmap.clear(); active_initdata.clear(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 37ace27fd..c5d9bc70b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -284,7 +284,7 @@ end_of_header: if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) log_error("Line %u has invalid symbol position!\n", line_count); - RTLIL::IdString escaped_s = stringf("\\%s", s.c_str()); + RTLIL::IdString escaped_s = stringf("\\%s", s); RTLIL::Wire* wire; if (c == 'i') wire = inputs[l1]; else if (c == 'l') wire = latches[l1]; @@ -830,7 +830,7 @@ void AigerReader::post_process() log_debug(" -> %s\n", log_id(escaped_s)); } else { - RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); + RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); existing = module->wire(indexed_name); if (!existing) module->rename(wire, indexed_name); @@ -877,7 +877,7 @@ void AigerReader::post_process() log_debug(" -> %s\n", log_id(escaped_s)); } else { - RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); + RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); existing = module->wire(indexed_name); if (!existing) module->rename(wire, indexed_name); @@ -922,7 +922,7 @@ void AigerReader::post_process() RTLIL::Wire *wire = module->wire(name); if (wire) - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name, 0))); // Do not make ports with a mix of input/output into // wide ports @@ -942,7 +942,7 @@ void AigerReader::post_process() wire->port_output = port_output; for (int i = min; i <= max; i++) { - RTLIL::IdString other_name = stringf("%s[%d]", name.c_str(), i); + RTLIL::IdString other_name = stringf("%s[%d]", name, i); RTLIL::Wire *other_wire = module->wire(other_name); if (other_wire) { other_wire->port_input = false; @@ -971,9 +971,9 @@ void AigerReader::post_process() if (cell->type != ID($lut)) continue; auto y_port = cell->getPort(ID::Y).as_bit(); if (y_port.wire->width == 1) - module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str())); + module->rename(cell, stringf("$lut%s", y_port.wire->name)); else - module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset)); + module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name, y_port.offset)); } } diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index aba0ef5dd..313161fc3 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -922,7 +922,7 @@ std::unique_ptr AstNode::mktemp_logic(AstSrcLocType loc, const std::str { auto wire_owned = std::make_unique(loc, AST_WIRE, std::make_unique(loc, AST_RANGE, mkconst_int(loc, range_left, true), mkconst_int(loc, range_right, true))); auto* wire = wire_owned.get(); - wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++); + wire->str = stringf("%s%s:%d$%d", name, RTLIL::encode_filename(*location.begin.filename), location.begin.line, autoidx++); if (nosync) wire->set_attribute(ID::nosync, AstNode::mkconst_int(loc, 1, false)); wire->is_signed = is_signed; @@ -1773,7 +1773,7 @@ static std::string serialize_param_value(const RTLIL::Const &val) { std::string AST::derived_module_name(std::string stripped_name, const std::vector> ¶meters) { std::string para_info; for (const auto &elem : parameters) - para_info += stringf("%s=%s", elem.first.c_str(), serialize_param_value(elem.second).c_str()); + para_info += stringf("%s=%s", elem.first, serialize_param_value(elem.second)); if (para_info.size() > 60) return "$paramod$" + sha1(para_info) + stripped_name; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b53fa7a44..896ae9bdb 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -45,7 +45,7 @@ using namespace AST_INTERNAL; // helper function for creating RTLIL code for unary operations static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) { - IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++); + IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); RTLIL::Cell *cell = current_module->addCell(name, type); set_src_attr(cell, that); @@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s return; } - IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++); + IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); set_src_attr(cell, that); @@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s // helper function for creating RTLIL code for binary operations static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { - IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++); + IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); RTLIL::Cell *cell = current_module->addCell(name, type); set_src_attr(cell, that); @@ -199,7 +199,7 @@ struct AST_INTERNAL::LookaheadRewriter for (auto& c : node->id2ast->children) wire->children.push_back(c->clone()); wire->fixup_hierarchy_flags(); - wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); + wire->str = stringf("$lookahead%s$%d", node->str, autoidx++); wire->set_attribute(ID::nosync, AstNode::mkconst_int(node->location, 1, false)); wire->is_logic = true; while (wire->simplify(true, 1, -1, false)) { } @@ -348,7 +348,7 @@ struct AST_INTERNAL::ProcessGenerator LookaheadRewriter la_rewriter(always.get()); // generate process and simple root case - proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename).c_str(), always->location.begin.line, autoidx++)); + proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename), always->location.begin.line, autoidx++)); set_src_attr(proc, always.get()); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) @@ -814,7 +814,7 @@ struct AST_INTERNAL::ProcessGenerator IdString cellname; if (ast->str.empty()) - cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*ast->location.begin.filename).c_str(), ast->location.begin.line, autoidx++); + cellname = stringf("$%s$%s:%d$%d", flavor, RTLIL::encode_filename(*ast->location.begin.filename), ast->location.begin.line, autoidx++); else cellname = ast->str; check_unique_id(current_module, cellname, ast, "procedural assertion"); @@ -1568,7 +1568,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // This makes it possible for the hierarchy pass to see what are interface connections and then replace them // with the individual signals: if (is_interface) { - IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str()); + IdString dummy_wire_name = stringf("$dummywireforinterface%s", str); RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name); if (!dummy_wire) { dummy_wire = current_module->addWire(dummy_wire_name); @@ -2019,7 +2019,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) IdString cellname; if (str.empty()) - cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++); + cellname = stringf("$%s$%s:%d$%d", flavor, RTLIL::encode_filename(*location.begin.filename), location.begin.line, autoidx++); else cellname = str; check_unique_id(current_module, cellname, this, "procedural assertion"); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b1a615d76..bf72a770f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -968,10 +968,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin verbose_activate: if (mem2reg_set.count(mem) == 0) { - std::string message = stringf("Replacing memory %s with list of registers.", mem->str.c_str()); + std::string message = stringf("Replacing memory %s with list of registers.", mem->str); bool first_element = true; for (auto &place : mem2reg_places[it.first]) { - message += stringf("%s%s", first_element ? " See " : ", ", place.c_str()); + message += stringf("%s%s", first_element ? " See " : ", ", place); first_element = false; } log_warning("%s\n", message.c_str()); @@ -997,7 +997,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin for (int i = 0; i < mem_size; i++) { auto reg = std::make_unique(loc, AST_WIRE, std::make_unique(loc, AST_RANGE, mkconst_int(loc, data_range_left, true), mkconst_int(loc, data_range_right, true))); - reg->str = stringf("%s[%d]", node->str.c_str(), i); + reg->str = stringf("%s[%d]", node->str, i); reg->is_reg = true; reg->is_signed = node->is_signed; for (auto &it : node->attributes) @@ -2050,7 +2050,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin const char *second_part = children[1]->str.c_str(); if (second_part[0] == '\\') second_part++; - newNode->str = stringf("%s[%d].%s", str.c_str(), children[0]->integer, second_part); + newNode->str = stringf("%s[%d].%s", str, children[0]->integer, second_part); goto apply_newNode; } @@ -2767,7 +2767,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } else { this->dumpAst(NULL, " "); log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); - new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); + new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str); } } @@ -3119,7 +3119,7 @@ skip_dynamic_range_lvalue_expansion:; auto wire_tmp_owned = std::make_unique(location, AST_WIRE, std::make_unique(location, AST_RANGE, mkconst_int(location, width_hint-1, true), mkconst_int(location, 0, true))); auto wire_tmp = wire_tmp_owned.get(); - wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++); + wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line, autoidx++); current_scope[wire_tmp->str] = wire_tmp; current_ast_mod->children.push_back(std::move(wire_tmp_owned)); wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(location, 1, false)); @@ -3433,7 +3433,7 @@ skip_dynamic_range_lvalue_expansion:; auto* reg = reg_owned.get(); current_ast_mod->children.push_back(std::move(reg_owned)); - reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, myidx, i); + reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line, myidx, i); reg->is_reg = true; reg->is_signed = sign_hint; @@ -4754,7 +4754,7 @@ static void mark_memories_assign_lhs_complex(dict> & if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) { AstNode *mem = that->id2ast; if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS)) - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS; } } @@ -4782,14 +4782,14 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg // activate mem2reg if this is assigned in an async proc if (flags & AstNode::MEM2REG_FL_ASYNC) { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC)) - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC; } // remember if this is assigned blocking (=) if (type == AST_ASSIGN_EQ) { if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1)) - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line)); proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1; } @@ -4806,11 +4806,11 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg // remember where this is if (flags & MEM2REG_FL_INIT) { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT)) - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT; } else { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE)) - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE; } } @@ -4827,7 +4827,7 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg // flag if used after blocking assignment (in same proc) if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) { - mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line)); + mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(*location.begin.filename), location.begin.line)); mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2; } } @@ -5070,7 +5070,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, auto assign_reg = std::make_unique(location, type, std::make_unique(location, AST_IDENTIFIER), std::make_unique(location, AST_IDENTIFIER)); if (children[0]->children.size() == 2) assign_reg->children[0]->children.push_back(children[0]->children[1]->clone()); - assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str.c_str(), i); + assign_reg->children[0]->str = stringf("%s[%d]", children[0]->str, i); assign_reg->children[1]->str = id_data; cond_node->children[1]->children.push_back(std::move(assign_reg)); case_node->children.push_back(std::move(cond_node)); @@ -5108,7 +5108,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, (right <= id && id <= left); if (valid_const_access) { - str = stringf("%s[%d]", str.c_str(), id); + str = stringf("%s[%d]", str, id); delete_children(); range_valid = false; id2ast = nullptr; @@ -5185,7 +5185,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, auto assign_reg = std::make_unique(location, AST_ASSIGN_EQ, std::make_unique(location, AST_IDENTIFIER), std::make_unique(location, AST_IDENTIFIER)); assign_reg->children[0]->str = id_data; assign_reg->children[0]->was_checked = true; - assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i); + assign_reg->children[1]->str = stringf("%s[%d]", str, i); cond_node->children[1]->children.push_back(std::move(assign_reg)); case_node->children.push_back(std::move(cond_node)); } diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index ec3952661..4a9ce4b8a 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -168,7 +168,7 @@ struct RpcModule : RTLIL::Module { std::string parameter_info; for (auto ¶m : parameters) { log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second))); - parameter_info += stringf("%s=%s", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second))); + parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second))); } std::string derived_name; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 7284c7cd9..d4bedf44f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -129,7 +129,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil message += vstringf(msg, args); if (log_verific_callback) { - string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); + string full_message = stringf("%s%s\n", message_prefix, message); #ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, @@ -232,7 +232,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) { std::string s = stringf("$verific$%s", obj->Name()); if (obj->Linefile()) - s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())).c_str(), Verific::LineFile::GetLineNo(obj->Linefile())); + s += stringf("$%s:%d", RTLIL::encode_filename(Verific::LineFile::GetFileName(obj->Linefile())), Verific::LineFile::GetLineNo(obj->Linefile())); s += stringf("$%d", autoidx++); return s; } @@ -472,7 +472,7 @@ void VerificImporter::import_attributes(dict &att if (nl->IsFromVerilog()) { auto const value = verific_const(type_name, v, nl, false); - attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k)); + attributes.emplace(stringf("\\enum_value_%s", value.as_string()), RTLIL::escape_id(k)); } #ifdef VERIFIC_VHDL_SUPPORT else if (nl->IsFromVhdl()) { @@ -1926,7 +1926,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : - RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd)); + RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memrd)); cell->parameters[ID::MEMID] = memory->name.str(); cell->parameters[ID::CLK_ENABLE] = false; cell->parameters[ID::CLK_POLARITY] = true; @@ -1956,7 +1956,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : - RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr)); + RTLIL::IdString(stringf("%s_%d", inst_name, i)), ID($memwr)); cell->parameters[ID::MEMID] = memory->name.str(); cell->parameters[ID::CLK_ENABLE] = false; cell->parameters[ID::CLK_POLARITY] = true; diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 60d8292b8..8b98997f6 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1031,12 +1031,12 @@ struct VerificSvaImporter [[noreturn]] void parser_error(std::string errmsg, linefile_type loc) { - parser_error(stringf("%s at %s:%d.\n", errmsg.c_str(), LineFile::GetFileName(loc), LineFile::GetLineNo(loc))); + parser_error(stringf("%s at %s:%d.\n", errmsg, LineFile::GetFileName(loc), LineFile::GetLineNo(loc))); } [[noreturn]] void parser_error(std::string errmsg, Instance *inst) { - parser_error(stringf("%s at %s (%s)", errmsg.c_str(), inst->View()->Owner()->Name(), inst->Name()), inst->Linefile()); + parser_error(stringf("%s at %s (%s)", errmsg, inst->View()->Owner()->Name(), inst->Name()), inst->Linefile()); } [[noreturn]] void parser_error(Instance *inst) diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 6dff1b6fc..7d011b68e 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -265,7 +265,7 @@ struct arg_map_t // (something like macro_foobar_arg2). This doesn't include the leading backtick. static std::string str_token(const std::string ¯o_name, int pos) { - return stringf("macro_%s_arg%d", macro_name.c_str(), pos); + return stringf("macro_%s_arg%d", macro_name, pos); } // Return definitions for the macro arguments (so that substituting in the macro body and diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 392d8921a..f4ae53a9c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -323,7 +323,7 @@ // create a unique name for the genvar std::string old_str = decl->str; - std::string new_str = stringf("$genfordecl$%d$%s", autoidx++, old_str.c_str()); + std::string new_str = stringf("$genfordecl$%d$%s", autoidx++, old_str); // rename and move the genvar declaration to the containing description decl->str = new_str; diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index c7bc34dd9..35e7a2865 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -33,8 +33,8 @@ FstData::FstData(std::string filename) : ctx(nullptr) std::string filename_trim = file_base_name(filename); if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vcd") == 0) { filename_trim.erase(filename_trim.size()-4); - tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir().c_str(), filename_trim.c_str()); - std::string cmd = stringf("vcd2fst %s %s", filename.c_str(), tmp_file.c_str()); + tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir(), filename_trim); + std::string cmd = stringf("vcd2fst %s %s", filename, tmp_file); log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); diff --git a/kernel/io.cc b/kernel/io.cc index 62cf6b7f4..4c593501c 100644 --- a/kernel/io.cc +++ b/kernel/io.cc @@ -307,7 +307,7 @@ bool is_absolute_path(std::string filename) void remove_directory(std::string dirname) { #ifdef _WIN32 - run_command(stringf("rmdir /s /q \"%s\"", dirname.c_str())); + run_command(stringf("rmdir /s /q \"%s\"", dirname)); #else struct stat stbuf; struct dirent **namelist; @@ -315,7 +315,7 @@ void remove_directory(std::string dirname) log_assert(n >= 0); for (int i = 0; i < n; i++) { if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) { - std::string buffer = stringf("%s/%s", dirname.c_str(), namelist[i]->d_name); + std::string buffer = stringf("%s/%s", dirname, namelist[i]->d_name); if (!stat(buffer.c_str(), &stbuf) && S_ISREG(stbuf.st_mode)) { remove(buffer.c_str()); } else diff --git a/kernel/log.cc b/kernel/log.cc index 011071439..3203ed3cf 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -791,7 +791,7 @@ dict> get_coverage_data() dict> coverage_data; for (auto &it : pass_register) { - std::string key = stringf("passes.%s", it.first.c_str()); + std::string key = stringf("passes.%s", it.first); coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__); coverage_data[key].second += it.second->call_counter; } diff --git a/kernel/mem.cc b/kernel/mem.cc index 67501acfd..f614a1f81 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -900,7 +900,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { if (width) { - SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width); + SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid, idx), width); SigSpec sig_d; int pos = 0; @@ -910,7 +910,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { port.addr[i] = sig_q[pos++]; } - c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity); + c = module->addDff(stringf("$%s$rdreg[%d]", memid, idx), port.clk, sig_d, sig_q, port.clk_polarity); } else { c = nullptr; } @@ -919,7 +919,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { { log_assert(port.arst == State::S0 || port.srst == State::S0); - SigSpec async_d = module->addWire(stringf("$%s$rdreg[%d]$d", memid.c_str(), idx), GetSize(port.data)); + SigSpec async_d = module->addWire(stringf("$%s$rdreg[%d]$d", memid, idx), GetSize(port.data)); SigSpec sig_d = async_d; for (int i = 0; i < GetSize(wr_ports); i++) { @@ -942,7 +942,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { raddr = port.sub_addr(sub); SigSpec addr_eq; if (raddr != waddr) - addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid.c_str(), idx, i, sub), raddr, waddr); + addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub), raddr, waddr); int pos = 0; int ewidth = width << min_wide_log2; int wsub = wide_write ? sub : 0; @@ -955,10 +955,10 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { SigSpec other = port.transparency_mask[i] ? wport.data.extract(pos + wsub * width, epos-pos) : Const(State::Sx, epos-pos); SigSpec cond; if (raddr != waddr) - cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid.c_str(), idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq); + cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq); else cond = wport.en[pos + wsub * width]; - SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid.c_str(), idx, i, sub, pos), cur, other, cond); + SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), cur, other, cond); sig_d.replace(pos + rsub * width, merged); pos = epos; } @@ -966,7 +966,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { } } - IdString name = stringf("$%s$rdreg[%d]", memid.c_str(), idx); + IdString name = stringf("$%s$rdreg[%d]", memid, idx); FfData ff(module, initvals, name); ff.width = GetSize(port.data); ff.has_clk = true; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0250346d1..13f6b1075 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2773,7 +2773,7 @@ RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index) } while (1) { - RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index); + RTLIL::IdString new_name = stringf("%s_%d", name, index); if (count_id(new_name) == 0) return new_name; index++; diff --git a/kernel/satgen.h b/kernel/satgen.h index 996eaf9fb..7815847b3 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -103,7 +103,7 @@ struct SatGen } else { std::string wire_name = RTLIL::unescape_id(bit.wire->name); std::string name = pf + - (bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset)); + (bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset)); vec.push_back(ez->frozen_literal(name)); imported_signals[pf][bit] = vec.back(); } diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index e970779d7..31d008404 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -89,7 +89,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); } else { - std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name.c_str(), it.first.c_str()); + std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name, it.first); Tcl_Eval(interp, tcl_script.c_str()); } } diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 196b78186..68e107a3b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -287,7 +287,7 @@ RTLIL::IdString new_id(std::string file, int line, std::string func) if (pos != std::string::npos) func = func.substr(pos+1); - return stringf("$auto$%s:%d:%s$%d", file.c_str(), line, func.c_str(), autoidx++); + return stringf("$auto$%s:%d:%s$%d", file, line, func, autoidx++); } RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix) @@ -304,7 +304,7 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std: if (pos != std::string::npos) func = func.substr(pos+1); - return stringf("$auto$%s:%d:%s$%s$%d", file.c_str(), line, func.c_str(), suffix.c_str(), autoidx++); + return stringf("$auto$%s:%d:%s$%s$%d", file, line, func, suffix, autoidx++); } RTLIL::Design *yosys_get_design() @@ -320,7 +320,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter) str += stringf("(%d) ", recursion_counter); str += "yosys"; if (!design->selected_active_module.empty()) - str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str()); + str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module)); if (!design->full_selection()) { if (design->selected_active_module.empty()) str += "*"; diff --git a/libs/subcircuit/subcircuit.cc b/libs/subcircuit/subcircuit.cc index 60f27fd55..8c8d3d92d 100644 --- a/libs/subcircuit/subcircuit.cc +++ b/libs/subcircuit/subcircuit.cc @@ -411,7 +411,7 @@ class SubCircuit::SolverWorker std::string toString() const { - return my_stringf("%s[%d]:%s[%d]", fromPort.c_str(), fromBit, toPort.c_str(), toBit); + return my_stringf("%s[%d]:%s[%d]", fromPort, fromBit, toPort, toBit); } }; @@ -444,7 +444,7 @@ class SubCircuit::SolverWorker std::string str; bool firstPort = true; for (const auto &it : portSizes) { - str += my_stringf("%s%s[%d]", firstPort ? "" : ",", it.first.c_str(), it.second); + str += my_stringf("%s%s[%d]", firstPort ? "" : ",", it.first, it.second); firstPort = false; } return typeId + "(" + str + ")"; diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 08dc76dda..d48e25d68 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -126,14 +126,14 @@ struct BugpointPass : public Pass { string bugpoint_file = "bugpoint-case"; if (suffix.size()) - bugpoint_file += stringf(".%.8s", suffix.c_str()); + bugpoint_file += stringf(".%.8s", suffix); std::ofstream f(bugpoint_file + ".il"); RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); f.close(); - string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner.c_str(), yosys_cmd.c_str(), bugpoint_file.c_str(), yosys_arg.c_str(), bugpoint_file.c_str()); - if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file.c_str()); + string yosys_cmdline = stringf("%s %s -qq -L %s.log %s %s.il", runner, yosys_cmd, bugpoint_file, yosys_arg, bugpoint_file); + if (catch_err) yosys_cmdline += stringf(" 2>%s.err", bugpoint_file); auto status = run_command(yosys_cmdline); // we're not processing lines, which means we're getting raw system() returns if(WIFEXITED(status)) @@ -156,7 +156,7 @@ struct BugpointPass : public Pass { string bugpoint_file = "bugpoint-case"; if (suffix.size()) - bugpoint_file += stringf(".%.8s", suffix.c_str()); + bugpoint_file += stringf(".%.8s", suffix); bugpoint_file += err ? ".err" : ".log"; std::ifstream f(bugpoint_file); @@ -469,13 +469,13 @@ struct BugpointPass : public Pass { if (args[argidx] == "-script" && argidx + 1 < args.size()) { if (!yosys_arg.empty()) log_cmd_error("A -script or -command option can be only provided once!\n"); - yosys_arg = stringf("-s %s", args[++argidx].c_str()); + yosys_arg = stringf("-s %s", args[++argidx]); continue; } if (args[argidx] == "-command" && argidx + 1 < args.size()) { if (!yosys_arg.empty()) log_cmd_error("A -script or -command option can be only provided once!\n"); - yosys_arg = stringf("-p %s", args[++argidx].c_str()); + yosys_arg = stringf("-p %s", args[++argidx]); continue; } if (args[argidx] == "-grep" && argidx + 1 < args.size()) { diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 3017630a6..b532b4527 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -322,7 +322,7 @@ struct CheckPass : public Pass { if (wire_drivers.count(state)) { string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state)); for (auto str : wire_drivers[state]) - message += stringf(" %s\n", str.c_str()); + message += stringf(" %s\n", str); log_warning("%s", message.c_str()); counter++; } @@ -331,7 +331,7 @@ struct CheckPass : public Pass { if (wire_drivers_count[it.first] > 1) { string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first)); for (auto str : it.second) - message += stringf(" %s\n", str.c_str()); + message += stringf(" %s\n", str); log_warning("%s", message.c_str()); counter++; } @@ -394,10 +394,10 @@ struct CheckPass : public Pass { std::string driver_src; if (driver->has_attribute(ID::src)) { std::string src_attr = driver->get_src_attribute(); - driver_src = stringf(" source: %s", src_attr.c_str()); + driver_src = stringf(" source: %s", src_attr); } - message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str()); + message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src); if (!coarsened_cells.count(driver)) { MatchingEdgePrinter printer(message, sigmap, prev, bit); @@ -411,9 +411,9 @@ struct CheckPass : public Pass { std::string wire_src; if (wire->has_attribute(ID::src)) { std::string src_attr = wire->get_src_attribute(); - wire_src = stringf(" source: %s", src_attr.c_str()); + wire_src = stringf(" source: %s", src_attr); } - message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str()); + message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src); } prev = bit; diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 347c8efa4..068b5d7d9 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -372,7 +372,7 @@ struct DftTagWorker { void propagate_tags(Cell *cell) { if (cell->type == ID($set_tag)) { - IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); if (all_tags.insert(tag).second) { auto group_sep = tag.str().find(':'); IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag; @@ -478,7 +478,7 @@ struct DftTagWorker { void process_cell(IdString tag, Cell *cell) { if (cell->type == ID($set_tag)) { - IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A)); auto &sig_y = cell->getPort(ID::Y); @@ -752,7 +752,7 @@ struct DftTagWorker { for (auto cell : get_tag_cells) { auto &sig_a = cell->getPort(ID::A); - IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); tag_signal(tag, sig_a); } @@ -772,7 +772,7 @@ struct DftTagWorker { continue; int index = 0; - auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index); + auto name = module->uniquify(stringf("%s:%s", wire->name, tag.c_str() + 1), index); auto hdlname = wire->get_hdlname_attribute(); if (!hdlname.empty()) @@ -817,7 +817,7 @@ struct DftTagWorker { for (auto cell : get_tag_cells) { auto &sig_a = cell->getPort(ID::A); auto &sig_y = cell->getPort(ID::Y); - IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string()); auto tag_sig = tag_signal(tag, sig_a); module->connect(sig_y, tag_sig); diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 0c321eba6..60324702c 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -163,7 +163,7 @@ private: std::vector next_pmux_y_ports, pmux_y_ports(costs.begin(), costs.begin() + exp2(select_width)); for (auto i = 0; pmux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(pmux_y_ports); j += 2) { - next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.c_str(), i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute())); + next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name, i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->get_src_attribute())); } if (GetSize(pmux_y_ports) % 2 == 1) next_pmux_y_ports.push_back(pmux_y_ports[GetSize(pmux_y_ports) - 1]); @@ -206,7 +206,7 @@ private: int num_versions = opt_instrumentmore? 8 : 4; for (auto i = 1; i <= num_versions; ++i) - taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1))); + taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1))); for (auto i = 0; i < num_versions; ++i) { switch(i) { @@ -239,7 +239,7 @@ private: std::vector next_meta_mux_y_ports, meta_mux_y_ports(taint_version); for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) { - next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); + next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); } if (GetSize(meta_mux_y_ports) % 2 == 1) next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]); @@ -271,7 +271,7 @@ private: log_assert(exp2(select_width) == num_versions); for (auto i = 1; i <= num_versions; ++i) - taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name.c_str(), i), 1))); + taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1))); for (auto i = 0; i < num_versions; ++i) { switch(i) { @@ -294,7 +294,7 @@ private: std::vector next_meta_mux_y_ports, meta_mux_y_ports(taint_version); for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) { - next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name.c_str(), i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); + next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); } if (GetSize(meta_mux_y_ports) % 2 == 1) next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]); diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 97682efbb..73ca98d88 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -243,7 +243,7 @@ struct PortarcsPass : Pass { if (draw_mode) { auto bit_str = [](SigBit bit) { - return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()).c_str(), bit.offset); + return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset); }; std::vector headings; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 167997dc0..1f3d0992e 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -64,7 +64,7 @@ static std::string derive_name_from_src(const std::string &src, int counter) if (src_base.empty()) return stringf("$%d", counter); else - return stringf("\\%s$%d", src_base.c_str(), counter); + return stringf("\\%s$%d", src_base, counter); } static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, string suffix, bool move_to_cell) @@ -422,7 +422,7 @@ struct RenamePass : public Pass { if (wire_suffix.empty()) { for (auto const &[port, _] : cell->connections()) { if (cell->output(port)) { - wire_suffix += stringf("%s.%s", cell->type.c_str(), port.c_str() + 1); + wire_suffix += stringf("%s.%s", cell->type, port.c_str() + 1); break; } } @@ -449,7 +449,7 @@ struct RenamePass : public Pass { for (auto wire : module->selected_wires()) if (wire->name[0] == '$') { RTLIL::IdString buf; - do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); + do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); while (module->wire(buf) != nullptr); new_wire_names[wire] = buf; } @@ -457,7 +457,7 @@ struct RenamePass : public Pass { for (auto cell : module->selected_cells()) if (cell->name[0] == '$') { RTLIL::IdString buf; - do buf = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); + do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); while (module->cell(buf) != nullptr); new_cell_names[cell] = buf; } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 4eb6569e6..9ea29bc4e 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -149,7 +149,7 @@ struct ShowWorker { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { - return stringf("color=\"%s\", fontcolor=\"%s\"", s.first.c_str(), s.first.c_str()); + return stringf("color=\"%s\", fontcolor=\"%s\"", s.first, s.first); } RTLIL::Const colorattr_value; @@ -308,11 +308,11 @@ struct ShowWorker std::string repinfo = rep > 1 ? stringf("%dx ", rep) : ""; std::string portside = stringf("%d:%d", bitpos, bitpos - rep*c.width + 1); - std::string remoteside = stringf("%s%d:%d", repinfo.c_str(), cl, cr); + std::string remoteside = stringf("%s%d:%d", repinfo, cl, cr); if (driver) { log_assert(!net.empty()); - label_pieces.push_back(stringf(" %s - %s ", chunk_idx, portside.c_str(), remoteside.c_str())); + label_pieces.push_back(stringf(" %s - %s ", chunk_idx, portside, remoteside)); net_conn_map[net].in.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width}); net_conn_map[net].color = nextColor(c, net_conn_map[net].color); } else { @@ -325,7 +325,7 @@ struct ShowWorker c.data.front() == State::Sz ? 'Z' : '?', bitpos, bitpos-rep*c.width+1)); } else { - label_pieces.push_back(stringf(" %s - %s ", chunk_idx, remoteside.c_str(), portside.c_str())); + label_pieces.push_back(stringf(" %s - %s ", chunk_idx, remoteside, portside)); net_conn_map[net].out.insert({stringf("x%d:s%d", dot_idx, chunk_idx), rep*c.width}); net_conn_map[net].color = nextColor(c, net_conn_map[net].color); } @@ -335,14 +335,14 @@ struct ShowWorker } code += stringf("x%d [ shape=record, style=rounded, label=\"", dot_idx) \ - + join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig).c_str()); + + join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig)); if (!port.empty()) { currentColor = xorshift32(currentColor); if (driver) - code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port.c_str(), dot_idx, nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); + code += stringf("%s:e -> x%d:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", port, dot_idx, nextColor(sig), widthLabel(sig.size())); else - code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port.c_str(), nextColor(sig).c_str(), widthLabel(sig.size()).c_str()); + code += stringf("x%d:e -> %s:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, %s, %s];\n", dot_idx, port, nextColor(sig), widthLabel(sig.size())); } if (node != nullptr) *node = stringf("x%d", dot_idx); @@ -490,7 +490,7 @@ struct ShowWorker std::string in_label = join_label_pieces(in_label_pieces); std::string out_label = join_label_pieces(out_label_pieces); - std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label.c_str(), + std::string label_string = stringf("{{%s}|%s\\n%s|{%s}}", in_label, findLabel(cell->name.str()), escape(cell->type.str()), out_label.c_str()); @@ -904,8 +904,8 @@ struct ShowPass : public Pass { if (libs.size() > 0) log_header(design, "Continuing show pass.\n"); - std::string dot_file = stringf("%s.dot", prefix.c_str()); - std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str()); + std::string dot_file = stringf("%s.dot", prefix); + std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format); log("Writing dot description to `%s'.\n", dot_file.c_str()); FILE *f = fopen(dot_file.c_str(), "w"); @@ -932,7 +932,7 @@ struct ShowPass : public Pass { #else #define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'" #endif - std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str()); + std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD log("Exec: %s\n", cmd.c_str()); #if !defined(YOSYS_DISABLE_SPAWN) @@ -950,9 +950,9 @@ struct ShowPass : public Pass { // system()/cmd.exe does not understand single quotes nor // background tasks on Windows. So we have to pause yosys // until the viewer exits. - std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str()); + std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file); #else - std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str()); + std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) @@ -960,9 +960,9 @@ struct ShowPass : public Pass { } else if (format.empty()) { #ifdef __APPLE__ - std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background); #else - std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 07b1e5228..ebbd10b5c 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -193,19 +193,19 @@ struct statdata_t { int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0; int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0; int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0; - cell_type = stringf("%s_%d", cell_type.c_str(), max({width_a, width_b, width_y})); + cell_type = stringf("%s_%d", cell_type, max({width_a, width_b, width_y})); } else if (cell_type.in(ID($mux))) - cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y))); + cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y))); else if (cell_type.in(ID($bmux), ID($pmux))) cell_type = - stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S))); + stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S))); else if (cell_type == ID($demux)) cell_type = - stringf("%s_%d_%d", cell_type.c_str(), GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S))); + stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S))); else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch), ID($dlatchsr))) - cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q))); + cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q))); } if (!cell_area.empty()) { diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 05dd2a4b3..f0e4943de 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -320,7 +320,7 @@ struct EstimateSta { std::string cell_src; if (cell->has_attribute(ID::src)) { std::string src_attr = cell->get_src_attribute(); - cell_src = stringf(" source: %s", src_attr.c_str()); + cell_src = stringf(" source: %s", src_attr); } log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str()); printed.insert(cell); @@ -331,7 +331,7 @@ struct EstimateSta { std::string wire_src; if (bit.wire && bit.wire->has_attribute(ID::src)) { std::string src_attr = bit.wire->get_src_attribute(); - wire_src = stringf(" source: %s", src_attr.c_str()); + wire_src = stringf(" source: %s", src_attr); } log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]); } diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 4c73b4d71..323b9cb34 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -982,8 +982,8 @@ struct VizPass : public Pass { if (modlist.empty()) log_cmd_error("Nothing there to show.\n"); - std::string dot_file = stringf("%s.dot", prefix.c_str()); - std::string out_file = stringf("%s.%s", prefix.c_str(), format.empty() ? "svg" : format.c_str()); + std::string dot_file = stringf("%s.dot", prefix); + std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format); if (custom_prefix) yosys_output_files.insert(dot_file); @@ -1026,7 +1026,7 @@ struct VizPass : public Pass { #else #define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'" #endif - std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str()); + std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD log("Exec: %s\n", cmd.c_str()); #if !defined(YOSYS_DISABLE_SPAWN) @@ -1043,9 +1043,9 @@ struct VizPass : public Pass { // system()/cmd.exe does not understand single quotes nor // background tasks on Windows. So we have to pause yosys // until the viewer exits. - std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str()); + std::string cmd = stringf("%s \"%s\"", viewer_exe, out_file); #else - std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str()); + std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) @@ -1053,9 +1053,9 @@ struct VizPass : public Pass { } else if (format.empty()) { #ifdef __APPLE__ - std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file, dot_file, background); #else - std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc index 0c15848e4..e25d34775 100644 --- a/passes/cmds/wrapcell.cc +++ b/passes/cmds/wrapcell.cc @@ -97,9 +97,9 @@ struct Chunk { if (len == cell->getPort(port).size()) return port; else if (len == 1) - return stringf("%s[%d]", port.c_str(), base); + return stringf("%s[%d]", port, base); else - return stringf("%s[%d:%d]", port.c_str(), base + len - 1, base); + return stringf("%s[%d:%d]", port, base + len - 1, base); } SigSpec sample(Cell *cell) diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index d2d0c4d8e..186e5eec0 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -978,8 +978,8 @@ struct XpropWorker if (wire->port_input == wire->port_output) { log_warning("Port %s not an input or an output port which is not supported by xprop\n", log_id(wire)); } else if ((options.split_inputs && !options.assume_def_inputs && wire->port_input) || (options.split_outputs && wire->port_output)) { - auto port_d = module->uniquify(stringf("%s_d", port.c_str())); - auto port_x = module->uniquify(stringf("%s_x", port.c_str())); + auto port_d = module->uniquify(stringf("%s_d", port)); + auto port_x = module->uniquify(stringf("%s_x", port)); auto wire_d = module->addWire(port_d, GetSize(wire)); auto wire_x = module->addWire(port_x, GetSize(wire)); @@ -1031,8 +1031,8 @@ struct XpropWorker continue; int index_d = 0; int index_x = 0; - auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()), index_d); - auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()), index_x); + auto name_d = module->uniquify(stringf("%s_d", wire->name), index_d); + auto name_x = module->uniquify(stringf("%s_x", wire->name), index_x); auto hdlname = wire->get_hdlname_attribute(); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 143ae7b54..a0fd50097 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm)); + RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm)); fsm_cell->setPort(ID::CLK, clk); fsm_cell->setPort(ID::ARST, arst); fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0; @@ -390,7 +390,7 @@ static void extract_fsm(RTLIL::Wire *wire) module->wires_.erase(wire->name); wire->attributes.erase(ID::fsm_encoding); - wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); + wire->name = stringf("$fsm$oldstate%s", wire->name); module->wires_[wire->name] = wire; if(wire->attributes.count(ID::hdlname)) { auto hdlname = wire->get_hdlname_attribute(); diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 299b18006..17bd6e340 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -281,11 +281,11 @@ struct FlattenWorker if (attr.first == ID::hdlname) scopeinfo->attributes.insert(attr); else - scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second); + scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second); } for (auto const &attr : tpl->attributes) - scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second); + scopeinfo->attributes.emplace(stringf("\\module_%s", RTLIL::unescape_id(attr.first)), attr.second); scopeinfo->attributes.emplace(ID(module), RTLIL::unescape_id(tpl->name)); } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index facc5d173..8d88a8919 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -166,7 +166,7 @@ struct SubmodWorker } } else if (hidden_mode) - new_wire_name = stringf("$submod%s", new_wire_name.c_str()); + new_wire_name = stringf("$submod%s", new_wire_name); } RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width); diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 9db329c5c..9bc8ad9b0 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -873,7 +873,7 @@ grow_read_ports:; for (int grid_a = 0; grid_a < acells; grid_a++) for (int dupidx = 0; dupidx < dup_count; dupidx++) { - Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid.c_str(), grid_d, grid_a, dupidx)), bram.name); + Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid, grid_d, grid_a, dupidx)), bram.name); log(" Creating %s cell at grid position <%d %d %d>: %s\n", log_id(bram.name), grid_d, grid_a, dupidx, log_id(c)); for (auto &vp : variant_params) diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index a5b30c7ae..4c7d9636d 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -1686,7 +1686,7 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, const PortVariant &pdef, const char *name, int wpidx, int rpidx, const std::vector &hw_addr_swizzle) { for (auto &it: pdef.options) for (auto cell: cells) - cell->setParam(stringf("\\PORT_%s_OPTION_%s", name, it.first.c_str()), it.second); + cell->setParam(stringf("\\PORT_%s_OPTION_%s", name, it.first), it.second); SigSpec addr = Const(State::Sx, cfg.def->abits); int wide_log2 = 0, wr_wide_log2 = 0, rd_wide_log2 = 0; SigSpec clk = State::S0; @@ -2067,7 +2067,7 @@ void MemMapping::emit(const MemConfig &cfg) { for (int rp = 0; rp < cfg.repl_port; rp++) { std::vector cells; for (int rd = 0; rd < cfg.repl_d; rd++) { - Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid.c_str(), rp, rd), cfg.def->id); + Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid, rp, rd), cfg.def->id); if (cfg.def->width_mode == WidthMode::Global) cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]); if (cfg.def->widthscale) { @@ -2077,18 +2077,18 @@ void MemMapping::emit(const MemConfig &cfg) { cell->setParam(ID::BITS_USED, val); } for (auto &it: cfg.def->options) - cell->setParam(stringf("\\OPTION_%s", it.first.c_str()), it.second); + cell->setParam(stringf("\\OPTION_%s", it.first), it.second); for (int i = 0; i < GetSize(cfg.def->shared_clocks); i++) { auto &cdef = cfg.def->shared_clocks[i]; auto &ccfg = cfg.shared_clocks[i]; if (cdef.anyedge) { - cell->setParam(stringf("\\CLK_%s_POL", cdef.name.c_str()), ccfg.used ? ccfg.polarity : true); - cell->setPort(stringf("\\CLK_%s", cdef.name.c_str()), ccfg.used ? ccfg.clk : State::S0); + cell->setParam(stringf("\\CLK_%s_POL", cdef.name), ccfg.used ? ccfg.polarity : true); + cell->setPort(stringf("\\CLK_%s", cdef.name), ccfg.used ? ccfg.clk : State::S0); } else { SigSpec sig = ccfg.used ? ccfg.clk : State::S0; if (ccfg.used && ccfg.invert) sig = mem.module->Not(NEW_ID, sig); - cell->setPort(stringf("\\CLK_%s", cdef.name.c_str()), sig); + cell->setPort(stringf("\\CLK_%s", cdef.name), sig); } } if (cfg.def->init == MemoryInitKind::Any || cfg.def->init == MemoryInitKind::NoUndef) { @@ -2136,11 +2136,11 @@ void MemMapping::emit(const MemConfig &cfg) { } if (pg.optional) for (auto cell: cells) - cell->setParam(stringf("\\PORT_%s_USED", pg.names[pi].c_str()), used); + cell->setParam(stringf("\\PORT_%s_USED", pg.names[pi]), used); if (pg.optional_rw) for (auto cell: cells) { - cell->setParam(stringf("\\PORT_%s_RD_USED", pg.names[pi].c_str()), used_r); - cell->setParam(stringf("\\PORT_%s_WR_USED", pg.names[pi].c_str()), used_w); + cell->setParam(stringf("\\PORT_%s_RD_USED", pg.names[pi]), used_r); + cell->setParam(stringf("\\PORT_%s_WR_USED", pg.names[pi]), used_w); } } } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index d1dd0fd88..126ec65b5 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -244,7 +244,7 @@ struct MemoryMapWorker data_reg_in[idx] = w_in; c->setPort(ID::D, w_in); - std::string w_out_name = stringf("%s[%d]", mem.memid.c_str(), addr); + std::string w_out_name = stringf("%s[%d]", mem.memid, addr); if (module->wires_.count(w_out_name) > 0) w_out_name = genid(mem.memid, "", addr, "$q"); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 22aa9d7d3..e5957df08 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -2201,7 +2201,7 @@ skip_alu_split: { if (cmp_type == ID($lt)) cmp_name = "<"; if (cmp_type == ID($le)) cmp_name = "<="; - condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig)); + condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig)); replacement = "constant 1"; replace_sig[0] = State::S1; replace = true; @@ -2210,7 +2210,7 @@ skip_alu_split: { if (cmp_type == ID($gt)) cmp_name = ">"; if (cmp_type == ID($ge)) cmp_name = ">="; - condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig)); + condition = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name, log_signal(const_sig)); replacement = "constant 0"; replace_sig[0] = State::S0; replace = true; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 61e7f4960..21afdf134 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s else { // create compare cell - RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq)); + RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq)); apply_attrs(eq_cell, sw, cs); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 6b94cbe19..db1eaad4b 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -72,7 +72,7 @@ struct Clk2fflogicPass : public Pass { } std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig)); if (is_fine) module->addFfGate(NEW_ID, sig, sampled_sig); @@ -84,7 +84,7 @@ struct Clk2fflogicPass : public Pass { SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) { std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig)); if (is_fine) module->addFfGate(NEW_ID, sig, sampled_sig); @@ -98,7 +98,7 @@ struct Clk2fflogicPass : public Pass { sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); - Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig)); + Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = init; Cell *cell; diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 485e44fd6..7522d716e 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -129,7 +129,7 @@ struct CutpointPass : public Pass { if (attr.first == ID::hdlname) scopeinfo->attributes.insert(attr); else - scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first).c_str()), attr.second); + scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second); } } diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index bdab9d5f4..7008e35e1 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -263,7 +263,7 @@ struct VlogHammerReporter RTLIL::SigSpec sig(wire); if (!ce.eval(sig)) log_error("Can't read back value for port %s!\n", log_id(inputs[i])); - input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str()); + input_pattern_list += stringf(" %s", sig.as_const().as_string()); log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str()); } } diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 575b2f40d..2d31822c4 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -44,7 +44,7 @@ struct FmcombineWorker FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) : opts(opts), design(design), original(design->module(orig_type)), - orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str())) + orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type)) { } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 6063c5ab9..870df7b55 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -595,9 +595,9 @@ struct FreduceWorker void dump() { - std::string filename = stringf("%s_%s_%05d.il", dump_prefix.c_str(), RTLIL::id2cstr(module->name), reduce_counter); + std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str()); - Pass::call(design, stringf("dump -outfile %s %s", filename.c_str(), design->selected_active_module.empty() ? module->name.c_str() : "")); + Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); } int run() diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 43373ce0e..7aef9ea38 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -570,7 +570,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena string str = "mutate"; if (!opts.ctrl_name.empty()) str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++); - str += stringf(" -mode %s", entry.mode.c_str()); + str += stringf(" -mode %s", entry.mode); if (!entry.module.empty()) str += stringf(" -module %s", log_id(entry.module)); if (!entry.cell.empty()) @@ -586,7 +586,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena if (entry.wirebit >= 0) str += stringf(" -wirebit %d", entry.wirebit); for (auto &s : entry.src) - str += stringf(" -src %s", s.c_str()); + str += stringf(" -src %s", s); if (filename.empty()) log("%s\n", str.c_str()); else diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index 7a7a31806..c7ddb9168 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -219,14 +219,14 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, const std::string smtbmc_warning = "z3: WARNING:"; const std::string smtbmc_cmd = stringf("\"%s\" -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1", yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(), - (opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(), + (opt.timeout != 0? stringf("--timeout %d", opt.timeout) : ""), (opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(), tempdir_name.c_str(), iter_num); std::string smt2_command = "write_smt2 -stbv -wires "; for (auto &solver_opt : opt.solver_options) - smt2_command += stringf("-solver-option %s %s ", solver_opt.first.c_str(), solver_opt.second.c_str()); - smt2_command += stringf("%s/problem%d.smt2", tempdir_name.c_str(), iter_num); + smt2_command += stringf("-solver-option %s %s ", solver_opt.first, solver_opt.second); + smt2_command += stringf("%s/problem%d.smt2", tempdir_name, iter_num); Pass::call(mod->design, smt2_command); auto process_line = [&ret, &smtbmc_warning, &opt, &quiet](const std::string &line) { diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc index 7ed8b1304..7939a64e0 100644 --- a/passes/sat/recover_names.cc +++ b/passes/sat/recover_names.cc @@ -380,7 +380,7 @@ struct RecoverModuleWorker { if (root2buffered.count(gate_bit)) { int buf_idx = 0; for (auto buf_bit : root2buffered.at(gate_bit)) { - std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name.c_str(), ++buf_idx); + std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name, ++buf_idx); if (buf_name_str[0] == '\\') buf_name_str[0] = '$'; rename_map[buf_bit] = std::make_pair( @@ -396,7 +396,7 @@ struct RecoverModuleWorker { bool must_invert_name = rule.second.first.inverted; while (must_invert_name || (mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) { - std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name.c_str(), + std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name, rule.second.first.inverted ? "inv" : "dup", ++dup_idx); if (new_name_str[0] == '\\') new_name_str[0] = '$'; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index e2b0022ff..044bd8acb 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2095,12 +2095,12 @@ struct SimWorker : SimShared std::stringstream f; if (wire->width==1) - f << stringf("%s", RTLIL::unescape_id(wire->name).c_str()); + f << stringf("%s", RTLIL::unescape_id(wire->name)); else if (wire->upto) - f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name).c_str()); + f << stringf("[%d:%d] %s", wire->start_offset, wire->width - 1 + wire->start_offset, RTLIL::unescape_id(wire->name)); else - f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name).c_str()); + f << stringf("[%d:%d] %s", wire->width - 1 + wire->start_offset, wire->start_offset, RTLIL::unescape_id(wire->name)); return f.str(); } @@ -2108,7 +2108,7 @@ struct SimWorker : SimShared { std::stringstream f; for(auto item=signals.begin();item!=signals.end();item++) - f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str()); + f << stringf("%c%s", (item==signals.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name)); return f.str(); } @@ -2207,7 +2207,7 @@ struct SimWorker : SimShared std::stringstream f; f << stringf("`timescale 1%s/1%s\n", fst->getTimescaleString(),fst->getTimescaleString()); - f << stringf("module %s();\n",tb_filename.c_str()); + f << stringf("module %s();\n",tb_filename); int clk_len = 0; int inputs_len = 0; int outputs_len = 0; @@ -2225,13 +2225,13 @@ struct SimWorker : SimShared } int data_len = clk_len + inputs_len + outputs_len + 32; f << "\n"; - f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name).c_str()); + f << stringf("\t%s uut(",RTLIL::unescape_id(topmod->name)); for(auto item=clocks.begin();item!=clocks.end();item++) - f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name).c_str(), RTLIL::unescape_id(item->first->name).c_str()); + f << stringf("%c.%s(%s)", (item==clocks.begin() ? ' ' : ','), RTLIL::unescape_id(item->first->name), RTLIL::unescape_id(item->first->name)); for(auto &item : inputs) - f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str()); + f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name)); for(auto &item : outputs) - f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name).c_str(), RTLIL::unescape_id(item.first->name).c_str()); + f << stringf(",.%s(%s)", RTLIL::unescape_id(item.first->name), RTLIL::unescape_id(item.first->name)); f << ");\n"; f << "\n"; f << "\tinteger i;\n"; @@ -2242,21 +2242,21 @@ struct SimWorker : SimShared unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX; fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, end_cycle, [&](uint64_t time) { for(auto &item : clocks) - data_file << stringf("%s",fst->valueOf(item.second).c_str()); + data_file << stringf("%s",fst->valueOf(item.second)); for(auto &item : inputs) - data_file << stringf("%s",fst->valueOf(item.second).c_str()); + data_file << stringf("%s",fst->valueOf(item.second)); for(auto &item : outputs) - data_file << stringf("%s",fst->valueOf(item.second).c_str()); - data_file << stringf("%s\n",Const(time-prev_time).as_string().c_str()); + data_file << stringf("%s",fst->valueOf(item.second)); + data_file << stringf("%s\n",Const(time-prev_time).as_string()); if (time==startCount) { // initial state for(auto var : fst->getVars()) { if (var.is_reg && !Const::from_string(fst->valueOf(var.id).c_str()).is_fully_undef()) { if (var.scope == scope) { - initstate << stringf("\t\tuut.%s = %d'b%s;\n", var.name.c_str(), var.width, fst->valueOf(var.id).c_str()); + initstate << stringf("\t\tuut.%s = %d'b%s;\n", var.name, var.width, fst->valueOf(var.id)); } else if (var.scope.find(scope+".")==0) { - initstate << stringf("\t\tuut.%s.%s = %d'b%s;\n",var.scope.substr(scope.size()+1).c_str(), var.name.c_str(), var.width, fst->valueOf(var.id).c_str()); + initstate << stringf("\t\tuut.%s.%s = %d'b%s;\n",var.scope.substr(scope.size()+1), var.name, var.width, fst->valueOf(var.id)); } } } @@ -2267,22 +2267,22 @@ struct SimWorker : SimShared f << stringf("\treg [0:%d] data [0:%d];\n", data_len-1, cycle-1); f << "\tinitial begin;\n"; - f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename.c_str()); - f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename.c_str()); + f << stringf("\t\t$dumpfile(\"%s\");\n",tb_filename); + f << stringf("\t\t$dumpvars(0,%s);\n",tb_filename); f << initstate.str(); - f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename.c_str()); + f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename); f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1); - f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1); + f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle); f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks).c_str(), 0, clk_len-1); - f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs).c_str(), clk_len, clk_len+inputs_len-1); + f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); - f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs).c_str(), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1); + f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1); f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n"; f << "\t\t\tend\n"; @@ -2337,7 +2337,7 @@ struct VCDWriter : public OutputWriter } if (!worker->timescale.empty()) - vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str()); + vcdfile << stringf("$timescale %s $end\n", worker->timescale); worker->top->write_output_header( [this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); }, @@ -2349,7 +2349,7 @@ struct VCDWriter : public OutputWriter // this is consistent with the range gtkwave makes up if it doesn't find a // range std::string full_name = form_vcd_name(name, size, w); - vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", full_name.c_str()); + vcdfile << stringf("$var %s %d n%d %s%s $end\n", is_reg ? "reg" : "wire", size, id, name[0] == '$' ? "\\" : "", full_name); } ); diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 9aaac84e9..d45a652fc 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -859,27 +859,27 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str()); + std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; for (std::string dont_use_cell : config.dont_use_cells) { - dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); + dont_use_args += stringf("-X \"%s\" ", dont_use_cell); } bool first_lib = true; for (std::string liberty_file : config.liberty_files) { - abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args.c_str(), first_lib ? "" : "-m", liberty_file.c_str()); + abc_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args, first_lib ? "" : "-m", liberty_file); first_lib = false; } for (std::string liberty_file : config.genlib_files) - abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); + abc_script += stringf("read_library \"%s\"; ", liberty_file); if (!config.constr_file.empty()) - abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file.c_str()); + abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file); } else if (!config.lut_costs.empty()) - abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); + abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name); else - abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); + abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name); if (!config.script_file.empty()) { const std::string &script_file = config.script_file; @@ -892,7 +892,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab else abc_script += script_file[i]; } else - abc_script += stringf("source %s", script_file.c_str()); + abc_script += stringf("source %s", script_file); } else if (!config.lut_costs.empty()) { bool all_luts_cost_same = true; for (int this_cost : config.lut_costs) @@ -925,15 +925,15 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3); if (config.abc_dress) - abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name.c_str()); - abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str()); + abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name); + abc_script += stringf("; write_blif %s/output.blif", tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); for (size_t i = 0; i+1 < abc_script.size(); i++) if (abc_script[i] == ';' && abc_script[i+1] == ' ') abc_script[i+1] = '\n'; - std::string buffer = stringf("%s/abc.script", tempdir_name.c_str()); + std::string buffer = stringf("%s/abc.script", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); @@ -988,7 +988,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab handle_loops(assign_map, module); - buffer = stringf("%s/input.blif", tempdir_name.c_str()); + buffer = stringf("%s/input.blif", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); @@ -1115,7 +1115,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost(); - buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str()); + buffer = stringf("%s/stdcells.genlib", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); @@ -1160,7 +1160,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab fclose(f); if (!config.lut_costs.empty()) { - buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str()); + buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); @@ -1169,14 +1169,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab fclose(f); } - buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str()); + buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str()); #ifndef YOSYS_LINK_ABC abc_output_filter filt(*this, tempdir_name, config.show_tempdir); int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); #else - string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str()); + string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name); FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); if (temp_stdouterr_w == NULL) log_error("ABC: cannot open a temporary file for output redirection"); @@ -1196,7 +1196,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab fclose(temp_stdouterr_w); // These needs to be mutable, supposedly due to getopt char *abc_argv[5]; - string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); + string tmp_script_name = stringf("%s/abc.script", tempdir_name); abc_argv[0] = strdup(config.exe_file.c_str()); abc_argv[1] = strdup("-s"); abc_argv[2] = strdup("-f"); @@ -1235,7 +1235,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL return; } - std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif"); + std::string buffer = stringf("%s/%s", tempdir_name, "output.blif"); std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) @@ -2102,7 +2102,7 @@ struct AbcPass : public Pass { goto ok_alias; } if (g_arg_from_cmd) - cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str())); + cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g)); else log_cmd_error("Unsupported gate type: %s", g.c_str()); ok_gate: diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index fe5cc7af1..b79d9dc96 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -332,8 +332,8 @@ struct Abc9Pass : public ScriptPass // Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs for (auto module : active_design->selected_modules()) { active_design->selected_active_module = module->name.str(); - if (module->cell(stringf("%s_$abc9_flop", module->name.c_str()))) - run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str())); + if (module->cell(stringf("%s_$abc9_flop", module->name))) + run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name)); } active_design->selected_active_module.clear(); } @@ -418,10 +418,10 @@ struct Abc9Pass : public ScriptPass tempdir_name = make_temp_dir(tempdir_name); if (!lut_mode) - run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str())); + run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name)); if (box_file.empty()) - run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str())); - run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name.c_str(), dff_mode ? "-dff" : "", tempdir_name.c_str())); + run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name)); + run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name, dff_mode ? "-dff" : "", tempdir_name)); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); @@ -433,15 +433,15 @@ struct Abc9Pass : public ScriptPass num_outputs); if (num_outputs) { std::string abc9_exe_cmd; - abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str()); + abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str(), tempdir_name); if (!lut_mode) - abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str()); + abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name); if (box_file.empty()) - abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str()); + abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name); else - abc9_exe_cmd += stringf(" -box %s", box_file.c_str()); + abc9_exe_cmd += stringf(" -box %s", box_file); run_nocheck(abc9_exe_cmd); - run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str())); + run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name, tempdir_name)); run_nocheck(stringf("abc9_ops -reintegrate %s", dff_mode ? "-dff" : "")); } else diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index dcc507fca..34348fd00 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -173,28 +173,28 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe std::string abc9_script; if (!lut_costs.empty()) - abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); + abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name); else if (!lut_file.empty()) - abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str()); + abc9_script += stringf("read_lut \"%s\"; ", lut_file); else if (!liberty_files.empty()) { std::string dont_use_args; for (std::string dont_use_cell : dont_use_cells) { - dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); + dont_use_args += stringf("-X \"%s\" ", dont_use_cell); } for (std::string liberty_file : liberty_files) { - abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); + abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args, liberty_file); } if (!constr_file.empty()) - abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str()); + abc9_script += stringf("read_constr -v \"%s\"; ", constr_file); } else if (!genlib_files.empty()) { for (std::string genlib_file : genlib_files) { - abc9_script += stringf("read_genlib \"%s\"; ", genlib_file.c_str()); + abc9_script += stringf("read_genlib \"%s\"; ", genlib_file); } } log_assert(!box_file.empty()); - abc9_script += stringf("read_box \"%s\"; ", box_file.c_str()); - abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); + abc9_script += stringf("read_box \"%s\"; ", box_file); + abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name); if (!script_file.empty()) { if (script_file[0] == '+') { @@ -206,7 +206,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe else abc9_script += script_file[i]; } else - abc9_script += stringf("source %s", script_file.c_str()); + abc9_script += stringf("source %s", script_file); } else if (!lut_costs.empty() || !lut_file.empty()) { abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos) : RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos); @@ -238,14 +238,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos)) abc9_script = abc9_script.erase(pos, strlen("&mfs")); else { - auto s = stringf("&write -n %s/output.aig; ", tempdir_name.c_str()); + auto s = stringf("&write -n %s/output.aig; ", tempdir_name); for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos)) { abc9_script = abc9_script.insert(pos, s); pos += GetSize(s) + strlen("&mfs"); } } - abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name.c_str()); + abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name); if (design->scratchpad_get_bool("abc9.verify")) { if (dff_mode) abc9_script += "; &verify -s"; @@ -268,7 +268,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe log_header(design, "Executing ABC9.\n"); if (!lut_costs.empty()) { - buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str()); + buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == NULL) log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); @@ -277,14 +277,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe fclose(f); } - buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str()); + buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); #ifndef YOSYS_LINK_ABC abc9_output_filter filt(tempdir_name, show_tempdir); int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1)); #else - string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str()); + string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name); FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); if (temp_stdouterr_w == NULL) log_error("ABC: cannot open a temporary file for output redirection"); @@ -304,7 +304,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe fclose(temp_stdouterr_w); // These needs to be mutable, supposedly due to getopt char *abc9_argv[5]; - string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); + string tmp_script_name = stringf("%s/abc.script", tempdir_name); abc9_argv[0] = strdup(exe_file.c_str()); abc9_argv[1] = strdup("-s"); abc9_argv[2] = strdup("-f"); @@ -328,7 +328,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe temp_stdouterr_r.close(); #endif if (ret != 0) { - if (check_file_exists(stringf("%s/output.aig", tempdir_name.c_str()))) + if (check_file_exists(stringf("%s/output.aig", tempdir_name))) log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); else log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index ee0a903c2..85a1099ed 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -856,7 +856,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) } } else if (w->port_output) - conn = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), log_id(port_name)), GetSize(w)); + conn = holes_module->addWire(stringf("%s.%s", cell->type, log_id(port_name)), GetSize(w)); } } else // box_module is a blackbox @@ -868,7 +868,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) log_assert(w); if (!w->port_output) continue; - Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w)); + Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name, log_id(port_name)), GetSize(w)); holes_wire->port_output = true; holes_wire->port_id = port_id++; holes_module->ports.push_back(holes_wire->name); @@ -1143,7 +1143,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) map_autoidx = autoidx++; - RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str())); + RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name)); if (mapped_mod == NULL) log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module)); @@ -1271,16 +1271,16 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) - driver_name = stringf("$lut%s", a_bit.wire->name.c_str()); + driver_name = stringf("$lut%s", a_bit.wire->name); else - driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset); + driver_name = stringf("$lut%s[%d]", a_bit.wire->name, a_bit.offset); driver_lut = mapped_mod->cell(driver_name); } if (!driver_lut) { // If a driver couldn't be found (could be from PI or box CI) // then implement using a LUT - RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())), + RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name)), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 00bd23f86..286ab4d5b 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -168,9 +168,9 @@ struct AbcNewPass : public ScriptPass { mod->get_string_attribute(ID(abc9_script))); } - run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str())); - run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str())); - run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str())); + run(stringf(" abc9_ops -write_box %s/input.box", tmpdir)); + run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir)); + run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir)); run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index a692b99fe..11ff71b29 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -201,7 +201,7 @@ struct BoothPassWorker { log_assert(sig_a.size() == sig_y.size()); for (int i = 0; i < sig_a.size(); i++) - mod->addFa(stringf("%s[%d]", name.c_str(), i), sig_a[i], sig_b[i], + mod->addFa(stringf("%s[%d]", name, i), sig_a[i], sig_b[i], sig_c[i], sig_x[i], sig_y[i], src); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 409ac7865..a2b9c3bff 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -553,7 +553,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) new_cell->setPort("\\" + port.first, sig); } - stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++; + stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type, new_cell->type)]++; } for (auto &stat: stats) @@ -687,7 +687,7 @@ struct DfflibmapPass : public Pass { if (!map_only_mode) { std::string dfflegalize_cmd = "dfflegalize"; for (auto it : cell_mappings) - dfflegalize_cmd += stringf(" -cell %s 01", it.first.c_str()); + dfflegalize_cmd += stringf(" -cell %s 01", it.first); dfflegalize_cmd += " t:$_DFF* t:$_SDFF*"; if (info_mode) { log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str()); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 137d22170..ea6ba5ddb 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -292,7 +292,7 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit: SigSet> sig2port; // create new cell - RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name); + RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name, autoidx++), needle->name); // create cell ports for (auto wire : needle->wires()) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 95c733f62..dd82958fa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -42,9 +42,9 @@ PRIVATE_NAMESPACE_BEGIN void apply_prefix(IdString prefix, IdString &id) { if (id[0] == '\\') - id = stringf("%s.%s", prefix.c_str(), id.c_str()+1); + id = stringf("%s.%s", prefix, id.c_str()+1); else - id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str()); + id = stringf("$techmap%s.%s", prefix, id); } void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module) @@ -107,7 +107,7 @@ struct TechmapWorker } } - return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); + return stringf("$paramod$constmap:%s%s", sha1(constmap_info), tpl->name); } TechmapWires techmap_find_special_wires(RTLIL::Module *module) @@ -222,7 +222,7 @@ struct TechmapWorker design->select(module, w); if (const char *p = strstr(tpl_w->name.c_str(), "_TECHMAP_REPLACE_.")) { - IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_")); + IdString replace_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_")); Wire *replace_w = module->addWire(replace_name, tpl_w); module->connect(replace_w, w); } @@ -327,7 +327,7 @@ struct TechmapWorker if (techmap_replace_cell) c_name = orig_cell_name; else if (const char *p = strstr(tpl_cell->name.c_str(), "_TECHMAP_REPLACE_.")) - c_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_")); + c_name = stringf("%s%s", orig_cell_name, p + strlen("_TECHMAP_REPLACE_")); else apply_prefix(cell->name, c_name); @@ -512,7 +512,7 @@ struct TechmapWorker if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { - std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); + std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type)); for (auto &c : cell->parameters) m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); @@ -586,7 +586,7 @@ struct TechmapWorker } else { - auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); log("%s\n", msg.c_str()); diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 306e760ee..bcaf097a1 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -114,7 +114,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s if (wire->port_output) { count_ports++; signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; - f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); + f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str())); } else if (wire->port_input) { count_ports++; bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock); @@ -134,73 +134,73 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s if (wire->attributes.count(ID::gentb_constant) != 0) signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string(); } - f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); + f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str())); } } - f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str()); + f << stringf("%s %s(\n", id(mod->name.str()), idy("uut", mod->name.str())); for (auto wire : mod->wires()) { if (wire->port_output || wire->port_input) - f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(), + f << stringf("\t.%s(%s)%s\n", id(wire->name.str()), idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); } f << stringf(");\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "reset")); f << stringf("begin\n"); int delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); ++it) - f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2); for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) - f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2); f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100); for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) { - f << stringf("\t#100; %s <= 1;\n", it->first.c_str()); - f << stringf("\t#100; %s <= 0;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 1;\n", it->first); + f << stringf("\t#100; %s <= 0;\n", it->first); } delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); ++it) - f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d ~0;\n", it->first, ++delay_counter*2); f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100); for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) { - f << stringf("\t#100; %s <= 1;\n", it->first.c_str()); - f << stringf("\t#100; %s <= 0;\n", it->first.c_str()); + f << stringf("\t#100; %s <= 1;\n", it->first); + f << stringf("\t#100; %s <= 0;\n", it->first); } delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); ++it) { if (signal_const.count(it->first) == 0) continue; - f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str()); + f << stringf("\t%s <= #%d 'b%s;\n", it->first, ++delay_counter*2, signal_const[it->first]); } f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100); f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "update_data")); f << stringf("begin\n"); delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { if (signal_const.count(it->first) > 0) continue; f << stringf("\txorshift128;\n"); - f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2); + f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first, ++delay_counter*2); } f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100); f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "update_clock")); f << stringf("begin\n"); if (signal_clk.size()) { f << stringf("\txorshift128;\n"); f << stringf("\t{"); int total_clock_bits = 0; for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first); total_clock_bits += it->second; } f << stringf(" } = {"); for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) - f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first); f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1); } f << stringf("end\n"); @@ -210,12 +210,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s std::vector header1; std::string header2 = ""; - f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "print_status")); f << stringf("begin\n"); f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {"); if (signal_in.size()) for (auto it = signal_in.begin(); it != signal_in.end(); it++) { - f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first); int len = it->second; header2 += ", \""; if (len > 1) @@ -237,7 +237,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s header2 += ", \" \""; if (signal_clk.size()) { for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) { - f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first); int len = it->second; header2 += ", \""; if (len > 1) @@ -259,7 +259,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s header2 += ", \" \""; if (signal_out.size()) { for (auto it = signal_out.begin(); it != signal_out.end(); it++) { - f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str()); + f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first); int len = it->second; header2 += ", \""; if (len > 1) @@ -281,25 +281,25 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "print_header")); f << stringf("begin\n"); f << stringf("\t$fdisplay(file, \"#OUT#\");\n"); for (auto &hdr : header1) - f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr.c_str()); + f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr); f << stringf("\t$fdisplay(file, \"#OUT#\");\n"); - f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2.c_str()); + f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2); f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str()); + f << stringf("task %s;\n", idy(mod->name.str(), "test")); f << stringf("begin\n"); - f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str()); - f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str()); + f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str())); + f << stringf("\t%s;\n", idy(mod->name.str(), "reset")); f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); - f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str()); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str()); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str()); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str()); + f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header")); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data")); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock")); + f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status")); f << stringf("\tend\n"); f << stringf("end\n"); f << stringf("endtask\n\n"); @@ -317,7 +317,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("\tend\n"); for (auto module : design->modules()) if (!module->get_bool_attribute(ID::gentb_skip)) - f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str()); + f << stringf("\t%s;\n", idy(module->name.str(), "test")); f << stringf("\t$fclose(file);\n"); f << stringf("\t$finish;\n"); f << stringf("end\n\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 4285611f7..87e0a00f8 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -591,7 +591,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: if (vlog_file.is_open()) { - vlog_file << stringf("\nmodule %s;\n", uut_name.c_str()); + vlog_file << stringf("\nmodule %s;\n", uut_name); for (auto port : gold_mod->ports) { RTLIL::Wire *wire = gold_mod->wire(port); @@ -601,13 +601,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire)); } - vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str()); + vlog_file << stringf(" %s_expr uut_expr(", uut_name); for (int i = 0; i < GetSize(gold_mod->ports); i++) vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]), gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr"); vlog_file << stringf(");\n"); - vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str()); + vlog_file << stringf(" %s_expr uut_noexpr(", uut_name); for (int i = 0; i < GetSize(gold_mod->ports); i++) vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]), gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr"); @@ -615,7 +615,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: vlog_file << stringf(" task run;\n"); vlog_file << stringf(" begin\n"); - vlog_file << stringf(" $display(\"%s\");\n", uut_name.c_str()); + vlog_file << stringf(" $display(\"%s\");\n", uut_name); } for (int i = 0; i < 64; i++) @@ -662,7 +662,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: gate_ce.set(gate_wire, in_value); if (vlog_file.is_open() && GetSize(in_value) > 0) { - vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str()); + vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string()); if (!vlog_pattern_info.empty()) vlog_pattern_info += " "; vlog_pattern_info += stringf("%s=%s", log_id(gold_wire), log_signal(in_value)); @@ -716,8 +716,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: if (vlog_file.is_open()) { vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n", vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire)); - vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str()); - vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str()); + vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string()); + vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string()); } } @@ -1142,12 +1142,12 @@ struct TestCellPass : public Pass { else uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); if (!write_prefix.empty()) { - Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); + Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i)); } else if (edges) { Pass::call(design, "dump gold"); run_edges_test(design, verbose); } else { - Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd.c_str())); + Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd)); if (!noopt) Pass::call(design, "opt -fast gate"); if (!nosat) @@ -1157,11 +1157,11 @@ struct TestCellPass : public Pass { Pass::call(design, "dump gold"); if (!nosat) Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter"); - std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i); + std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1), i); if (vlog_file.is_open()) { - Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str())); + Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name, uut_name)); Backend::backend_call(design, &vlog_file, "", "verilog -selected"); - Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str())); + Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name, uut_name)); Backend::backend_call(design, &vlog_file, "", "verilog -selected -noexpr"); uut_names.push_back(uut_name); } @@ -1208,7 +1208,7 @@ struct TestCellPass : public Pass { if (vlog_file.is_open()) { vlog_file << "\nmodule testbench;\n"; for (auto &uut : uut_names) - vlog_file << stringf(" %s %s ();\n", uut.c_str(), uut.c_str()); + vlog_file << stringf(" %s %s ();\n", uut, uut); vlog_file << " initial begin\n"; for (auto &uut : uut_names) vlog_file << " " << uut << ".run;\n"; diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 2b969182e..1b48f426b 100644 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -123,7 +123,7 @@ struct SynthAchronixPass : public ScriptPass { if (check_label("begin")) { run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index c72e7f2a1..a03374fb0 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -150,7 +150,7 @@ struct SynthAnlogicPass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -233,13 +233,13 @@ struct SynthAnlogicPass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif %s", help_mode ? "" : edif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthAnlogicPass; diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index e9176304d..a98619abd 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -177,7 +177,7 @@ struct PrepPass : public ScriptPass else run("hierarchy -check"); } else - run(stringf("hierarchy -check -top %s", top_module.c_str())); + run(stringf("hierarchy -check -top %s", top_module)); } } diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 8b4561c34..9c85fbbc7 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -249,7 +249,7 @@ struct SynthPass : public ScriptPass { else run("hierarchy -check"); } else - run(stringf("hierarchy -check -top %s", top_module.c_str())); + run(stringf("hierarchy -check -top %s", top_module)); } } @@ -294,7 +294,7 @@ struct SynthPass : public ScriptPass { if (!techmap_maps.empty()) techmap_opts += " -map +/techmap.v"; for (auto fn : techmap_maps) - techmap_opts += stringf(" -map %s", fn.c_str()); + techmap_opts += stringf(" -map %s", fn); run("techmap" + techmap_opts); } if (help_mode) { @@ -316,7 +316,7 @@ struct SynthPass : public ScriptPass { run(abc + " -fast -lut k", "(unless -noabc, if -lut)"); } else { if (lut) - run(stringf("%s -fast -lut %d", abc.c_str(), lut)); + run(stringf("%s -fast -lut %d", abc, lut)); else run(abc + " -fast"); } diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index a746ac222..7ee1393be 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -126,7 +126,7 @@ struct SynthCoolrunner2Pass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib +/coolrunner2/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -198,7 +198,7 @@ struct SynthCoolrunner2Pass : public ScriptPass if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthCoolrunner2Pass; diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index 50526a9ea..6c5df7beb 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -129,14 +129,14 @@ struct SynthEasicPass : public ScriptPass void script() override { - string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str()); - string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str()); + string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path); + string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path); if (check_label("begin")) { - run(stringf("read_liberty -lib %s", help_mode ? "" : phys_clk_lib.c_str())); - run(stringf("read_liberty -lib %s", help_mode ? "" : logic_lut_lib.c_str())); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("read_liberty -lib %s", help_mode ? "" : phys_clk_lib)); + run(stringf("read_liberty -lib %s", help_mode ? "" : logic_lut_lib)); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -165,8 +165,8 @@ struct SynthEasicPass : public ScriptPass if (check_label("map")) { - run(stringf("dfflibmap -liberty %s", help_mode ? "" : phys_clk_lib.c_str())); - run(stringf("abc -liberty %s", help_mode ? "" : logic_lut_lib.c_str())); + run(stringf("dfflibmap -liberty %s", help_mode ? "" : phys_clk_lib)); + run(stringf("abc -liberty %s", help_mode ? "" : logic_lut_lib)); run("opt_clean"); } @@ -181,7 +181,7 @@ struct SynthEasicPass : public ScriptPass if (check_label("vlog")) { if (!vlog_file.empty() || help_mode) - run(stringf("write_verilog -noexpr -attr2comment %s", help_mode ? "" : vlog_file.c_str())); + run(stringf("write_verilog -noexpr -attr2comment %s", help_mode ? "" : vlog_file)); } } } SynthEasicPass; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 6e518f5d1..8960df70c 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -272,7 +272,7 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) @@ -383,9 +383,9 @@ struct SynthEcp5Pass : public ScriptPass abc9_opts += " -maxlut 4"; std::string k = "synth_ecp5.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); if (nowidelut) abc9_opts += " -maxlut 4"; if (dff) @@ -443,13 +443,13 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif %s", help_mode ? "" : edif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthEcp5Pass; diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 419bc2f88..ef245e755 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -142,7 +142,7 @@ struct SynthEfinixPass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib +/efinix/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -225,13 +225,13 @@ struct SynthEfinixPass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif %s", help_mode ? "" : edif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthEfinixPass; diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 8d2fb1471..0e6553fa1 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -278,7 +278,7 @@ struct SynthPass : public ScriptPass else run("hierarchy -check"); } else - run(stringf("hierarchy -check -top %s", top_module.c_str())); + run(stringf("hierarchy -check -top %s", top_module)); run("proc"); } @@ -365,7 +365,7 @@ struct SynthPass : public ScriptPass } else if (!extra_map.empty()) { std::string map_str = "techmap"; for (auto map : extra_map) - map_str += stringf(" -map %s", map.c_str()); + map_str += stringf(" -map %s", map); run(map_str); } run("clean"); @@ -399,7 +399,7 @@ struct SynthPass : public ScriptPass if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthPass; diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index fa36252f5..7726e7a15 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -203,7 +203,7 @@ struct SynthGateMatePass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("prepare")) @@ -351,14 +351,14 @@ struct SynthGateMatePass : public ScriptPass { run("opt_clean -purge"); if (!vlog_file.empty() || help_mode) { - run(stringf("write_verilog -noattr %s", help_mode ? "" : vlog_file.c_str())); + run(stringf("write_verilog -noattr %s", help_mode ? "" : vlog_file)); } } if (check_label("json")) { if (!json_file.empty() || help_mode) { - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 484b88b94..8f3553df6 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -219,8 +219,8 @@ struct SynthGowinPass : public ScriptPass if (check_label("begin")) { run("read_verilog -specify -lib +/gowin/cells_sim.v"); - run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "" : family.c_str())); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("read_verilog -specify -lib +/gowin/cells_xtra_%s.v", help_mode ? "" : family)); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index a9f7db679..99fe45dc4 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -138,7 +138,7 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib +/greenpak4/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -202,7 +202,7 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthGreenPAK4Pass; diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index 014490564..fe928ba6d 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -59,9 +59,9 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT))); for (const auto &a : st.carry->attributes) - cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second; + cell->attributes[stringf("\\SB_CARRY.%s", a.first)] = a.second; for (const auto &a : st.lut->attributes) - cell->attributes[stringf("\\SB_LUT4.%s", a.first.c_str())] = a.second; + cell->attributes[stringf("\\SB_LUT4.%s", a.first)] = a.second; cell->attributes[ID(SB_LUT4.name)] = Const(st.lut->name.str()); if (st.carry->get_bool_attribute(ID::keep) || st.lut->get_bool_attribute(ID::keep)) cell->attributes[ID::keep] = true; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 818323892..d433c0408 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -302,7 +302,7 @@ struct SynthIce40Pass : public ScriptPass if (check_label("begin")) { run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); run("proc"); } @@ -419,10 +419,10 @@ struct SynthIce40Pass : public ScriptPass std::string abc9_opts; std::string k = "synth_ice40.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else { - k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str()); - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + k = stringf("synth_ice40.abc9.%s.W", device_opt); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); } if (dff) abc9_opts += " -dff"; @@ -475,13 +475,13 @@ struct SynthIce40Pass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif %s", help_mode ? "" : edif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthIce40Pass; diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 11567ece9..af0717235 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -188,12 +188,12 @@ struct SynthIntelPass : public ScriptPass { { if (check_label("begin")) { if (check_label("family")) - run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str())); + run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt)); // Misc and common cells run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) { @@ -225,7 +225,7 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL9X9"); run("chtype -set $mul t:$__soft_mul"); run("alumacc"); - run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt.c_str())); + run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt)); } else { run("alumacc"); } @@ -274,7 +274,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (iopads || help_mode) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)"); - run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt)); run("clean -purge"); } @@ -294,7 +294,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("vpr")) { if (!blif_file.empty() || help_mode) { run(stringf("opt_clean -purge")); - run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str())); + run(stringf("write_blif %s", help_mode ? "" : blif_file)); } } } diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index cdae9586e..28852d7df 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -169,17 +169,17 @@ struct SynthIntelALMPass : public ScriptPass { if (check_label("begin")) { if (family_opt == "cyclonev") - run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str())); + run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/misc_sim.v", family_opt)); + run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt)); // Misc and common cells run("read_verilog -lib +/intel/common/altpll_bb.v"); run("read_verilog -lib +/intel_alm/common/megafunction_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) { @@ -225,8 +225,8 @@ struct SynthIntelALMPass : public ScriptPass { } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str())); - run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str())); + run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type)); + run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type)); } if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index 16a068b07..e1df20dd7 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -333,7 +333,7 @@ struct SynthLatticePass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) @@ -449,9 +449,9 @@ struct SynthLatticePass : public ScriptPass abc9_opts += " -maxlut 4"; std::string k = "synth_lattice.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); if (nowidelut) abc9_opts += " -maxlut 4"; if (dff) @@ -489,13 +489,13 @@ struct SynthLatticePass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif %s", help_mode ? "" : edif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthLatticePass; diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc index 727bf9ac6..77cedcd1f 100644 --- a/techlibs/microchip/synth_microchip.cc +++ b/techlibs/microchip/synth_microchip.cc @@ -262,7 +262,7 @@ struct SynthMicrochipPass : public ScriptPass { read_args += " -lib -specify +/microchip/cells_sim.v"; run("read_verilog" + read_args); - run(stringf("hierarchy -check %s", top_opt.c_str())); + run(stringf("hierarchy -check %s", top_opt)); } if (check_label("prepare")) { @@ -534,18 +534,18 @@ struct SynthMicrochipPass : public ScriptPass { if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif -pvector bra %s", edif_file.c_str())); + run(stringf("write_edif -pvector bra %s", edif_file)); } if (check_label("blif")) { if (!blif_file.empty() || help_mode) - run(stringf("write_blif %s", blif_file.c_str())); + run(stringf("write_blif %s", blif_file)); } if (check_label("vlog")) { if (!vlog_file.empty() || help_mode) - run(stringf("write_verilog %s", help_mode ? "" : vlog_file.c_str())); + run(stringf("write_verilog %s", help_mode ? "" : vlog_file)); } } } SynthMicrochipPass; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 4674559fb..a8f4a05d1 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -244,7 +244,7 @@ struct SynthNanoXplorePass : public ScriptPass run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); run("techmap -map +/nanoxplore/cells_wrap.v"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) @@ -335,9 +335,9 @@ struct SynthNanoXplorePass : public ScriptPass std::string abc9_opts = " -maxlut 4"; std::string k = "synth_nanoxplore.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); run("abc9" + abc9_opts); } else { std::string abc_args = " -dress"; @@ -362,7 +362,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthNanoXplorePass; diff --git a/techlibs/nexus/synth_nexus.cc b/techlibs/nexus/synth_nexus.cc index 2935fbd3b..83abd156a 100644 --- a/techlibs/nexus/synth_nexus.cc +++ b/techlibs/nexus/synth_nexus.cc @@ -254,7 +254,7 @@ struct SynthNexusPass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib -specify +/nexus/cells_sim.v +/nexus/cells_xtra.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("coarse")) @@ -361,9 +361,9 @@ struct SynthNexusPass : public ScriptPass abc9_opts += " -maxlut 4"; std::string k = "synth_nexus.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); if (nowidelut) abc9_opts += " -maxlut 4"; if (dff) @@ -405,13 +405,13 @@ struct SynthNexusPass : public ScriptPass if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } if (check_label("vm")) { if (!vm_file.empty() || help_mode) - run(stringf("write_verilog %s", help_mode ? "" : vm_file.c_str())); + run(stringf("write_verilog %s", help_mode ? "" : vm_file)); } } } SynthNexusPass; diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index c9b8eb289..84f9c48a7 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -198,16 +198,16 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("begin")) { - std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str()); + std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path, lib_path, family); if (family == "qlf_k6n10f") { - read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); + read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path); if (bramTypes) - read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path); if (dsp) - read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str()); + read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path); } run(read_simlibs); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (check_label("prepare")) { @@ -373,13 +373,13 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("blif", "(if -blif)")) { if (!blif_file.empty() || help_mode) { - run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str())); + run(stringf("write_blif -attr -param %s %s", top_opt, blif_file)); } } if (check_label("verilog", "(if -verilog)")) { if (!verilog_file.empty() || help_mode) { - run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); + run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file)); } } } diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index bf4a6e031..ad335536b 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -166,7 +166,7 @@ struct SynthSf2Pass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib +/sf2/cells_sim.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); } if (flatten && check_label("flatten", "(unless -noflatten)")) @@ -244,19 +244,19 @@ struct SynthSf2Pass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif -gndvccy %s", help_mode ? "" : edif_file.c_str())); + run(stringf("write_edif -gndvccy %s", help_mode ? "" : edif_file)); } if (check_label("vlog")) { if (!vlog_file.empty() || help_mode) - run(stringf("write_verilog %s", help_mode ? "" : vlog_file.c_str())); + run(stringf("write_verilog %s", help_mode ? "" : vlog_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthSf2Pass; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 505026fe8..4e422c5cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -350,7 +350,7 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -lib +/xilinx/cells_xtra.v"); - run(stringf("hierarchy -check %s", top_opt.c_str())); + run(stringf("hierarchy -check %s", top_opt)); } if (check_label("prepare")) { @@ -649,10 +649,10 @@ struct SynthXilinxPass : public ScriptPass std::string abc9_opts; std::string k = "synth_xilinx.abc9.W"; if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); else { - k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); + k = stringf("synth_xilinx.abc9.%s.W", family); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W"))); } if (nowidelut) abc9_opts += stringf(" -maxlut %d", lut_size); @@ -718,18 +718,18 @@ struct SynthXilinxPass : public ScriptPass if (check_label("edif")) { if (!edif_file.empty() || help_mode) - run(stringf("write_edif -pvector bra %s", edif_file.c_str())); + run(stringf("write_edif -pvector bra %s", edif_file)); } if (check_label("blif")) { if (!blif_file.empty() || help_mode) - run(stringf("write_blif %s", blif_file.c_str())); + run(stringf("write_blif %s", blif_file)); } if (check_label("json")) { if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + run(stringf("write_json %s", help_mode ? "" : json_file)); } } } SynthXilinxPass; From 41b6c0cb9fefb5dfab77930652c29939f9b89edd Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 1 Sep 2025 03:26:40 +0000 Subject: [PATCH 008/188] Make CellTypes methods take IdString by reference to avoid refcount churn --- kernel/celltypes.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 11640c25f..f08a695e9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -303,24 +303,24 @@ struct CellTypes cell_types.clear(); } - bool cell_known(RTLIL::IdString type) const + bool cell_known(const RTLIL::IdString &type) const { return cell_types.count(type) != 0; } - bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.outputs.count(port) != 0; } - bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const + bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.inputs.count(port) != 0; } - bool cell_evaluable(RTLIL::IdString type) const + bool cell_evaluable(const RTLIL::IdString &type) const { auto it = cell_types.find(type); return it != cell_types.end() && it->second.is_evaluable; From 54a258f8546bbc999fd7ab8a53aeecbdc436fb25 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 1 Sep 2025 03:36:03 +0000 Subject: [PATCH 009/188] In hash_cell_inputs, avoid constructing an std::pair (which requires copying the port IdString) --- kernel/hashlib.h | 6 ++++++ passes/opt/opt_merge.cc | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 9c53e6687..39530baea 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -188,6 +188,12 @@ template struct hash_ops> { return h; } HASH_TOP_LOOP_FST (const std::pair &a) HASH_TOP_LOOP_SND + [[nodiscard]] static inline Hasher hash(const P &p, const Q &q) { + Hasher h; + h = hash_ops

::hash_into(p, h); + h = hash_ops::hash_into(q, h); + return h; + } }; template struct hash_ops> { diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index ba8168e74..6c81ee241 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -107,7 +107,7 @@ struct OptMergeWorker for (const auto& [port, sig] : cell->connections()) { if (cell->output(port)) continue; - comm.eat(hash_ops>::hash({port, assign_map(sig)})); + comm.eat(hash_ops>::hash(port, assign_map(sig))); } h = comm.hash_into(h); if (RTLIL::builtin_ff_cell_types().count(cell->type)) From b2ccfb2d0e5486e851ccaf70c107add77c3f5914 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 2 Sep 2025 02:43:03 +0000 Subject: [PATCH 010/188] Make in() variadic operator take parameters by reference so we don't copy IdStrings Template argument deduction strips references. --- kernel/rtlil.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e0de79ea9..ea358d83b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -411,7 +411,7 @@ struct RTLIL::IdString // often one needs to check if a given IdString is part of a list (for example a list // of cell types). the following functions helps with that. template - bool in(Args... args) const { + bool in(const Args &... args) const { return (... || in(args)); } From ddf7ba5a34619eda291d9510f6da4f65bffbcf4f Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 2 Sep 2025 02:44:02 +0000 Subject: [PATCH 011/188] Make `ID()` macro return a reference to the underlying `IdString` instead of copying it Lambda return type deduction infers `IdString` here. --- kernel/yosys_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index bc92e7869..943aa4f05 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -285,7 +285,7 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std: // // sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' // -#define ID(_id) ([]() { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ +#define ID(_id) ([]() -> const RTLIL::IdString & { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })() namespace ID = RTLIL::ID; From 030e5ec43851569fc0e7991a6672cebdae295b48 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 2 Sep 2025 03:01:11 +0000 Subject: [PATCH 012/188] Make IdString hashing take a reference to the IdString instead of copying it --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ea358d83b..c81a0c00a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -430,10 +430,10 @@ namespace hashlib { static inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) { return a == b; } - [[nodiscard]] static inline Hasher hash(const RTLIL::IdString id) { + [[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) { return id.hash_top(); } - [[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString id, Hasher h) { + [[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) { return id.hash_into(h); } }; From ccf140f2efcf916a6e17ecb03dde1c758b75ec56 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 4 Sep 2025 14:47:45 +0200 Subject: [PATCH 013/188] hashlib: don't build an unused hash for expired value in do_insert --- kernel/hashlib.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 9c53e6687..bef54b500 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -509,12 +509,11 @@ class dict { return do_lookup_internal(key, hash); } - int do_insert(const K &key, Hasher::hash_t &hash) + int do_insert(const K &key, const Hasher::hash_t &hash) { if (hashtable.empty()) { entries.emplace_back(std::pair(key, T()), -1); do_rehash(); - hash = do_hash(key); } else { entries.emplace_back(std::pair(key, T()), hashtable[hash]); hashtable[hash] = entries.size() - 1; @@ -522,12 +521,11 @@ class dict { return entries.size() - 1; } - int do_insert(const std::pair &value, Hasher::hash_t &hash) + int do_insert(const std::pair &value, const Hasher::hash_t &hash) { if (hashtable.empty()) { entries.emplace_back(value, -1); do_rehash(); - hash = do_hash(value.first); } else { entries.emplace_back(value, hashtable[hash]); hashtable[hash] = entries.size() - 1; @@ -535,13 +533,11 @@ class dict { return entries.size() - 1; } - int do_insert(std::pair &&rvalue, Hasher::hash_t &hash) + int do_insert(std::pair &&rvalue, const Hasher::hash_t &hash) { if (hashtable.empty()) { - auto key = rvalue.first; entries.emplace_back(std::forward>(rvalue), -1); do_rehash(); - hash = do_hash(key); } else { entries.emplace_back(std::forward>(rvalue), hashtable[hash]); hashtable[hash] = entries.size() - 1; From 6276464ea7366762d68ed3392c8558d7f087388d Mon Sep 17 00:00:00 2001 From: Mike Inouye Date: Thu, 4 Sep 2025 10:52:37 -0700 Subject: [PATCH 014/188] Increase muxtree glob eval attempts to 10M. --- passes/opt/opt_muxtree.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 98803b935..809353f8c 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -64,7 +64,7 @@ struct OptMuxtreeWorker RTLIL::Module *module; SigMap assign_map; int removed_count; - int glob_evals_left = 100000; + int glob_evals_left = 10000000; struct bitinfo_t { // Is bit directly used by non-mux cells or ports? From ae8c4e2ea6ee8f6c2e68261c06eb7f33131732ee Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 30 Aug 2025 06:13:12 +0300 Subject: [PATCH 015/188] libparse/filterlib: mark LibertyParser::error() as weak When FILTERLIB is defined (attempts to compile libparse more or less standalone,) mark the `LibertyParser::error()` as weak so utilities using libparse as a library can override its behavior (the default behavior being exit(1)). As the code is quite performance-critical, I've elected to not modify it to raise an exception or have a callback or similar and simply allow for a link-time replacement. --- passes/techmap/libparse.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index c6f87b60b..b60e0b84b 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -676,12 +676,15 @@ void LibertyParser::error(const std::string &str) const #else +YS_ATTRIBUTE(weak) void LibertyParser::error() const { fprintf(stderr, "Syntax error in liberty file on line %d.\n", line); exit(1); } + +YS_ATTRIBUTE(weak) void LibertyParser::error(const std::string &str) const { std::stringstream ss; From f45255f5a234c46d84b2ac240dbeb86b10f299be Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 5 Aug 2025 12:23:11 +1200 Subject: [PATCH 016/188] tests: More autoname tests --- tests/various/autoname.ys | 176 +++++++++++++++++++++++++++++++++++++- 1 file changed, 172 insertions(+), 4 deletions(-) diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index f12fb7995..88d0837d9 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -1,10 +1,11 @@ +# prefer output name +design -reset read_rtlil < Date: Tue, 5 Aug 2025 12:24:05 +1200 Subject: [PATCH 017/188] autoname.cc: Avoid int overflow --- passes/cmds/autoname.cc | 67 ++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 737bd3e58..75e54f4b1 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -22,11 +22,24 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -int autoname_worker(Module *module, const dict& wire_score) +typedef struct name_proposal { + string name; + unsigned int score; + name_proposal() : name(""), score(-1) { } + name_proposal(string name, unsigned int score) : name(name), score(score) { } + bool operator<(const name_proposal &other) const { + if (score != other.score) + return score < other.score; + else + return name.length() < other.name.length(); + } +} name_proposal; + +int autoname_worker(Module *module, const dict& wire_score) { - dict> proposed_cell_names; - dict> proposed_wire_names; - int best_score = -1; + dict proposed_cell_names; + dict proposed_wire_names; + name_proposal best_name; for (auto cell : module->selected_cells()) { if (cell->name[0] == '$') { @@ -36,14 +49,14 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); - string new_name(bit.wire->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_cell_names[cell] = make_pair(score, new_name); + name_proposal proposed_name( + bit.wire->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_cell_names.count(cell) || proposed_name < proposed_cell_names.at(cell)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_cell_names[cell] = proposed_name; } } } @@ -54,32 +67,36 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) suffix = stringf("_%s", log_id(conn.first)); - string new_name(cell->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_wire_names[bit.wire] = make_pair(score, new_name); + name_proposal proposed_name( + cell->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_wire_names.count(bit.wire) || proposed_name < proposed_wire_names.at(bit.wire)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_wire_names[bit.wire] = proposed_name; } } } } } + // compare against double best score for following comparisons so we don't + // pre-empt a future iteration + best_name.score *= 2; + for (auto &it : proposed_cell_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } for (auto &it : proposed_wire_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } @@ -115,7 +132,7 @@ struct AutonamePass : public Pass { for (auto module : design->selected_modules()) { - dict wire_score; + dict wire_score; for (auto cell : module->selected_cells()) for (auto &conn : cell->connections()) for (auto bit : conn.second) From bc77b6213b1db0455ef443a5a044b5160a219145 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 9 Aug 2025 10:52:52 +1200 Subject: [PATCH 018/188] autoname: Fix selection arg --- passes/cmds/autoname.cc | 1 + tests/various/autoname.ys | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 75e54f4b1..d2ff568c3 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -127,6 +127,7 @@ struct AutonamePass : public Pass { // } break; } + extra_args(args, argidx, design); log_header(design, "Executing AUTONAME pass.\n"); diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index 88d0837d9..29ca81bbe 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -171,11 +171,14 @@ module \top end end EOT -# wires all named for being cell outputs +# wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 +logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 +debug autoname t:$or +logger -check-expected + # $name gets shortest name (otherwise bcd_$__unknown_B) logger -expect log "Rename cell .name in top to a_.__unknown_A" 1 -logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 # another output wire logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1 # $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) @@ -183,5 +186,5 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 # $c gets shortest name, since the cell driving it doesn't have known port # directions logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 -debug autoname t:$and +debug autoname logger -check-expected From baa61a146ffdbdb2971022a8cdabebdd1fedffcc Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 5 Sep 2025 00:23:12 +0000 Subject: [PATCH 019/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fb4fb5776..a72a35d32 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+0 +YOSYS_VER := 0.57+1 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From c30fd46ea32a132b2524acd98d5a45a97528d725 Mon Sep 17 00:00:00 2001 From: Xing Guo Date: Fri, 5 Sep 2025 11:10:25 +0800 Subject: [PATCH 020/188] Fix handling of cases that look like sva labels again. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit c8e0ac0 introduces a regression on handling case exprs that look like sva labels. After some debugging, we shouldn't push the identifier ast node to the ast_stack, otherwise, we will get the following assertion failure: ``` âžœ /tmp yosys -p 'read -sv a1.v' /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2025 Claire Xenia Wolf | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3) -- Running command `read -sv a1.v' -- 1. Executing Verilog-2005 frontend: a1.v Parsing SystemVerilog input from `a1.v' to AST representation. ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709. âžœ /tmp cat a1.v module test(input wire A); localparam TEST = 1; always_comb begin case (A) TEST: assert(1); endcase end endmodule ``` We encountered this issue before but with a different error message[^1], [^1]: https://github.com/YosysHQ/yosys/issues/862 --- frontends/verilog/verilog_parser.y | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 392d8921a..c77d0a7cf 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3023,7 +3023,8 @@ case_expr_list: SET_AST_NODE_LOC(node, @1, @1); } | TOK_SVA_LABEL { - AstNode* node = extra->pushChild(std::make_unique(@$, AST_IDENTIFIER)); + AstNode* node = extra->saveChild(std::make_unique(@$, AST_IDENTIFIER)); + node->str = *$1; SET_AST_NODE_LOC(node, @1, @1); } | expr { From 62120bda0661102ba60801a871ab5c9f336a8aa6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 5 Sep 2025 12:34:38 +0200 Subject: [PATCH 021/188] verilog: test cases that look like SVA labels #862 --- tests/verilog/sva-in-case-expr.ys | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 tests/verilog/sva-in-case-expr.ys diff --git a/tests/verilog/sva-in-case-expr.ys b/tests/verilog/sva-in-case-expr.ys new file mode 100644 index 000000000..e326e2bfb --- /dev/null +++ b/tests/verilog/sva-in-case-expr.ys @@ -0,0 +1,10 @@ +read_verilog -sv < Date: Sat, 6 Sep 2025 00:21:53 +0000 Subject: [PATCH 022/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a72a35d32..5b362a652 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+1 +YOSYS_VER := 0.57+7 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 8fb3f88842ed4dbb6471d830d9ca5e57987987b3 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Thu, 3 Oct 2024 16:34:19 +0200 Subject: [PATCH 023/188] tests: remove -seq 1 from sat with -tempinduct where possible * When used with -tempinduct mode, -seq causes assertions to be ignored in the first N steps. While this has uses for reset modelling, for these test cases it is unnecessary and could lead to failures slipping through uncaught --- tests/svtypes/typedef_initial_and_assign.ys | 2 +- tests/svtypes/typedef_struct_port.ys | 4 ++-- tests/various/const_arg_loop.ys | 2 +- tests/various/const_func.ys | 2 +- tests/various/countbits.ys | 2 +- tests/various/param_struct.ys | 2 +- tests/verilog/atom_type_signedness.ys | 2 +- tests/verilog/int_types.ys | 2 +- tests/verilog/mem_bounds.ys | 2 +- tests/verilog/param_no_default.ys | 2 +- tests/verilog/parameters_across_files.ys | 2 +- tests/verilog/typedef_across_files.ys | 2 +- tests/verilog/typedef_legacy_conflict.ys | 2 +- tests/verilog/unbased_unsized.ys | 2 +- tests/verilog/unbased_unsized_shift.ys | 2 +- 15 files changed, 16 insertions(+), 16 deletions(-) diff --git a/tests/svtypes/typedef_initial_and_assign.ys b/tests/svtypes/typedef_initial_and_assign.ys index e778a49bb..4563ca491 100644 --- a/tests/svtypes/typedef_initial_and_assign.ys +++ b/tests/svtypes/typedef_initial_and_assign.ys @@ -11,4 +11,4 @@ logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1 read_verilog -sv typedef_initial_and_assign.sv hierarchy; proc; opt; async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/svtypes/typedef_struct_port.ys b/tests/svtypes/typedef_struct_port.ys index dd0775b9f..6cd61064c 100644 --- a/tests/svtypes/typedef_struct_port.ys +++ b/tests/svtypes/typedef_struct_port.ys @@ -1,6 +1,6 @@ read_verilog -sv typedef_struct_port.sv hierarchy; proc; opt; async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all select -module test_parser -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys index 01bea7044..21554cc0a 100644 --- a/tests/various/const_arg_loop.ys +++ b/tests/various/const_arg_loop.ys @@ -4,4 +4,4 @@ proc opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys index d982c3a43..e721e0e81 100644 --- a/tests/various/const_func.ys +++ b/tests/various/const_func.ys @@ -5,4 +5,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/countbits.ys b/tests/various/countbits.ys index f2db9cfe1..2d972e2d8 100644 --- a/tests/various/countbits.ys +++ b/tests/various/countbits.ys @@ -5,4 +5,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys index bb26b61d5..96837aafc 100644 --- a/tests/various/param_struct.ys +++ b/tests/various/param_struct.ys @@ -48,4 +48,4 @@ endmodule EOF hierarchy; proc; opt async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys index c8a82f993..77a0bd291 100644 --- a/tests/verilog/atom_type_signedness.ys +++ b/tests/verilog/atom_type_signedness.ys @@ -16,4 +16,4 @@ endmodule EOT hierarchy; proc; opt; async2sync select -module dut -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/int_types.ys b/tests/verilog/int_types.ys index 344f3ee09..70c99976c 100644 --- a/tests/verilog/int_types.ys +++ b/tests/verilog/int_types.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys index 146a6f433..2c973822a 100644 --- a/tests/verilog/mem_bounds.ys +++ b/tests/verilog/mem_bounds.ys @@ -4,4 +4,4 @@ flatten opt -full select -module top async2sync -sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef +sat -verify -tempinduct -prove-asserts -show-all -enable_undef diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys index 0509f6a1a..c609987e4 100644 --- a/tests/verilog/param_no_default.ys +++ b/tests/verilog/param_no_default.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/parameters_across_files.ys b/tests/verilog/parameters_across_files.ys index 94565eb67..3efe3e68c 100644 --- a/tests/verilog/parameters_across_files.ys +++ b/tests/verilog/parameters_across_files.ys @@ -18,4 +18,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys index baa4b7919..8cd578af4 100644 --- a/tests/verilog/typedef_across_files.ys +++ b/tests/verilog/typedef_across_files.ys @@ -21,4 +21,4 @@ proc opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys index dd1503a85..d26cc188f 100644 --- a/tests/verilog/typedef_legacy_conflict.ys +++ b/tests/verilog/typedef_legacy_conflict.ys @@ -35,4 +35,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys index 75d1bf5e4..3290650d5 100644 --- a/tests/verilog/unbased_unsized.ys +++ b/tests/verilog/unbased_unsized.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized_shift.ys b/tests/verilog/unbased_unsized_shift.ys index 2b5b9d8d0..6a72560b8 100644 --- a/tests/verilog/unbased_unsized_shift.ys +++ b/tests/verilog/unbased_unsized_shift.ys @@ -5,4 +5,4 @@ flatten opt -full async2sync select -module top -sat -verify -seq 1 -tempinduct -prove-asserts -show-all +sat -verify -tempinduct -prove-asserts -show-all From 23af52c3c8b7cd4898524cf3a9f84f61a8365aa2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 6 Sep 2025 00:28:52 +0000 Subject: [PATCH 024/188] Use well-known constants in ID macro and make the constant values known at compile time --- kernel/constids.inc | 289 ++++++++++++++++++++++-------------------- kernel/rtlil.cc | 27 +++- kernel/rtlil.h | 132 ++++++++++++++++--- kernel/yosys.cc | 4 - kernel/yosys_common.h | 14 +- 5 files changed, 294 insertions(+), 172 deletions(-) diff --git a/kernel/constids.inc b/kernel/constids.inc index 29872d45e..1419c89fa 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -1,27 +1,27 @@ +// These must be in perfect ASCII order!!! +X($_AND_) +X($_OR_) +X($_XOR_) +X($add) +X($and) +X($logic_and) +X($logic_or) +X($mul) +X($or) +X($pmux) +X($reduce_and) +X($reduce_bool) +X($reduce_or) +X($reduce_xnor) +X($reduce_xor) +X($xor) X(A) -X(abc9_box) -X(abc9_box_id) -X(abc9_box_seq) -X(abc9_bypass) -X(abc9_carry) -X(abc9_flop) -X(abc9_keep) -X(abc9_lut) -X(abc9_mergeability) -X(abc9_scc_id) -X(abcgroup) X(ABITS) X(AD) +X(ADDEND_NEGATED) X(ADDR) -X(allconst) -X(allseq) X(ALOAD) X(ALOAD_POLARITY) -X(always_comb) -X(always_ff) -X(always_latch) -X(anyconst) -X(anyseq) X(ARGS) X(ARGS_WIDTH) X(ARST) @@ -29,27 +29,21 @@ X(ARST_POLARITY) X(ARST_VALUE) X(A_SIGNED) X(A_WIDTH) +X(A_WIDTHS) X(B) X(BI) X(BITS_USED) -X(blackbox) -X(B_SIGNED) -X(bugpoint_keep) -X(B_WIDTH) X(BYTE) +X(B_SIGNED) +X(B_WIDTH) +X(B_WIDTHS) X(C) -X(cells_not_processed) X(CE_OVER_SRST) X(CFG_ABITS) X(CFG_DBITS) X(CFG_INIT) -X(chain) X(CI) X(CLK) -X(clkbuf_driver) -X(clkbuf_inhibit) -X(clkbuf_inv) -X(clkbuf_sink) X(CLK_ENABLE) X(CLK_POLARITY) X(CLR) @@ -62,12 +56,13 @@ X(CTRL_IN) X(CTRL_IN_WIDTH) X(CTRL_OUT) X(CTRL_OUT_WIDTH) +X(C_SIGNED) +X(C_WIDTHS) X(D) X(DAT) X(DATA) X(DAT_DST_PEN) X(DAT_DST_POL) -X(defaultvalue) X(DELAY) X(DEPTH) X(DST) @@ -75,7 +70,6 @@ X(DST_EN) X(DST_PEN) X(DST_POL) X(DST_WIDTH) -X(dynports) X(E) X(EDGE_EN) X(EDGE_POL) @@ -83,82 +77,34 @@ X(EN) X(EN_DST) X(EN_POLARITY) X(EN_SRC) -X(enum_base_type) -X(enum_type) -X(equiv_merged) -X(equiv_region) -X(extract_order) X(F) X(FLAVOR) X(FORMAT) -X(force_downto) -X(force_upto) -X(fsm_encoding) -X(fsm_export) X(FULL) -X(full_case) X(G) -X(gclk) -X(gentb_clock) -X(gentb_constant) -X(gentb_skip) X(H) -X(hdlname) -X(hierconn) X(I) X(INIT) X(INIT_VALUE) -X(init) -X(initial_top) -X(interface_modport) -X(interfaces_replaced_in_module) -X(interface_type) -X(invertible_pin) -X(iopad_external_pin) -X(is_interface) X(J) X(K) -X(keep) -X(keep_hierarchy) X(L) -X(lib_whitebox) -X(localparam) -X(logic_block) -X(lram) X(LUT) -X(lut_keep) X(M) -X(maximize) -X(mem2reg) X(MEMID) -X(minimize) -X(module_not_derived) X(N) +X(NADDENDS) X(NAME) -X(noblackbox) -X(nolatches) -X(nomem2init) -X(nomem2reg) -X(nomeminit) -X(nosync) -X(nowrshmsk) -X(no_ram) -X(no_rw_check) +X(NPRODUCTS) X(O) X(OFFSET) -X(onehot) X(P) -X(parallel_case) -X(parameter) X(PORTID) X(PRIORITY) X(PRIORITY_MASK) -X(promoted_if) +X(PRODUCT_NEGATED) X(Q) X(R) -X(ram_block) -X(ram_style) -X(ramstyle) X(RD_ADDR) X(RD_ARST) X(RD_ARST_VALUE) @@ -176,19 +122,11 @@ X(RD_SRST_VALUE) X(RD_TRANSPARENCY_MASK) X(RD_TRANSPARENT) X(RD_WIDE_CONTINUATION) -X(reg) -X(replaced_by_gclk) -X(reprocess_after) -X(rom_block) -X(rom_style) -X(romstyle) X(S) X(SET) X(SET_POLARITY) -X(single_bit_vector) X(SIZE) X(SRC) -X(src) X(SRC_DST_PEN) X(SRC_DST_POL) X(SRC_EN) @@ -198,34 +136,24 @@ X(SRC_WIDTH) X(SRST) X(SRST_POLARITY) X(SRST_VALUE) -X(sta_arrival) X(STATE_BITS) X(STATE_NUM) X(STATE_NUM_LOG2) X(STATE_RST) X(STATE_TABLE) -X(smtlib2_module) -X(smtlib2_comb_expr) -X(submod) -X(syn_ramstyle) -X(syn_romstyle) X(S_WIDTH) X(T) X(TABLE) X(TAG) -X(techmap_autopurge) -X(_TECHMAP_BITS_CONNMAP_) -X(_TECHMAP_CELLNAME_) -X(_TECHMAP_CELLTYPE_) -X(techmap_celltype) -X(_TECHMAP_FAIL_) -X(techmap_maccmap) -X(_TECHMAP_REPLACE_) -X(techmap_simplemap) -X(_techmap_special_) -X(techmap_wrap) -X(_TECHMAP_PLACEHOLDER_) -X(techmap_chtype) +X(TRANSPARENCY_MASK) +X(TRANSPARENT) +X(TRANS_NUM) +X(TRANS_TABLE) +X(TRG) +X(TRG_ENABLE) +X(TRG_POLARITY) +X(TRG_WIDTH) +X(TYPE) X(T_FALL_MAX) X(T_FALL_MIN) X(T_FALL_TYP) @@ -237,31 +165,12 @@ X(T_LIMIT2_TYP) X(T_LIMIT_MAX) X(T_LIMIT_MIN) X(T_LIMIT_TYP) -X(to_delete) -X(top) -X(TRANS_NUM) -X(TRANSPARENCY_MASK) -X(TRANSPARENT) -X(TRANS_TABLE) -X(TRG) -X(TRG_ENABLE) -X(TRG_POLARITY) -X(TRG_WIDTH) X(T_RISE_MAX) X(T_RISE_MIN) X(T_RISE_TYP) -X(TYPE) X(U) -X(unique) -X(unused_bits) X(V) -X(via_celltype) -X(wand) -X(whitebox) X(WIDTH) -X(wildcard_port_conns) -X(wiretype) -X(wor) X(WORDS) X(WR_ADDR) X(WR_CLK) @@ -273,17 +182,125 @@ X(WR_PORTS) X(WR_PRIORITY_MASK) X(WR_WIDE_CONTINUATION) X(X) -X(xprop_decoder) X(Y) X(Y_WIDTH) +X(_TECHMAP_BITS_CONNMAP_) +X(_TECHMAP_CELLNAME_) +X(_TECHMAP_CELLTYPE_) +X(_TECHMAP_FAIL_) +X(_TECHMAP_PLACEHOLDER_) +X(_TECHMAP_REPLACE_) +X(_techmap_special_) +X(abc9_box) +X(abc9_box_id) +X(abc9_box_seq) +X(abc9_bypass) +X(abc9_carry) +X(abc9_flop) +X(abc9_keep) +X(abc9_lut) +X(abc9_mergeability) +X(abc9_scc_id) +X(abcgroup) +X(allconst) +X(allseq) +X(always_comb) +X(always_ff) +X(always_latch) +X(anyconst) +X(anyseq) X(area) +X(blackbox) +X(bugpoint_keep) X(capacitance) -X(NPRODUCTS) -X(NADDENDS) -X(PRODUCT_NEGATED) -X(ADDEND_NEGATED) -X(A_WIDTHS) -X(B_WIDTHS) -X(C_WIDTHS) -X(C_SIGNED) +X(cells_not_processed) +X(chain) +X(clkbuf_driver) +X(clkbuf_inhibit) +X(clkbuf_inv) +X(clkbuf_sink) +X(defaultvalue) +X(dynports) +X(enum_base_type) +X(enum_type) +X(equiv_merged) +X(equiv_region) +X(extract_order) +X(force_downto) +X(force_upto) +X(fsm_encoding) +X(fsm_export) +X(full_case) +X(gclk) +X(gentb_clock) +X(gentb_constant) +X(gentb_skip) +X(hdlname) +X(hierconn) +X(init) +X(initial_top) +X(interface_modport) +X(interface_type) +X(interfaces_replaced_in_module) +X(invertible_pin) +X(iopad_external_pin) +X(is_interface) +X(keep) +X(keep_hierarchy) +X(lib_whitebox) +X(localparam) +X(logic_block) +X(lram) +X(lut_keep) +X(maximize) +X(mem2reg) +X(minimize) +X(module_not_derived) +X(no_ram) +X(no_rw_check) +X(noblackbox) +X(nolatches) +X(nomem2init) +X(nomem2reg) +X(nomeminit) +X(nosync) +X(nowrshmsk) +X(onehot) +X(parallel_case) +X(parameter) +X(promoted_if) X(raise_error) +X(ram_block) +X(ram_style) +X(ramstyle) +X(reg) +X(replaced_by_gclk) +X(reprocess_after) +X(rom_block) +X(rom_style) +X(romstyle) +X(single_bit_vector) +X(smtlib2_comb_expr) +X(smtlib2_module) +X(src) +X(sta_arrival) +X(submod) +X(syn_ramstyle) +X(syn_romstyle) +X(techmap_autopurge) +X(techmap_celltype) +X(techmap_chtype) +X(techmap_maccmap) +X(techmap_simplemap) +X(techmap_wrap) +X(to_delete) +X(top) +X(unique) +X(unused_bits) +X(via_celltype) +X(wand) +X(whitebox) +X(wildcard_port_conns) +X(wiretype) +X(wor) +X(xprop_decoder) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 13f6b1075..9c7e3888c 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -29,6 +29,7 @@ #include #include #include +#include YOSYS_NAMESPACE_BEGIN @@ -37,7 +38,7 @@ RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard; std::vector RTLIL::IdString::global_id_storage_; std::unordered_map RTLIL::IdString::global_id_index_; #ifndef YOSYS_NO_IDS_REFCNT -std::vector RTLIL::IdString::global_refcount_storage_; +std::vector RTLIL::IdString::global_refcount_storage_; std::vector RTLIL::IdString::global_free_idx_list_; #endif #ifdef YOSYS_USE_STICKY_IDS @@ -45,10 +46,32 @@ int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; #endif -#define X(_id) IdString RTLIL::ID::_id; +#define X(N) const RTLIL::IdString RTLIL::ID::N(RTLIL::StaticId::N); #include "kernel/constids.inc" #undef X +static void populate(std::string_view name) +{ + if (name[1] == '$') { + // Skip prepended '\' + name = name.substr(1); + } + RTLIL::IdString::global_id_index_.insert({name, GetSize(RTLIL::IdString::global_id_storage_)}); + RTLIL::IdString::global_id_storage_.push_back(const_cast(name.data())); +} + +void RTLIL::IdString::prepopulate() +{ + int size = static_cast(RTLIL::StaticId::STATIC_ID_END); + global_id_storage_.reserve(size); + RTLIL::IdString::global_id_storage_.push_back(const_cast("")); + global_id_index_.reserve(size); + global_refcount_storage_.resize(size, 1); +#define X(N) populate("\\" #N); +#include "kernel/constids.inc" +#undef X +} + dict RTLIL::constpad; const pool &RTLIL::builtin_ff_cell_types() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index c81a0c00a..80d0d0cfb 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -83,6 +83,14 @@ namespace RTLIL SB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module }; + enum class StaticId : short { + STATIC_ID_BEGIN = 0, +#define X(N) N, +#include "kernel/constids.inc" +#undef X + STATIC_ID_END, + }; + struct Const; struct AttrObject; struct NamedObject; @@ -105,8 +113,18 @@ namespace RTLIL struct Process; struct Binding; struct IdString; + struct StaticIdString; typedef std::pair SigSig; + + struct StaticIdString { + constexpr StaticIdString(StaticId id, const IdString &id_str) : id_str(id_str), id(id) {} + constexpr inline operator const IdString &() const { return id_str; } + constexpr inline int index() const { return static_cast(id); } + + const IdString &id_str; + const StaticId id; + }; }; struct RTLIL::IdString @@ -127,7 +145,13 @@ struct RTLIL::IdString static std::vector global_id_storage_; static std::unordered_map global_id_index_; #ifndef YOSYS_NO_IDS_REFCNT - static std::vector global_refcount_storage_; + // For prepopulated IdStrings, the refcount is meaningless since they + // are never freed even if the refcount is zero. For code efficiency + // we increment the refcount of prepopulated IdStrings like any other string, + // but we never decrement the refcount or check whether it's zero. + // So, make this unsigned because refcounts of preopulated IdStrings may overflow + // and overflow of signed integers is undefined behavior. + static std::vector global_refcount_storage_; static std::vector global_free_idx_list_; #endif @@ -144,7 +168,7 @@ struct RTLIL::IdString if (global_id_storage_.at(idx) == nullptr) log("#X# DB-DUMP index %d: FREE\n", idx); else - log("#X# DB-DUMP index %d: '%s' (ref %d)\n", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx)); + log("#X# DB-DUMP index %d: '%s' (ref %u)\n", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx)); } #endif } @@ -166,15 +190,13 @@ struct RTLIL::IdString static inline int get_reference(int idx) { - if (idx) { #ifndef YOSYS_NO_IDS_REFCNT - global_refcount_storage_[idx]++; + global_refcount_storage_[idx]++; #endif #ifdef YOSYS_XTRACE_GET_PUT - if (yosys_xtrace) - log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + if (yosys_xtrace && idx >= static_cast(StaticId::STATIC_ID_END)) + log("#X# GET-BY-INDEX '%s' (index %d, refcount %u)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); #endif - } return idx; } @@ -182,9 +204,6 @@ struct RTLIL::IdString { log_assert(destruct_guard_ok); - if (!p[0]) - return 0; - auto it = global_id_index_.find((char*)p); if (it != global_id_index_.end()) { #ifndef YOSYS_NO_IDS_REFCNT @@ -192,11 +211,17 @@ struct RTLIL::IdString #endif #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace) - log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second)); + log("#X# GET-BY-NAME '%s' (index %d, refcount %u)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second)); #endif return it->second; } + if (global_id_index_.empty()) + prepopulate(); + + if (!p[0]) + return 0; + log_assert(p[0] == '$' || p[0] == '\\'); log_assert(p[1] != 0); for (const char *c = p; *c; c++) @@ -238,7 +263,7 @@ struct RTLIL::IdString #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace) - log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + log("#X# GET-BY-NAME '%s' (index %d, refcount %u)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); #endif #ifdef YOSYS_USE_STICKY_IDS @@ -258,21 +283,20 @@ struct RTLIL::IdString { // put_reference() may be called from destructors after the destructor of // global_refcount_storage_ has been run. in this case we simply do nothing. - if (!destruct_guard_ok || !idx) + if (idx < static_cast(StaticId::STATIC_ID_END) || !destruct_guard_ok) return; #ifdef YOSYS_XTRACE_GET_PUT if (yosys_xtrace) { - log("#X# PUT '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); + log("#X# PUT '%s' (index %d, refcount %u)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx)); } #endif - int &refcount = global_refcount_storage_[idx]; + uint32_t &refcount = global_refcount_storage_[idx]; if (--refcount > 0) return; - log_assert(refcount == 0); free_reference(idx); } static inline void free_reference(int idx) @@ -281,6 +305,7 @@ struct RTLIL::IdString log("#X# Removed IdString '%s' with index %d.\n", global_id_storage_.at(idx), idx); log_backtrace("-X- ", yosys_xtrace-1); } + log_assert(idx >= static_cast(StaticId::STATIC_ID_END)); global_id_index_.erase(global_id_storage_.at(idx)); free(global_id_storage_.at(idx)); @@ -300,6 +325,7 @@ struct RTLIL::IdString inline IdString(const IdString &str) : index_(get_reference(str.index_)) { } inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; } inline IdString(const std::string &str) : index_(get_reference(str.c_str())) { } + inline IdString(StaticId id) : index_(static_cast(id)) {} inline ~IdString() { put_reference(index_); } inline void operator=(const IdString &rhs) { @@ -331,6 +357,8 @@ struct RTLIL::IdString inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; } inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; } + inline bool operator==(const StaticIdString &rhs) const; + inline bool operator!=(const StaticIdString &rhs) const; // The methods below are just convenience functions for better compatibility with std::string. @@ -416,12 +444,16 @@ struct RTLIL::IdString } bool in(const IdString &rhs) const { return *this == rhs; } + bool in(const StaticIdString &rhs) const { return *this == rhs; } bool in(const char *rhs) const { return *this == rhs; } bool in(const std::string &rhs) const { return *this == rhs; } inline bool in(const pool &rhs) const; inline bool in(const pool &&rhs) const; bool isPublic() const { return begins_with("\\"); } + +private: + static void prepopulate(); }; namespace hashlib { @@ -449,12 +481,76 @@ inline bool RTLIL::IdString::in(const pool &rhs) const { return rhs.co [[deprecated]] inline bool RTLIL::IdString::in(const pool &&rhs) const { return rhs.count(*this) != 0; } +inline bool RTLIL::IdString::operator==(const RTLIL::StaticIdString &rhs) const { + return index_ == rhs.index(); +} +inline bool RTLIL::IdString::operator!=(const RTLIL::StaticIdString &rhs) const { + return index_ != rhs.index(); +} + namespace RTLIL { namespace ID { -#define X(_id) extern IdString _id; +#define X(_id) extern const IdString _id; #include "kernel/constids.inc" #undef X - }; + } +} + +struct IdTableEntry { + const std::string_view name; + const RTLIL::StaticIdString static_id; +}; + +constexpr IdTableEntry IdTable[] = { +#define X(_id) {#_id, RTLIL::StaticIdString(RTLIL::StaticId::_id, RTLIL::ID::_id)}, +#include "kernel/constids.inc" +#undef X +}; + +constexpr int lookup_well_known_id(std::string_view name) +{ + int low = 0; + int high = sizeof(IdTable) / sizeof(IdTable[0]); + while (high - low >= 2) { + int mid = (low + high) / 2; + if (name < IdTable[mid].name) + high = mid; + else + low = mid; + } + if (IdTable[low].name == name) + return low; + return -1; +} + +// Create a statically allocated IdString object, using for example ID::A or ID($add). +// +// Recipe for Converting old code that is using conversion of strings like ID::A and +// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for +// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. +// +// sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' +// +typedef const RTLIL::IdString &IDMacroHelperFunc(); + +template struct IDMacroHelper { + static constexpr RTLIL::StaticIdString eval(IDMacroHelperFunc) { + return IdTable[IdTableIndex].static_id; + } +}; +template <> struct IDMacroHelper<-1> { + static constexpr const RTLIL::IdString &eval(IDMacroHelperFunc func) { + return func(); + } +}; + +#define ID(_id) IDMacroHelper::eval([]() -> const RTLIL::IdString & { \ + const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ + static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); \ + return id; \ + }) + +namespace RTLIL { extern dict constpad; const pool &builtin_ff_cell_types(); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 68e107a3b..17832d241 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -211,10 +211,6 @@ void yosys_setup() init_share_dirname(); init_abc_executable_name(); -#define X(_id) RTLIL::ID::_id = "\\" # _id; -#include "kernel/constids.inc" -#undef X - Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 943aa4f05..fd84dd74e 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -206,13 +206,13 @@ namespace RTLIL { struct Module; struct Design; struct Monitor; - struct Selection; + struct Selection; struct SigChunk; enum State : unsigned char; typedef std::pair SigSig; - namespace ID {} + namespace ID {} } namespace AST { @@ -277,16 +277,6 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std: #define NEW_ID_SUFFIX(suffix) \ YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix) -// Create a statically allocated IdString object, using for example ID::A or ID($add). -// -// Recipe for Converting old code that is using conversion of strings like ID::A and -// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for -// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. -// -// sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' -// -#define ID(_id) ([]() -> const RTLIL::IdString & { const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ - static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); return id; })() namespace ID = RTLIL::ID; From 2a4a9aedfe76e902f6d0755b990edee86f9210aa Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 11:34:53 +0200 Subject: [PATCH 025/188] Ensure the ID macro consistently uses YOSYS_NAMESPACE_PREFIX The previous version of the ID macro used this for everything in the Yosys namespace, so the new version should continue to do so. --- kernel/rtlil.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 80d0d0cfb..999b60fd7 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -544,10 +544,14 @@ template <> struct IDMacroHelper<-1> { } }; -#define ID(_id) IDMacroHelper::eval([]() -> const RTLIL::IdString & { \ - const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ - static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); \ - return id; \ +#define ID(_id) \ + YOSYS_NAMESPACE_PREFIX IDMacroHelper< \ + YOSYS_NAMESPACE_PREFIX lookup_well_known_id(#_id) \ + >::eval([]() \ + -> const YOSYS_NAMESPACE_PREFIX RTLIL::IdString & { \ + const char *p = "\\" #_id, *q = p[1] == '$' ? p+1 : p; \ + static const YOSYS_NAMESPACE_PREFIX RTLIL::IdString id(q); \ + return id; \ }) namespace RTLIL { From 3ebecb631c0396371d9bdb5a06be0c0f2c53e5af Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 11:49:21 +0200 Subject: [PATCH 026/188] Add a compile time check that kernel/constids.inc is sorted This is an invariant now required by the ID macro, so it's better to have an actual check and not rely on a comment at the top of kernel/constids.inc. --- kernel/rtlil.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9c7e3888c..352fbb84e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -72,6 +72,19 @@ void RTLIL::IdString::prepopulate() #undef X } +static constexpr bool check_well_known_id_order() +{ + int size = sizeof(IdTable) / sizeof(IdTable[0]); + for (int i = 1; i < size; ++i) + if (IdTable[i - 1].name >= IdTable[i].name) + return false; + return true; +} + +// Ensure the statically allocated IdStrings in kernel/constids.inc are unique +// and in sorted ascii order, as required by the ID macro. +static_assert(check_well_known_id_order()); + dict RTLIL::constpad; const pool &RTLIL::builtin_ff_cell_types() { From b6db32873d505a6d4fad99665a7e869b750056d0 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 12:59:13 +0200 Subject: [PATCH 027/188] Add IdString const &id_string() const to StaticIdString and IdString The vast majority of ID(...) uses are in a context that is overloaded for StaticIdString or will cause implicit conversion to an IdString constant reference. For some sufficently overloaded contexts, implicit conversion may fail, so it's useful to have a method to force obtaining a `IdString const &` from an ID(...) use. When turning all literal IdStrings of the codebase into StaticIdStrings this was needed in exactly one place, for which this commit adds an `id_string()` call. --- kernel/rtlil.h | 3 +++ passes/cmds/example_dt.cc | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 999b60fd7..471aa5e5f 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -121,6 +121,7 @@ namespace RTLIL constexpr StaticIdString(StaticId id, const IdString &id_str) : id_str(id_str), id(id) {} constexpr inline operator const IdString &() const { return id_str; } constexpr inline int index() const { return static_cast(id); } + constexpr inline const IdString &id_string() const { return id_str; } const IdString &id_str; const StaticId id; @@ -343,6 +344,8 @@ struct RTLIL::IdString *this = id; } + constexpr inline const IdString &id_string() const { return *this; } + inline const char *c_str() const { return global_id_storage_.at(index_); } diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index b10f50502..7d1c42a79 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -77,7 +77,7 @@ struct ExampleDtPass : public Pass auto enqueue = [&](DriveSpec const &spec) { int index = queue(spec); if (index == GetSize(graph_nodes)) - graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index()); + graph_nodes.emplace_back(compute_graph.add(ID($pending).id_string(), index).index()); //if (index >= GetSize(graph_nodes)) return compute_graph[graph_nodes[index]]; }; From a97381448a1e17e0ce61f944ce98415706053b57 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 13:33:46 +0200 Subject: [PATCH 028/188] Ensure static IdStrings get prepopulated when initializing yosys An alternative would be to call ensure_prepopulated() in various IdString methods. --- kernel/rtlil.h | 9 +++++++-- kernel/yosys.cc | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 471aa5e5f..9112ae64b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -217,8 +217,7 @@ struct RTLIL::IdString return it->second; } - if (global_id_index_.empty()) - prepopulate(); + ensure_prepopulated(); if (!p[0]) return 0; @@ -457,6 +456,12 @@ struct RTLIL::IdString private: static void prepopulate(); + +public: + static void ensure_prepopulated() { + if (global_id_index_.empty()) + prepopulate(); + } }; namespace hashlib { diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 17832d241..46dc6a76f 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -196,6 +196,8 @@ void yosys_setup() already_setup = true; already_shutdown = false; + IdString::ensure_prepopulated(); + #ifdef WITH_PYTHON // With Python 3.12, calling PyImport_AppendInittab on an already // initialized platform fails (such as when libyosys is imported From 9213bc5d5455406c88d7e310a02d46769d38111b Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 13:07:40 +0200 Subject: [PATCH 029/188] Update kernel/constids.inc to include all literal ids I've used this shell command to obtain the list: rg -I -t cpp -t yacc -o \ 'ID\((\$?[a-zA-Z0-9_]+)\)|ID::($?[a-zA-Z0-9_]+)' -r 'X($1$2)' \ | LC_ALL=C sort -u This removed the entries X(_TECHMAP_FAIL_) and X(nomem2init). --- kernel/constids.inc | 700 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 695 insertions(+), 5 deletions(-) diff --git a/kernel/constids.inc b/kernel/constids.inc index 1419c89fa..2be70694a 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -1,62 +1,418 @@ // These must be in perfect ASCII order!!! +X($_ALDFFE_NNN_) +X($_ALDFFE_NNP_) +X($_ALDFFE_NPN_) +X($_ALDFFE_NPP_) +X($_ALDFFE_PNN_) +X($_ALDFFE_PNP_) +X($_ALDFFE_PPN_) +X($_ALDFFE_PPP_) +X($_ALDFF_NN_) +X($_ALDFF_NP_) +X($_ALDFF_PN_) +X($_ALDFF_PP_) +X($_ANDNOT_) X($_AND_) +X($_AOI3_) +X($_AOI4_) +X($_BUF_) +X($_DFFE_NN0N_) +X($_DFFE_NN0P_) +X($_DFFE_NN1N_) +X($_DFFE_NN1P_) +X($_DFFE_NN_) +X($_DFFE_NP0N_) +X($_DFFE_NP0P_) +X($_DFFE_NP1N_) +X($_DFFE_NP1P_) +X($_DFFE_NP_) +X($_DFFE_PN0N_) +X($_DFFE_PN0P_) +X($_DFFE_PN1N_) +X($_DFFE_PN1P_) +X($_DFFE_PN_) +X($_DFFE_PP0N_) +X($_DFFE_PP0P_) +X($_DFFE_PP1N_) +X($_DFFE_PP1P_) +X($_DFFE_PP_) +X($_DFFSRE_NNNN_) +X($_DFFSRE_NNNP_) +X($_DFFSRE_NNPN_) +X($_DFFSRE_NNPP_) +X($_DFFSRE_NPNN_) +X($_DFFSRE_NPNP_) +X($_DFFSRE_NPPN_) +X($_DFFSRE_NPPP_) +X($_DFFSRE_PNNN_) +X($_DFFSRE_PNNP_) +X($_DFFSRE_PNPN_) +X($_DFFSRE_PNPP_) +X($_DFFSRE_PPNN_) +X($_DFFSRE_PPNP_) +X($_DFFSRE_PPPN_) +X($_DFFSRE_PPPP_) +X($_DFFSR_NNN_) +X($_DFFSR_NNP_) +X($_DFFSR_NPN_) +X($_DFFSR_NPP_) +X($_DFFSR_PNN_) +X($_DFFSR_PNP_) +X($_DFFSR_PPN_) +X($_DFFSR_PPP_) +X($_DFF_N) +X($_DFF_NN0_) +X($_DFF_NN1_) +X($_DFF_NP0_) +X($_DFF_NP1_) +X($_DFF_N_) +X($_DFF_PN0_) +X($_DFF_PN1_) +X($_DFF_PP0_) +X($_DFF_PP1_) +X($_DFF_P_) +X($_DLATCHSR_NNN_) +X($_DLATCHSR_NNP_) +X($_DLATCHSR_NPN_) +X($_DLATCHSR_NPP_) +X($_DLATCHSR_PNN_) +X($_DLATCHSR_PNP_) +X($_DLATCHSR_PPN_) +X($_DLATCHSR_PPP_) +X($_DLATCH_NN0_) +X($_DLATCH_NN1_) +X($_DLATCH_NP0_) +X($_DLATCH_NP1_) +X($_DLATCH_N_) +X($_DLATCH_PN0_) +X($_DLATCH_PN1_) +X($_DLATCH_PP0_) +X($_DLATCH_PP1_) +X($_DLATCH_P_) +X($_FF_) +X($_MUX16_) +X($_MUX4_) +X($_MUX8_) +X($_MUX_) +X($_NAND_) +X($_NMUX_) +X($_NOR_) +X($_NOT_) +X($_OAI3_) +X($_OAI4_) +X($_ORNOT_) X($_OR_) +X($_SDFFCE_NN0N_) +X($_SDFFCE_NN0P_) +X($_SDFFCE_NN1N_) +X($_SDFFCE_NN1P_) +X($_SDFFCE_NP0N_) +X($_SDFFCE_NP0P_) +X($_SDFFCE_NP1N_) +X($_SDFFCE_NP1P_) +X($_SDFFCE_PN0N_) +X($_SDFFCE_PN0P_) +X($_SDFFCE_PN1N_) +X($_SDFFCE_PN1P_) +X($_SDFFCE_PP0N_) +X($_SDFFCE_PP0P_) +X($_SDFFCE_PP1N_) +X($_SDFFCE_PP1P_) +X($_SDFFE_NN0N_) +X($_SDFFE_NN0P_) +X($_SDFFE_NN1N_) +X($_SDFFE_NN1P_) +X($_SDFFE_NP0N_) +X($_SDFFE_NP0P_) +X($_SDFFE_NP1N_) +X($_SDFFE_NP1P_) +X($_SDFFE_PN0N_) +X($_SDFFE_PN0P_) +X($_SDFFE_PN1N_) +X($_SDFFE_PN1P_) +X($_SDFFE_PP0N_) +X($_SDFFE_PP0P_) +X($_SDFFE_PP1N_) +X($_SDFFE_PP1P_) +X($_SDFF_NN0_) +X($_SDFF_NN1_) +X($_SDFF_NP0_) +X($_SDFF_NP1_) +X($_SDFF_PN0_) +X($_SDFF_PN1_) +X($_SDFF_PP0_) +X($_SDFF_PP1_) +X($_SR_NN_) +X($_SR_NP_) +X($_SR_PN_) +X($_SR_PP_) +X($_TBUF_) +X($_XNOR_) X($_XOR_) +X($__ABC9_DELAY) +X($__ABC9_SCC_BREAKER) +X($__CC_NOT) +X($__COUNT_) +X($__ICE40_CARRY_WRAPPER) +X($__QLF_TDP36K) +X($__QLF_TDP36K_MERGED) +X($__XILINX_SHREG_) +X($abc9_flops) X($add) +X($adff) +X($adffe) +X($adlatch) +X($aldff) +X($aldffe) +X($allconst) +X($allseq) +X($alu) X($and) +X($anyconst) +X($anyinit) +X($anyseq) +X($assert) +X($assume) +X($bmux) +X($buf) +X($bugpoint) +X($bweq) +X($bweqx) +X($bwmux) +X($check) +X($concat) +X($cover) +X($demux) +X($dff) +X($dffe) +X($dffsr) +X($dffsre) +X($div) +X($divfloor) +X($dlatch) +X($dlatchsr) +X($eq) +X($equiv) +X($eqx) +X($fa) +X($fair) +X($false) +X($ff) +X($flowmap_level) +X($fsm) +X($fullskew) +X($future_ff) +X($ge) +X($get_tag) +X($gt) +X($initstate) +X($input) +X($lcu) +X($le) +X($live) X($logic_and) +X($logic_not) X($logic_or) +X($lt) +X($lut) +X($macc) +X($macc_v2) +X($mem) +X($mem_v2) +X($meminit) +X($meminit_v2) +X($memrd) +X($memrd_v2) +X($memwr) +X($memwr_v2) +X($mod) +X($modfloor) X($mul) +X($mux) +X($ne) +X($neg) +X($nex) +X($not) X($or) +X($original_tag) +X($output) +X($overwrite_tag) +X($pending) X($pmux) +X($pos) +X($pow) +X($print) +X($recrem) X($reduce_and) X($reduce_bool) +X($reduce_nand) X($reduce_or) X($reduce_xnor) X($reduce_xor) +X($scopeinfo) +X($sdff) +X($sdffce) +X($sdffe) +X($set_tag) +X($setup) +X($setuphold) +X($shift) +X($shiftx) +X($shl) +X($shr) +X($slice) +X($sop) +X($specify2) +X($specify3) +X($specrule) +X($sr) +X($sshl) +X($sshr) +X($state) +X($sub) +X($tribuf) +X($true) +X($undef) +X($xnor) X($xor) X(A) +X(A0REG) +X(A1) +X(A1REG) +X(A2) +X(A3) +X(A4) X(ABITS) +X(ACASCREG) +X(ACCUMCI) +X(ACCUMCO) +X(ACIN) X(AD) X(ADDEND_NEGATED) X(ADDR) +X(ADDSUBBOT) +X(ADDSUBTOP) +X(ADREG) +X(AHOLD) X(ALOAD) X(ALOAD_POLARITY) +X(ALUMODE) +X(ALUMODEREG) +X(ALUTYPE) +X(AL_MAP_ADDER) +X(AL_MAP_LUT1) +X(AL_MAP_LUT2) +X(AL_MAP_LUT3) +X(AL_MAP_LUT4) +X(AL_MAP_LUT5) +X(AL_MAP_LUT6) +X(ALn) +X(AND) +X(ANDNOT) +X(ANDTERM) +X(AOI3) +X(AOI4) +X(AREG) X(ARGS) X(ARGS_WIDTH) X(ARST) X(ARST_POLARITY) X(ARST_VALUE) +X(A_BYPASS) +X(A_EN) +X(A_INPUT) +X(A_REG) X(A_SIGNED) +X(A_SRST_N) X(A_WIDTH) X(A_WIDTHS) X(B) +X(B0REG) +X(B1) +X(B1REG) +X(B2) +X(B3) +X(B4) +X(BCASCREG) +X(BCIN) +X(BHOLD) X(BI) X(BITS_USED) -X(BYTE) +X(BOTADDSUB_CARRYSELECT) +X(BOTADDSUB_LOWERINPUT) +X(BOTADDSUB_UPPERINPUT) +X(BOTOUTPUT_SELECT) +X(BOT_8x8_MULT_REG) +X(BREG) +X(BUF) +X(BUFG) +X(BUFGSR) +X(BUFGTS) +X(B_BYPASS) +X(B_EN) +X(B_INPUT) +X(B_REG) X(B_SIGNED) +X(B_SRST_N) X(B_WIDTH) X(B_WIDTHS) X(C) +X(CARRYIN) +X(CARRYINREG) +X(CARRYINSEL) +X(CARRYINSELREG) +X(CARRYOUT) +X(CC_L2T4) +X(CC_L2T5) +X(CC_LUT2) +X(CDIN_FDBK_SEL) +X(CE) +X(CEA) +X(CEA1) +X(CEA2) +X(CEAD) +X(CEB) +X(CEB1) +X(CEB2) +X(CEC) +X(CED) +X(CEM) +X(CEP) X(CE_OVER_SRST) +X(CFG1) +X(CFG2) +X(CFG3) +X(CFG4) X(CFG_ABITS) X(CFG_DBITS) X(CFG_INIT) +X(CHOLD) X(CI) X(CLK) +X(CLKIN_DIVIDE) +X(CLKPOL) X(CLK_ENABLE) X(CLK_POLARITY) X(CLR) X(CLR_POLARITY) X(CO) X(COLLISION_X_MASK) +X(COMP_INP) X(CONFIG) X(CONFIG_WIDTH) +X(COUNT_EXTRACT) +X(COUNT_TO) +X(CREG) X(CTRL_IN) X(CTRL_IN_WIDTH) X(CTRL_OUT) X(CTRL_OUT_WIDTH) +X(C_ARST_N) +X(C_BYPASS) +X(C_EN) +X(C_REG) X(C_SIGNED) +X(C_SRST_N) X(C_WIDTHS) X(D) X(DAT) @@ -65,45 +421,248 @@ X(DAT_DST_PEN) X(DAT_DST_POL) X(DELAY) X(DEPTH) +X(DFF) +X(DHOLD) +X(DIRECTION) +X(DREG) +X(DSP48E1) X(DST) X(DST_EN) X(DST_PEN) X(DST_POL) X(DST_WIDTH) +X(D_ARST_N) +X(D_BYPASS) +X(D_EN) +X(D_REG) +X(D_SRST_N) X(E) X(EDGE_EN) X(EDGE_POL) +X(EFX_ADD) X(EN) +X(ENPOL) X(EN_DST) X(EN_POLARITY) X(EN_SRC) +X(EQN) X(F) +X(FDCE) +X(FDCE_1) +X(FDCP) +X(FDCPE) +X(FDCPE_1) +X(FDCPE_N) +X(FDCP_N) +X(FDDCP) +X(FDDCPE) +X(FDPE) +X(FDPE_1) +X(FDRE) +X(FDRE_1) +X(FDRSE) +X(FDRSE_1) +X(FDSE) +X(FDSE_1) X(FLAVOR) X(FORMAT) +X(FTCP) +X(FTCP_N) +X(FTDCP) X(FULL) X(G) +X(GP_DFF) +X(GP_DFFI) +X(GP_DFFR) +X(GP_DFFRI) +X(GP_DFFS) +X(GP_DFFSI) +X(GP_DFFSR) +X(GP_DFFSRI) +X(GP_DLATCH) +X(GP_DLATCHI) +X(GP_DLATCHR) +X(GP_DLATCHRI) +X(GP_DLATCHS) +X(GP_DLATCHSI) +X(GP_DLATCHSR) +X(GP_DLATCHSRI) +X(GP_INV) +X(GP_SHREG) +X(GSR) X(H) +X(HAS_CE) +X(HAS_POUT) X(I) +X(I0) +X(I0_POLARITY) +X(I1) +X(I1_POLARITY) +X(I2) +X(I3) +X(I3_IS_CI) +X(I4) +X(I5) +X(IBUF) +X(IN) X(INIT) +X(INIT1) +X(INIT2) +X(INIT_FILE) +X(INIT_L00) +X(INIT_L01) +X(INIT_L02) +X(INIT_L03) +X(INIT_L10) +X(INIT_L20) X(INIT_VALUE) +X(INMODE) +X(INMODEREG) +X(INV) +X(INVERT_OUT) +X(IN_B) +X(IN_ORTERM) +X(IN_PTC) +X(IOBUFE) +X(IRSTBOT) +X(IRSTTOP) +X(IS_C_INVERTED) +X(IS_D_INVERTED) +X(IS_R_INVERTED) +X(IS_S_INVERTED) X(J) X(K) X(L) +X(LAT) +X(LDCP) +X(LDCP_N) +X(LSR) X(LUT) +X(LUT1) +X(LUT2) +X(LUT3) +X(LUT4) +X(LUT5) +X(LUT6) +X(LUT_INIT) X(M) +X(MACROCELL_XOR) +X(MASK) X(MEMID) +X(MODE_8x8) +X(MODE_BITS) +X(MREG) +X(MUX) +X(MUX16) +X(MUX4) +X(MUX8) X(N) X(NADDENDS) X(NAME) +X(NAND) +X(NEG_TRIGGER) +X(NMUX) +X(NOR) +X(NOT) X(NPRODUCTS) +X(NX_CY) +X(NX_CY_1BIT) X(O) +X(OAI3) +X(OAI4) X(OFFSET) +X(OHOLDBOT) +X(OHOLDTOP) +X(OLOADBOT) +X(OLOADTOP) +X(ONE) +X(OPMODE) +X(OPMODEREG) +X(OPTION_SPLIT) +X(OR) +X(ORNOT) +X(ORSTBOT) +X(ORSTTOP) +X(ORTERM) +X(OUT) +X(OUTA) +X(OUTA_INVERT) +X(OUTA_TAP) +X(OUTB) +X(OUTB_TAP) +X(OVERFLOW) X(P) +X(PASUB) +X(PATTERN) +X(PCIN) +X(PIPELINE_16x16_MULT_REG1) +X(PIPELINE_16x16_MULT_REG2) X(PORTID) +X(PORT_A1_ADDR) +X(PORT_A1_CLK) +X(PORT_A1_CLK_EN) +X(PORT_A1_RD_DATA) +X(PORT_A1_WIDTH) +X(PORT_A1_WR_BE) +X(PORT_A1_WR_BE_WIDTH) +X(PORT_A1_WR_DATA) +X(PORT_A1_WR_EN) +X(PORT_A2_ADDR) +X(PORT_A2_CLK) +X(PORT_A2_CLK_EN) +X(PORT_A2_RD_DATA) +X(PORT_A2_WIDTH) +X(PORT_A2_WR_BE) +X(PORT_A2_WR_BE_WIDTH) +X(PORT_A2_WR_DATA) +X(PORT_A2_WR_EN) +X(PORT_A_ADDR) +X(PORT_A_CLK) +X(PORT_A_CLK_EN) +X(PORT_A_RD_DATA) +X(PORT_A_WIDTH) +X(PORT_A_WR_BE) +X(PORT_A_WR_BE_WIDTH) +X(PORT_A_WR_DATA) +X(PORT_A_WR_EN) +X(PORT_B1_ADDR) +X(PORT_B1_CLK) +X(PORT_B1_CLK_EN) +X(PORT_B1_RD_DATA) +X(PORT_B1_WIDTH) +X(PORT_B1_WR_BE) +X(PORT_B1_WR_BE_WIDTH) +X(PORT_B1_WR_DATA) +X(PORT_B1_WR_EN) +X(PORT_B2_ADDR) +X(PORT_B2_CLK) +X(PORT_B2_CLK_EN) +X(PORT_B2_RD_DATA) +X(PORT_B2_WIDTH) +X(PORT_B2_WR_BE) +X(PORT_B2_WR_BE_WIDTH) +X(PORT_B2_WR_DATA) +X(PORT_B2_WR_EN) +X(PORT_B_ADDR) +X(PORT_B_CLK) +X(PORT_B_CLK_EN) +X(PORT_B_RD_DATA) +X(PORT_B_WIDTH) +X(PORT_B_WR_BE) +X(PORT_B_WR_BE_WIDTH) +X(PORT_B_WR_DATA) +X(PORT_B_WR_EN) +X(POUT) +X(PRE) +X(PREG) X(PRIORITY) X(PRIORITY_MASK) X(PRODUCT_NEGATED) +X(P_BYPASS) +X(P_EN) +X(P_SRST_N) X(Q) +X(QL_DSP2) X(R) X(RD_ADDR) X(RD_ARST) @@ -122,10 +681,38 @@ X(RD_SRST_VALUE) X(RD_TRANSPARENCY_MASK) X(RD_TRANSPARENT) X(RD_WIDE_CONTINUATION) +X(RESET_MODE) +X(RESET_TO_MAX) +X(RST) +X(RSTA) +X(RSTB) +X(RSTC) +X(RSTD) +X(RSTM) +X(RSTP) X(S) +X(S1) +X(S2) +X(S3) +X(S4) +X(SB_CARRY) +X(SB_LUT4) +X(SB_MAC16) +X(SB_RAM40_4K) +X(SB_RAM40_4KNR) +X(SB_RAM40_4KNRNW) +X(SB_RAM40_4KNW) +X(SD) +X(SEL_MASK) +X(SEL_PATTERN) X(SET) X(SET_POLARITY) +X(SGSR) +X(SIGNEXTIN) +X(SIGNEXTOUT) X(SIZE) +X(SLE) +X(SLn) X(SRC) X(SRC_DST_PEN) X(SRC_DST_POL) @@ -133,6 +720,7 @@ X(SRC_EN) X(SRC_PEN) X(SRC_POL) X(SRC_WIDTH) +X(SRMODE) X(SRST) X(SRST_POLARITY) X(SRST_VALUE) @@ -141,24 +729,31 @@ X(STATE_NUM) X(STATE_NUM_LOG2) X(STATE_RST) X(STATE_TABLE) +X(SUB) X(S_WIDTH) X(T) X(TABLE) X(TAG) +X(TDP36K) +X(TOPADDSUB_CARRYSELECT) +X(TOPADDSUB_LOWERINPUT) +X(TOPADDSUB_UPPERINPUT) +X(TOPOUTPUT_SELECT) +X(TOP_8x8_MULT_REG) X(TRANSPARENCY_MASK) X(TRANSPARENT) X(TRANS_NUM) X(TRANS_TABLE) +X(TRELLIS_FF) X(TRG) X(TRG_ENABLE) X(TRG_POLARITY) X(TRG_WIDTH) +X(TRUE_INP) X(TYPE) X(T_FALL_MAX) X(T_FALL_MIN) X(T_FALL_TYP) -X(T_LIMIT) -X(T_LIMIT2) X(T_LIMIT2_MAX) X(T_LIMIT2_MIN) X(T_LIMIT2_TYP) @@ -169,6 +764,12 @@ X(T_RISE_MAX) X(T_RISE_MIN) X(T_RISE_TYP) X(U) +X(UP) +X(USE_DPORT) +X(USE_MULT) +X(USE_PATTERN_DETECT) +X(USE_SIMD) +X(UUT) X(V) X(WIDTH) X(WORDS) @@ -182,26 +783,41 @@ X(WR_PORTS) X(WR_PRIORITY_MASK) X(WR_WIDE_CONTINUATION) X(X) +X(XNOR) +X(XOR) X(Y) X(Y_WIDTH) +X(Z) +X(ZERO) X(_TECHMAP_BITS_CONNMAP_) X(_TECHMAP_CELLNAME_) X(_TECHMAP_CELLTYPE_) -X(_TECHMAP_FAIL_) X(_TECHMAP_PLACEHOLDER_) X(_TECHMAP_REPLACE_) +X(__glift_weight) +X(_const0_) +X(_const1_) +X(_dff_) +X(_id) X(_techmap_special_) +X(a) +X(a_i) X(abc9_box) X(abc9_box_id) X(abc9_box_seq) X(abc9_bypass) X(abc9_carry) +X(abc9_deferred_box) X(abc9_flop) X(abc9_keep) X(abc9_lut) X(abc9_mergeability) X(abc9_scc_id) +X(abc9_script) X(abcgroup) +X(acc_fir) +X(acc_fir_i) +X(add_carry) X(allconst) X(allseq) X(always_comb) @@ -209,34 +825,63 @@ X(always_ff) X(always_latch) X(anyconst) X(anyseq) +X(architecture) X(area) +X(b) +X(b_i) X(blackbox) +X(bottom_bound) X(bugpoint_keep) +X(c) X(capacitance) X(cells_not_processed) X(chain) +X(clk) +X(clk2fflogic) X(clkbuf_driver) X(clkbuf_inhibit) X(clkbuf_inv) X(clkbuf_sink) +X(clock_i) +X(cxxrtl_blackbox) +X(cxxrtl_comb) +X(cxxrtl_edge) +X(cxxrtl_sync) +X(cxxrtl_template) +X(cxxrtl_width) X(defaultvalue) +X(dff) +X(dffsre) +X(dft_tag) +X(dly_b) +X(dly_b_o) +X(dsp_t1_10x9x32) X(dynports) X(enum_base_type) X(enum_type) X(equiv_merged) X(equiv_region) X(extract_order) +X(f_mode) +X(feedback) +X(feedback_i) +X(first) X(force_downto) X(force_upto) X(fsm_encoding) X(fsm_export) X(full_case) +X(gate) +X(gate_cost_equivalent) X(gclk) X(gentb_clock) X(gentb_constant) X(gentb_skip) +X(glift) +X(gold) X(hdlname) X(hierconn) +X(i) X(init) X(initial_top) X(interface_modport) @@ -244,28 +889,44 @@ X(interface_type) X(interfaces_replaced_in_module) X(invertible_pin) X(iopad_external_pin) +X(is_inferred) X(is_interface) +X(it) X(keep) X(keep_hierarchy) X(lib_whitebox) +X(library) +X(load_acc) +X(load_acc_i) X(localparam) X(logic_block) X(lram) +X(lut) X(lut_keep) X(maximize) X(mem2reg) X(minimize) +X(module) X(module_not_derived) +X(nQ) +X(nRST) +X(nSET) +X(netlist) X(no_ram) X(no_rw_check) X(noblackbox) +X(nogsr) X(nolatches) -X(nomem2init) X(nomem2reg) X(nomeminit) X(nosync) X(nowrshmsk) +X(o) +X(offset) X(onehot) +X(output_select) +X(output_select_i) +X(p_class) X(parallel_case) X(parameter) X(promoted_if) @@ -274,17 +935,32 @@ X(ram_block) X(ram_style) X(ramstyle) X(reg) +X(register_inputs) +X(register_inputs_i) X(replaced_by_gclk) X(reprocess_after) +X(reset) +X(reset_i) X(rom_block) X(rom_style) X(romstyle) +X(round) +X(round_i) +X(rtlil) +X(saturate_enable) +X(saturate_enable_i) +X(scopename) +X(sdffsre) +X(shift_right) +X(shift_right_i) X(single_bit_vector) X(smtlib2_comb_expr) X(smtlib2_module) X(src) X(sta_arrival) X(submod) +X(subtract) +X(subtract_i) X(syn_ramstyle) X(syn_romstyle) X(techmap_autopurge) @@ -293,14 +969,28 @@ X(techmap_chtype) X(techmap_maccmap) X(techmap_simplemap) X(techmap_wrap) +X(test) X(to_delete) X(top) +X(top_bound) +X(trg_on_gclk) +X(trigger) X(unique) +X(unsigned_a) +X(unsigned_a_i) +X(unsigned_b) +X(unsigned_b_i) X(unused_bits) +X(use_dsp) +X(value) X(via_celltype) X(wand) X(whitebox) +X(width) X(wildcard_port_conns) X(wiretype) X(wor) X(xprop_decoder) +X(y) +X(z) +X(z_o) From 985b9164dae4a8bd733f017b60ceae78a1a02abb Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 14:11:31 +0200 Subject: [PATCH 030/188] Disable flaky arch/anlogic/mux test --- tests/arch/anlogic/mux.ys | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys index 89014b5e0..64a04d08d 100644 --- a/tests/arch/anlogic/mux.ys +++ b/tests/arch/anlogic/mux.ys @@ -36,9 +36,17 @@ select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT6 %% t:* %D +# Flaky test, started failing with statically allocated IdStrings, but works +# for me locally when I scramble the names using: +# +# rename -scramble-name -seed 1 +# + +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +#cd mux16 # Constrain all select calls below inside the top module +#show +#select -assert-count 5 t:AL_MAP_LUT6 + +#select -assert-none t:AL_MAP_LUT6 %% t:* %D From 6498265eb045262df5e0842477cc16caa799bd3a Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 13:55:09 +0200 Subject: [PATCH 031/188] Add macOS workaround to constids.inc The ID(OVERFLOW) IdString isn't used widely enough that we require a statically allocated IdString, but I think it's good to have an example workaround in place in case more collisions come up. --- kernel/constids.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/kernel/constids.inc b/kernel/constids.inc index 2be70694a..d75f0a784 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -1,4 +1,10 @@ // These must be in perfect ASCII order!!! + +// Workaround for macos's math.h defining an OVERFLOW macro +#ifdef OVERFLOW +#undef OVERFLOW +#endif + X($_ALDFFE_NNN_) X($_ALDFFE_NNP_) X($_ALDFFE_NPN_) From 0116dc438470351c7f389fd84c19bdd5ee01dd8a Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 8 Sep 2025 17:08:01 +0200 Subject: [PATCH 032/188] Add windows workaround to constids.inc --- kernel/constids.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/kernel/constids.inc b/kernel/constids.inc index d75f0a784..7aed897e1 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -5,6 +5,15 @@ #undef OVERFLOW #endif +// Workaround for windows defining IN and OUT macros in minwindef.h which ends +// up getting included for visual studio builds +#ifdef IN +#undef IN +#endif +#ifdef OUT +#undef OUT +#endif + X($_ALDFFE_NNN_) X($_ALDFFE_NNP_) X($_ALDFFE_NPN_) From 23e4c0e4245f26a3d069112ae92b5582c09a550e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 9 Sep 2025 00:23:18 +0000 Subject: [PATCH 033/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5b362a652..aedcd4d3b 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+7 +YOSYS_VER := 0.57+30 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 75316e8c496c93ec048682463d24f8ea28f0cab9 Mon Sep 17 00:00:00 2001 From: Michael Kupfer Date: Wed, 14 May 2025 20:23:29 +0200 Subject: [PATCH 034/188] Add state_dependent_path_declaration so that `ifnone` can be parsed --- frontends/verilog/verilog_lexer.l | 1 + frontends/verilog/verilog_parser.y | 56 ++++++++++++++++++++++++++---- tests/verilog/specify-ifnone.ys | 27 ++++++++++++++ 3 files changed, 77 insertions(+), 7 deletions(-) create mode 100644 tests/verilog/specify-ifnone.ys diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8280c0067..686e9853f 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -377,6 +377,7 @@ TIME_SCALE_SUFFIX [munpf]?s "begin" { return parser::make_TOK_BEGIN(out_loc); } "end" { return parser::make_TOK_END(out_loc); } "if" { return parser::make_TOK_IF(out_loc); } +"ifnone" { return parser::make_TOK_IFNONE(out_loc); } "else" { return parser::make_TOK_ELSE(out_loc); } "for" { return parser::make_TOK_FOR(out_loc); } "posedge" { return parser::make_TOK_POSEDGE(out_loc); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index c77d0a7cf..238d39254 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -493,7 +493,7 @@ %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH -%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT +%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_IFNONE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY @@ -1581,18 +1581,60 @@ list_of_specparam_assignments: specparam_assignment: ignspec_id TOK_EQ ignspec_expr ; -ignspec_opt_cond: - TOK_IF TOK_LPAREN ignspec_expr TOK_RPAREN | %empty; - path_declaration : simple_path_declaration TOK_SEMICOL // | edge_sensitive_path_declaration - // | state_dependent_path_declaration + | state_dependent_path_declaration TOK_SEMICOL ; simple_path_declaration : - ignspec_opt_cond parallel_path_description TOK_EQ path_delay_value | - ignspec_opt_cond full_path_description TOK_EQ path_delay_value + parallel_path_description TOK_EQ path_delay_value | + full_path_description TOK_EQ path_delay_value + ; + +state_dependent_path_declaration: + TOK_IF TOK_LPAREN module_path_expression TOK_RPAREN simple_path_declaration + // | TOK_IF TOK_LPAREN module_path_expression TOK_RPAREN edge_sensitive_path_declaration + | TOK_IFNONE simple_path_declaration + ; + +module_path_expression: + module_path_primary + // Flatten out unary_operator to avoid shift/reduce conflict + | TOK_EXCL attr module_path_primary { free_attr($2); } + | TOK_TILDE attr module_path_primary { free_attr($2); } + | TOK_AMP attr module_path_primary { free_attr($2); } + | OP_NAND attr module_path_primary { free_attr($2); } + | TOK_PIPE attr module_path_primary { free_attr($2); } + | OP_NOR attr module_path_primary { free_attr($2); } + | TOK_CARET attr module_path_primary { free_attr($2); } + | OP_XNOR attr module_path_primary { free_attr($2); } + // Flatten out binary_operator to avoid shift/reduce conflict + | module_path_expression OP_EQ attr module_path_expression { free_attr($3); } + | module_path_expression OP_NE attr module_path_expression { free_attr($3); } + | module_path_expression OP_LAND attr module_path_expression { free_attr($3); } + | module_path_expression OP_LOR attr module_path_expression { free_attr($3); } + | module_path_expression TOK_AMP attr module_path_expression { free_attr($3); } + | module_path_expression TOK_PIPE attr module_path_expression { free_attr($3); } + | module_path_expression TOK_CARET attr module_path_expression { free_attr($3); } + | module_path_expression OP_XNOR attr module_path_expression { free_attr($3); } + // | module_path_conditional_expression + ; + +module_path_primary: + number + | TOK_ID + // Deviate from specification: Normally string would not be allowed, however they are necessary for the ecp5 tests + | TOK_STRING + // | module_path_concatenation + // | module_path_multiple_concatenation + // | function_subroutine_call + // | TOK_LPAREN module_path_minmax_expression TOK_RPAREN + ; + +number: + integral_number + | TOK_REALVAL ; path_delay_value : diff --git a/tests/verilog/specify-ifnone.ys b/tests/verilog/specify-ifnone.ys new file mode 100644 index 000000000..50b11d487 --- /dev/null +++ b/tests/verilog/specify-ifnone.ys @@ -0,0 +1,27 @@ +# ifnone gets parsed and ignored without -specify +logger -expect-no-warnings +read_verilog << EOF +module dut1 (i, o); + output o; + input i; + specify + if (a ^ (* meow *) 1 == 1'b0) + (i => o) = 1; + ifnone (i => o) = 0; + endspecify +endmodule +EOF + +# ifnone is still an error with -specify +logger -expect error "syntax error" 1 +read_verilog -specify << EOF +module dut2 (i, o); + output o; + input i; + specify + if (a ^ (* meow *) 1 == 1'b0) + (i => o) = 1; + ifnone (i => o) = 0; + endspecify +endmodule +EOF From 61a00b91313118d414502b19d955bd1b679ade99 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 9 Sep 2025 13:24:48 +0200 Subject: [PATCH 035/188] memory_libmap: Fix use of uninitialized value for async read ports The code in memory_libmap expects `clk_en` to be initialized for all `PortVariant`s but the parsing in memlib.cc didn't initialize it for variants of kind `PortKind::Ar` (async read ports). While this fixes the immediate CI failure, it would be best to refactor the code so it becomes obvious if something isn't initialized. --- passes/memory/memlib.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index 8a7adc9ac..fb256e41c 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -855,7 +855,9 @@ struct Parser { PortVariant var; var.options = portopts; var.kind = pdef.kind; - if (pdef.kind != PortKind::Ar) { + if (pdef.kind == PortKind::Ar) { + var.clk_en = false; + } else { const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock"); if (!cdef) log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line); From 3f69a768f4aac3e1b95f830b13c866e20a0f073e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 02:30:12 +0000 Subject: [PATCH 036/188] Hide public `logv_` variant declarations that don't need to be public --- kernel/log.cc | 11 ++++++----- kernel/log.h | 5 ----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 3203ed3cf..1cd4a5449 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -102,7 +102,7 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) } #endif -void logv(const char *format, va_list ap) +static void logv(const char *format, va_list ap) { while (format[0] == '\n' && format[1] != 0) { log("\n"); @@ -204,7 +204,7 @@ void logv(const char *format, va_list ap) } } -void logv_header(RTLIL::Design *design, const char *format, va_list ap) +static void logv_header(RTLIL::Design *design, const char *format, va_list ap) { bool pop_errfile = false; @@ -305,12 +305,12 @@ static void logv_warning_with_prefix(const char *prefix, } } -void logv_warning(const char *format, va_list ap) +static void logv_warning(const char *format, va_list ap) { logv_warning_with_prefix("Warning: ", format, ap); } -void logv_warning_noprefix(const char *format, va_list ap) +static void logv_warning_noprefix(const char *format, va_list ap) { logv_warning_with_prefix("", format, ap); } @@ -390,7 +390,8 @@ static void logv_error_with_prefix(const char *prefix, #endif } -void logv_error(const char *format, va_list ap) +[[noreturn]] +static void logv_error(const char *format, va_list ap) { logv_error_with_prefix("ERROR: ", format, ap); } diff --git a/kernel/log.h b/kernel/log.h index 48997d250..27ee49d8f 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -119,11 +119,6 @@ extern int log_make_debug; extern int log_force_debug; extern int log_debug_suppressed; -void logv(const char *format, va_list ap); -void logv_header(RTLIL::Design *design, const char *format, va_list ap); -void logv_warning(const char *format, va_list ap); -void logv_warning_noprefix(const char *format, va_list ap); -[[noreturn]] void logv_error(const char *format, va_list ap); [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); From d34ac0c87d5a31eacfe9c8ae0ad350f72ba90349 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 10 Jul 2025 05:24:59 +0000 Subject: [PATCH 037/188] Make `log()` use the `FmtString` infrastructure. Now `log()` supports `std::string`. We have to fix a few places where the format parameter was not a compile time constant. This is mostly trivial. --- backends/cxxrtl/cxxrtl_backend.cc | 4 +-- kernel/io.h | 1 + kernel/log.cc | 45 +++++++++++++++++-------------- kernel/log.h | 35 +++++++++++++++++++----- passes/cmds/logcmd.cc | 10 +++---- passes/cmds/stat.cc | 2 +- passes/equiv/equiv_simple.cc | 2 +- passes/sat/sat.cc | 4 +-- passes/techmap/dfflibmap.cc | 14 +++++----- passes/tests/test_cell.cc | 2 +- 10 files changed, 74 insertions(+), 45 deletions(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 7080f54d5..0c9f6c054 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -3478,8 +3478,8 @@ struct CxxrtlWorker { }; struct CxxrtlBackend : public Backend { - static const int DEFAULT_OPT_LEVEL = 6; - static const int DEFAULT_DEBUG_LEVEL = 4; + static constexpr int DEFAULT_OPT_LEVEL = 6; + static constexpr int DEFAULT_DEBUG_LEVEL = 4; CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { } void help() override diff --git a/kernel/io.h b/kernel/io.h index 08c234d6e..2ad0a6466 100644 --- a/kernel/io.h +++ b/kernel/io.h @@ -437,6 +437,7 @@ public: { return format_emit_toplevel(fmt, has_escapes, specs, args...); } + std::string_view format_string() const { return fmt; } private: std::string_view fmt; bool has_escapes = false; diff --git a/kernel/log.cc b/kernel/log.cc index 1cd4a5449..0afc98cd0 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -102,17 +102,16 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) } #endif -static void logv(const char *format, va_list ap) -{ - while (format[0] == '\n' && format[1] != 0) { - log("\n"); - format++; +static void logv_string(std::string_view format, std::string str) { + size_t remove_leading = 0; + while (format.size() > 1 && format[0] == '\n') { + logv_string("\n", "\n"); + format = format.substr(1); + ++remove_leading; + } + if (remove_leading > 0) { + str = str.substr(remove_leading); } - - if (log_make_debug && !ys_debug(1)) - return; - - std::string str = vstringf(format, ap); if (str.empty()) return; @@ -145,13 +144,13 @@ static void logv(const char *format, va_list ap) time_str += stringf("[%05d.%06d] ", int(tv.tv_sec), int(tv.tv_usec)); } - if (format[0] && format[strlen(format)-1] == '\n') + if (!format.empty() && format[format.size() - 1] == '\n') next_print_log = true; // Special case to detect newlines in Python log output, since // the binding always calls `log("%s", payload)` and the newline // is then in the first formatted argument - if (!strcmp(format, "%s") && str.back() == '\n') + if (format == "%s" && str.back() == '\n') next_print_log = true; for (auto f : log_files) @@ -204,6 +203,20 @@ static void logv(const char *format, va_list ap) } } +static void logv(const char *format, va_list ap) +{ + if (log_make_debug && !ys_debug(1)) + return; + logv_string(format, vstringf(format, ap)); +} + +void log_formatted_string(std::string_view format, std::string str) +{ + if (log_make_debug && !ys_debug(1)) + return; + logv_string(format, std::move(str)); +} + static void logv_header(RTLIL::Design *design, const char *format, va_list ap) { bool pop_errfile = false; @@ -412,14 +425,6 @@ void log_file_error(const string &filename, int lineno, logv_file_error(filename, lineno, format, ap); } -void log(const char *format, ...) -{ - va_list ap; - va_start(ap, format); - logv(format, ap); - va_end(ap); -} - void log_header(RTLIL::Design *design, const char *format, ...) { va_list ap; diff --git a/kernel/log.h b/kernel/log.h index 27ee49d8f..f58bf3afe 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -121,7 +121,7 @@ extern int log_debug_suppressed; [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); -void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); + void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -145,6 +145,15 @@ static inline bool ys_debug(int = 0) { return false; } #endif # define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0) +void log_formatted_string(std::string_view format, std::string str); +template +inline void log(FmtString...> fmt, const Args &... args) +{ + if (log_make_debug && !ys_debug(1)) + return; + log_formatted_string(fmt.format_string(), fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); @@ -346,8 +355,22 @@ static inline void log_dump_val_worker(unsigned long int v) { log("%lu", v); } static inline void log_dump_val_worker(long long int v) { log("%lld", v); } static inline void log_dump_val_worker(unsigned long long int v) { log("%lld", v); } #endif -static inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); } -static inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); } +static inline void log_dump_val_worker(char c) +{ + if (c >= 32 && c < 127) { + log("'%c'", c); + } else { + log("'\\x%02x'", c); + } +} +static inline void log_dump_val_worker(unsigned char c) +{ + if (c >= 32 && c < 127) { + log("'%c'", c); + } else { + log("'\\x%02x'", c); + } +} static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false"); } static inline void log_dump_val_worker(double v) { log("%f", v); } static inline void log_dump_val_worker(char *v) { log("%s", v); } @@ -369,7 +392,7 @@ static inline void log_dump_val_worker(dict &v) { log("{"); bool first = true; for (auto &it : v) { - log(first ? " " : ", "); + log("%s ", first ? "" : ","); log_dump_val_worker(it.first); log(": "); log_dump_val_worker(it.second); @@ -383,7 +406,7 @@ static inline void log_dump_val_worker(pool &v) { log("{"); bool first = true; for (auto &it : v) { - log(first ? " " : ", "); + log("%s ", first ? "" : ","); log_dump_val_worker(it); first = false; } @@ -395,7 +418,7 @@ static inline void log_dump_val_worker(std::vector &v) { log("{"); bool first = true; for (auto &it : v) { - log(first ? " " : ", "); + log("%s ", first ? "" : ","); log_dump_val_worker(it); first = false; } diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 0238627d1..391eaea2e 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -101,13 +101,13 @@ struct LogPass : public Pass { text += args[argidx] + ' '; if (!text.empty()) text.resize(text.size()-1); - const char *fmtline = newline ? "%s\n" : "%s"; + const char *line_end = newline ? "\n" : ""; - if (to_stdout) fprintf(stdout, fmtline, text.c_str()); - if (to_stderr) fprintf(stderr, fmtline, text.c_str()); + if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end); + if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end); if (to_log) { - if (!header) log(fmtline, text.c_str()); - else log_header(design, fmtline, text.c_str()); + if (!header) log("%s%s", text.c_str(), line_end); + else log_header(design, "%s%s", text.c_str(), line_end); } } } LogPass; diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index ebbd10b5c..9281f3327 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -1017,7 +1017,7 @@ struct StatPass : public Pass { if (json_mode) { log("\n"); - log(top_mod == nullptr ? " }\n" : " },\n"); + log("%s", top_mod == nullptr ? " }\n" : " },\n"); } if (top_mod != nullptr) { diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 8ba42595e..9e3076077 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -331,7 +331,7 @@ struct EquivSimpleWorker construct_ezsat(input_bits, step); if (!ez->solve(ez_context)) { - log(cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); + log("%s", cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n"); // Replace $equiv cell with a short cell->setPort(ID::B, cell->getPort(ID::A)); ez->assume(ez->NOT(ez_context)); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 2f20880cb..60e099097 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -634,10 +634,10 @@ struct SatHelper "---------------------------------------------------------------------------------------------------" "---------------------------------------------------------------------------------------------------"; if (last_timestep == -2) { - log(max_timestep > 0 ? " Time " : " "); + log("%s", max_timestep > 0 ? " Time " : " "); log("%-*s %11s %9s %*s\n", maxModelName+5, "Signal Name", "Dec", "Hex", maxModelWidth+3, "Bin"); } - log(max_timestep > 0 ? " ---- " : " "); + log("%s", max_timestep > 0 ? " ---- " : " "); log("%*.*s %11.11s %9.9s %*.*s\n", maxModelName+5, maxModelName+5, hline, hline, hline, maxModelWidth+3, maxModelWidth+3, hline); last_timestep = info.timestep; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index a2b9c3bff..70d0f4ef5 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -135,7 +135,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std if (ff == nullptr || ff->args.size() != 2) return false; auto ff_output = ff->args.at(0); - + // This test is redundant with the one in enable_pin, but we're in a // position that gives better diagnostics here. if (!pin_names.count(ff_output)) { @@ -166,23 +166,23 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std // the ff output Q is in a known bit location, so we now just have to compare the LUT mask to known values to find the enable pin and polarity. if (lut == 0xD8) { data_name = pins[1]; - enable_name = pins[0]; + enable_name = pins[0]; return true; } if (lut == 0xB8) { data_name = pins[0]; - enable_name = pins[1]; + enable_name = pins[1]; return true; } enable_not_inverted = false; if (lut == 0xE4) { data_name = pins[1]; - enable_name = pins[0]; + enable_name = pins[0]; return true; } if (lut == 0xE2) { data_name = pins[0]; - enable_name = pins[1]; + enable_name = pins[1]; return true; } // this does not match an enable flop. @@ -553,11 +553,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) new_cell->setPort("\\" + port.first, sig); } - stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type, new_cell->type)]++; + stats[stringf("%s cells to %s cells", cell_type, new_cell->type)]++; } for (auto &stat: stats) - log(stat.first.c_str(), stat.second); + log(" mapped %d %s.\n", stat.second, stat.first); } struct DfflibmapPass : public Pass { diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 87e0a00f8..a08a6ec29 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -620,7 +620,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: for (int i = 0; i < 64; i++) { - log(verbose ? "\n" : "."); + log("%s", verbose ? "\n" : "."); gold_ce.clear(); gate_ce.clear(); From 66d2c2af08447ce1d4f80e91579a7348d1c65381 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 02:26:50 +0000 Subject: [PATCH 038/188] Make `log_header()` use variadic templates. --- kernel/log.cc | 12 ++---------- kernel/log.h | 8 +++++++- passes/opt/opt.cc | 2 +- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 0afc98cd0..bef3efb99 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -217,7 +217,7 @@ void log_formatted_string(std::string_view format, std::string str) logv_string(format, std::move(str)); } -static void logv_header(RTLIL::Design *design, const char *format, va_list ap) +void log_formatted_header(RTLIL::Design *design, std::string_view format, std::string str) { bool pop_errfile = false; @@ -236,7 +236,7 @@ static void logv_header(RTLIL::Design *design, const char *format, va_list ap) header_id += stringf("%s%d", header_id.empty() ? "" : ".", c); log("%s. ", header_id.c_str()); - logv(format, ap); + log_formatted_string(format, std::move(str)); log_flush(); if (log_hdump_all) @@ -425,14 +425,6 @@ void log_file_error(const string &filename, int lineno, logv_file_error(filename, lineno, format, ap); } -void log_header(RTLIL::Design *design, const char *format, ...) -{ - va_list ap; - va_start(ap, format); - logv_header(design, format, ap); - va_end(ap); -} - void log_warning(const char *format, ...) { va_list ap; diff --git a/kernel/log.h b/kernel/log.h index f58bf3afe..55fa58a34 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -122,7 +122,6 @@ extern int log_debug_suppressed; [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); -void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -154,6 +153,13 @@ inline void log(FmtString...> fmt, const Args &... args) log_formatted_string(fmt.format_string(), fmt.format(args...)); } +void log_formatted_header(RTLIL::Design *design, std::string_view format, std::string str); +template +inline void log_header(RTLIL::Design *design, FmtString...> fmt, const Args &... args) +{ + log_formatted_header(design, fmt.format_string(), fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 146c21cce..ec5760cd9 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -196,7 +196,7 @@ struct OptPass : public Pass { design->sort(); design->check(); - log_header(design, fast_mode ? "Finished fast OPT passes.\n" : "Finished OPT passes. (There is nothing left to do.)\n"); + log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)"); log_pop(); } } OptPass; From 25cba6181e533f41474e7e87f465b13616931651 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 03:14:15 +0000 Subject: [PATCH 039/188] Make log_warning()/log_warning_noprefix() use variadic templates. --- kernel/log.cc | 38 +++++--------------------------------- kernel/log.h | 14 ++++++++++++-- 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index bef3efb99..18de1296a 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -256,10 +256,8 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s log_files.pop_back(); } -static void logv_warning_with_prefix(const char *prefix, - const char *format, va_list ap) +void log_formatted_warning(std::string_view prefix, std::string message) { - std::string message = vstringf(format, ap); bool suppressed = false; for (auto &re : log_nowarn_regexes) @@ -268,7 +266,7 @@ static void logv_warning_with_prefix(const char *prefix, if (suppressed) { - log("Suppressed %s%s", prefix, message.c_str()); + log("Suppressed %s%s", prefix, message); } else { @@ -294,7 +292,7 @@ static void logv_warning_with_prefix(const char *prefix, if (log_warnings.count(message)) { - log("%s%s", prefix, message.c_str()); + log("%s%s", prefix, message); log_flush(); } else @@ -302,7 +300,7 @@ static void logv_warning_with_prefix(const char *prefix, if (log_errfile != NULL && !log_quiet_warnings) log_files.push_back(log_errfile); - log("%s%s", prefix, message.c_str()); + log("%s%s", prefix, message); log_flush(); if (log_errfile != NULL && !log_quiet_warnings) @@ -318,16 +316,6 @@ static void logv_warning_with_prefix(const char *prefix, } } -static void logv_warning(const char *format, va_list ap) -{ - logv_warning_with_prefix("Warning: ", format, ap); -} - -static void logv_warning_noprefix(const char *format, va_list ap) -{ - logv_warning_with_prefix("", format, ap); -} - void log_file_warning(const std::string &filename, int lineno, const char *format, ...) { @@ -335,7 +323,7 @@ void log_file_warning(const std::string &filename, int lineno, va_start(ap, format); std::string prefix = stringf("%s:%d: Warning: ", filename.c_str(), lineno); - logv_warning_with_prefix(prefix.c_str(), format, ap); + log_formatted_warning(prefix, vstringf(format, ap)); va_end(ap); } @@ -425,14 +413,6 @@ void log_file_error(const string &filename, int lineno, logv_file_error(filename, lineno, format, ap); } -void log_warning(const char *format, ...) -{ - va_list ap; - va_start(ap, format); - logv_warning(format, ap); - va_end(ap); -} - void log_experimental(const char *format, ...) { va_list ap; @@ -446,14 +426,6 @@ void log_experimental(const char *format, ...) } } -void log_warning_noprefix(const char *format, ...) -{ - va_list ap; - va_start(ap, format); - logv_warning_noprefix(format, ap); - va_end(ap); -} - void log_error(const char *format, ...) { va_list ap; diff --git a/kernel/log.h b/kernel/log.h index 55fa58a34..c8277f365 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -122,7 +122,6 @@ extern int log_debug_suppressed; [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); -void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); @@ -132,7 +131,6 @@ extern void (*log_verific_callback)(int msg_type, const char *message_id, const void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); -void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); [[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); [[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); [[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -160,6 +158,18 @@ inline void log_header(RTLIL::Design *design, FmtString...> f log_formatted_header(design, fmt.format_string(), fmt.format(args...)); } +void log_formatted_warning(std::string_view prefix, std::string str); +template +inline void log_warning(FmtString...> fmt, const Args &... args) +{ + log_formatted_warning("Warning: ", fmt.format(args...)); +} +template +inline void log_warning_noprefix(FmtString...> fmt, const Args &... args) +{ + log_formatted_warning("", fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From 2a2c586e2c6ff1d1cca63aefc6df3ba337fa87a7 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 03:51:29 +0000 Subject: [PATCH 040/188] Make log_experimental() just take an std::string, since it doesn't need to be varargs. --- kernel/log.cc | 13 ++++--------- kernel/log.h | 5 ++--- kernel/register.cc | 2 +- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 18de1296a..e5715425a 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -413,16 +413,11 @@ void log_file_error(const string &filename, int lineno, logv_file_error(filename, lineno, format, ap); } -void log_experimental(const char *format, ...) +void log_experimental(const std::string &str) { - va_list ap; - va_start(ap, format); - string s = vstringf(format, ap); - va_end(ap); - - if (log_experimentals_ignored.count(s) == 0 && log_experimentals.count(s) == 0) { - log_warning("Feature '%s' is experimental.\n", s.c_str()); - log_experimentals.insert(s); + if (log_experimentals_ignored.count(str) == 0 && log_experimentals.count(str) == 0) { + log_warning("Feature '%s' is experimental.\n", str); + log_experimentals.insert(str); } } diff --git a/kernel/log.h b/kernel/log.h index c8277f365..af30d9cfa 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -121,9 +121,6 @@ extern int log_debug_suppressed; [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); - -void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); - void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); @@ -170,6 +167,8 @@ inline void log_warning_noprefix(FmtString...> fmt, const Arg log_formatted_warning("", fmt.format(args...)); } +void log_experimental(const std::string &str); + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); diff --git a/kernel/register.cc b/kernel/register.cc index 0b02a6aa5..c82620f40 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -265,7 +265,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str()); if (pass_register[args[0]]->experimental_flag) - log_experimental("%s", args[0].c_str()); + log_experimental(args[0]); size_t orig_sel_stack_pos = design->selection_stack.size(); auto state = pass_register[args[0]]->pre_execute(); From 9764fa5c41c39d704762c961fbba3db4008d41e2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:01:02 +0000 Subject: [PATCH 041/188] Remove superfluous/wasteful .c_str()s in log_file_warning() filename parameter --- frontends/verilog/verilog_lexer.l | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 8280c0067..fbc9fca07 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -162,7 +162,7 @@ static bool is_hex_dig(char c, int *val, parser::location_type loc) *val = c - 'A' + 0xA; return true; } else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') { - log_file_warning(loc.begin.filename->c_str(), loc.begin.line, "'%c' not a valid digit in hex escape sequence.\n", c); + log_file_warning(*loc.begin.filename, loc.begin.line, "'%c' not a valid digit in hex escape sequence.\n", c); *val = 0; // not semantically valid in hex escape... return true; // ...but still processed as part of hex token } @@ -176,7 +176,7 @@ static bool is_oct_dig(char c, int *val, parser::location_type loc) *val = c - '0'; return true; } else if (c == 'x' || c == 'X' || c == 'z' || c == 'Z' || c == '?') { - log_file_warning(loc.begin.filename->c_str(), loc.begin.line, "'%c' not a valid digit in octal escape sequence.\n", c); + log_file_warning(*loc.begin.filename, loc.begin.line, "'%c' not a valid digit in octal escape sequence.\n", c); *val = 0; // not semantically valid in octal escape... return true; // ...but still processed as part of octal token } @@ -196,7 +196,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser:: if (in + 1 < str + len && (in[1] ^ *in) == ('\n' ^ '\r')) in++; if (!triple) - log_file_warning(loc.begin.filename->c_str(), loc.begin.line, "Multi-line string literals should be triple-quoted or escaped.\n"); + log_file_warning(*loc.begin.filename, loc.begin.line, "Multi-line string literals should be triple-quoted or escaped.\n"); *out++ = '\n'; break; case '\\': @@ -233,7 +233,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser:: } out++; } else - log_file_warning(loc.begin.filename->c_str(), loc.begin.line, "ignoring invalid hex escape.\n"); + log_file_warning(*loc.begin.filename, loc.begin.line, "ignoring invalid hex escape.\n"); break; case '\\': *out++ = '\\'; @@ -256,7 +256,7 @@ static parser::symbol_type process_str(char *str, int len, bool triple, parser:: in++; if (in + 1 < str + len && is_oct_dig(in[1], &val, loc)) { if (*out >= 040) - log_file_warning(loc.begin.filename->c_str(), loc.begin.line, "octal escape exceeds \\377\n"); + log_file_warning(*loc.begin.filename, loc.begin.line, "octal escape exceeds \\377\n"); *out = *out * 010 + val; in++; } From ec5f62e6d4b3a4a207935ff6d94bbb9c0508cc75 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:03:43 +0000 Subject: [PATCH 042/188] Make log_file_warning() use variadic templates. --- kernel/log.cc | 11 +++-------- kernel/log.h | 10 ++++++++-- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index e5715425a..911afbe9d 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -316,15 +316,10 @@ void log_formatted_warning(std::string_view prefix, std::string message) } } -void log_file_warning(const std::string &filename, int lineno, - const char *format, ...) +void log_formatted_file_warning(std::string_view filename, int lineno, std::string str) { - va_list ap; - va_start(ap, format); - std::string prefix = stringf("%s:%d: Warning: ", - filename.c_str(), lineno); - log_formatted_warning(prefix, vstringf(format, ap)); - va_end(ap); + std::string prefix = stringf("%s:%d: Warning: ", filename, lineno); + log_formatted_warning(prefix, std::move(str)); } void log_file_info(const std::string &filename, int lineno, diff --git a/kernel/log.h b/kernel/log.h index af30d9cfa..694b238df 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -124,8 +124,6 @@ extern int log_debug_suppressed; void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); -// Log with filename to report a problem in a source file. -void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); [[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -169,6 +167,14 @@ inline void log_warning_noprefix(FmtString...> fmt, const Arg void log_experimental(const std::string &str); +// Log with filename to report a problem in a source file. +void log_formatted_file_warning(std::string_view filename, int lineno, std::string str); +template +void log_file_warning(std::string_view filename, int lineno, FmtString...> fmt, const Args &... args) +{ + log_formatted_file_warning(filename, lineno, fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From ea2bb5b79aac400f473035e16094d664405477f2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:15:30 +0000 Subject: [PATCH 043/188] Make log_file_info() use variadic templates. --- kernel/log.cc | 17 ++--------------- kernel/log.h | 11 +++++++++-- 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 911afbe9d..27d58b45b 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -203,13 +203,6 @@ static void logv_string(std::string_view format, std::string str) { } } -static void logv(const char *format, va_list ap) -{ - if (log_make_debug && !ys_debug(1)) - return; - logv_string(format, vstringf(format, ap)); -} - void log_formatted_string(std::string_view format, std::string str) { if (log_make_debug && !ys_debug(1)) @@ -322,15 +315,9 @@ void log_formatted_file_warning(std::string_view filename, int lineno, std::stri log_formatted_warning(prefix, std::move(str)); } -void log_file_info(const std::string &filename, int lineno, - const char *format, ...) +void log_formatted_file_info(std::string_view filename, int lineno, std::string str) { - va_list ap; - va_start(ap, format); - std::string fmt = stringf("%s:%d: Info: %s", - filename.c_str(), lineno, format); - logv(fmt.c_str(), ap); - va_end(ap); + log("%s:%d: Info: %s", filename, lineno, str); } [[noreturn]] diff --git a/kernel/log.h b/kernel/log.h index 694b238df..c3cbbc04a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -124,8 +124,6 @@ extern int log_debug_suppressed; void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); -void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); - [[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); [[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); [[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -175,6 +173,15 @@ void log_file_warning(std::string_view filename, int lineno, FmtString +void log_file_info(std::string_view filename, int lineno, FmtString...> fmt, const Args &... args) +{ + if (log_make_debug && !ys_debug(1)) + return; + log_formatted_file_info(filename, lineno, fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From 1b5373de0d4137c671c298cbf6e5530178a10ab8 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 23 Aug 2025 18:21:33 +1200 Subject: [PATCH 044/188] Move log_assert_worker()'s call to log_error() into an out-of-line non-varags function --- kernel/log.cc | 5 +++++ kernel/log.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/kernel/log.cc b/kernel/log.cc index 27d58b45b..1e95ea5c5 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -410,6 +410,11 @@ void log_error(const char *format, ...) logv_error(format, ap); } +void log_assert_failure(const char *expr, const char *file, int line) +{ + log_error("Assert `%s' failed in %s:%d.\n", expr, file, line); +} + void log_cmd_error(const char *format, ...) { va_list ap; diff --git a/kernel/log.h b/kernel/log.h index c3cbbc04a..40e1f02ff 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -252,9 +252,11 @@ void log_module(RTLIL::Module *module, std::string indent = ""); void log_cell(RTLIL::Cell *cell, std::string indent = ""); void log_wire(RTLIL::Wire *wire, std::string indent = ""); +[[noreturn]] +void log_assert_failure(const char *expr, const char *file, int line); #ifndef NDEBUG static inline void log_assert_worker(bool cond, const char *expr, const char *file, int line) { - if (!cond) log_error("Assert `%s' failed in %s:%d.\n", expr, file, line); + if (!cond) log_assert_failure(expr, file, line); } # define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__) #else From c3924d06169d4172a336c4ac39766f2bb969c6af Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 23 Aug 2025 18:30:07 +1200 Subject: [PATCH 045/188] Move log_abort()'s call to log_error() into an out-of-line non-varargs function --- kernel/log.cc | 5 +++++ kernel/log.h | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/kernel/log.cc b/kernel/log.cc index 1e95ea5c5..6bab033de 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -415,6 +415,11 @@ void log_assert_failure(const char *expr, const char *file, int line) log_error("Assert `%s' failed in %s:%d.\n", expr, file, line); } +void log_abort_internal(const char *file, int line) +{ + log_error("Abort in %s:%d.\n", file, line); +} + void log_cmd_error(const char *format, ...) { va_list ap; diff --git a/kernel/log.h b/kernel/log.h index 40e1f02ff..653a73ba3 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -263,7 +263,9 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi # define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0) #endif -#define log_abort() YOSYS_NAMESPACE_PREFIX log_error("Abort in %s:%d.\n", __FILE__, __LINE__) +[[noreturn]] +void log_abort_internal(const char *file, int line); +#define log_abort() YOSYS_NAMESPACE_PREFIX log_abort_internal(__FILE__, __LINE__) #define log_ping() YOSYS_NAMESPACE_PREFIX log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__) From 974455378b14e0aa71a7fc55517209bf1cdd0a6c Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:28:32 +0000 Subject: [PATCH 046/188] Make log_error() use variadic templates. --- kernel/log.cc | 25 ++++++++----------------- kernel/log.h | 8 +++++++- 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 6bab033de..55e721768 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -268,7 +268,7 @@ void log_formatted_warning(std::string_view prefix, std::string message) for (auto &re : log_werror_regexes) if (std::regex_search(message, re)) - log_error("%s", message.c_str()); + log_error("%s", message); bool warning_match = false; for (auto &[_, item] : log_expect_warning) @@ -321,8 +321,7 @@ void log_formatted_file_info(std::string_view filename, int lineno, std::string } [[noreturn]] -static void logv_error_with_prefix(const char *prefix, - const char *format, va_list ap) +static void log_error_with_prefix(std::string_view prefix, std::string str) { #ifdef EMSCRIPTEN auto backup_log_files = log_files; @@ -339,8 +338,8 @@ static void logv_error_with_prefix(const char *prefix, if (f == stdout) f = stderr; - log_last_error = vstringf(format, ap); - log("%s%s", prefix, log_last_error.c_str()); + log_last_error = std::move(str); + log("%s%s", prefix, log_last_error); log_flush(); log_make_debug = bak_log_make_debug; @@ -373,18 +372,12 @@ static void logv_error_with_prefix(const char *prefix, #endif } -[[noreturn]] -static void logv_error(const char *format, va_list ap) -{ - logv_error_with_prefix("ERROR: ", format, ap); -} - void logv_file_error(const string &filename, int lineno, const char *format, va_list ap) { std::string prefix = stringf("%s:%d: ERROR: ", filename.c_str(), lineno); - logv_error_with_prefix(prefix.c_str(), format, ap); + log_error_with_prefix(prefix, vstringf(format, ap)); } void log_file_error(const string &filename, int lineno, @@ -403,11 +396,9 @@ void log_experimental(const std::string &str) } } -void log_error(const char *format, ...) +void log_formatted_error(std::string str) { - va_list ap; - va_start(ap, format); - logv_error(format, ap); + log_error_with_prefix("ERROR: ", std::move(str)); } void log_assert_failure(const char *expr, const char *file, int line) @@ -445,7 +436,7 @@ void log_cmd_error(const char *format, ...) throw log_cmd_error_exception(); } - logv_error(format, ap); + log_formatted_error(vstringf(format, ap)); } void log_spacer() diff --git a/kernel/log.h b/kernel/log.h index 653a73ba3..396a24efa 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -124,7 +124,6 @@ extern int log_debug_suppressed; void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); -[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); [[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); [[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); @@ -182,6 +181,13 @@ void log_file_info(std::string_view filename, int lineno, FmtString +[[noreturn]] void log_error(FmtString...> fmt, const Args &... args) +{ + log_formatted_error(fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From 243f5f52013a4dd7efcb44b564d916c2c094435c Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:35:30 +0000 Subject: [PATCH 047/188] Make log_file_error() use variadic templates. --- kernel/log.cc | 18 +++++++----------- kernel/log.h | 8 +++++++- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 55e721768..ceebc3a86 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -372,20 +372,16 @@ static void log_error_with_prefix(std::string_view prefix, std::string str) #endif } +void log_formatted_file_error(std::string_view filename, int lineno, std::string str) +{ + std::string prefix = stringf("%s:%d: ERROR: ", filename, lineno); + log_error_with_prefix(prefix, str); +} + void logv_file_error(const string &filename, int lineno, const char *format, va_list ap) { - std::string prefix = stringf("%s:%d: ERROR: ", - filename.c_str(), lineno); - log_error_with_prefix(prefix, vstringf(format, ap)); -} - -void log_file_error(const string &filename, int lineno, - const char *format, ...) -{ - va_list ap; - va_start(ap, format); - logv_file_error(filename, lineno, format, ap); + log_formatted_file_error(filename, lineno, vstringf(format, ap)); } void log_experimental(const std::string &str) diff --git a/kernel/log.h b/kernel/log.h index 396a24efa..6cd97ce11 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -124,7 +124,6 @@ extern int log_debug_suppressed; void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); -[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); [[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); #ifndef NDEBUG @@ -188,6 +187,13 @@ template log_formatted_error(fmt.format(args...)); } +[[noreturn]] void log_formatted_file_error(std::string_view filename, int lineno, std::string str); +template +[[noreturn]] void log_file_error(std::string_view filename, int lineno, FmtString...> fmt, const Args &... args) +{ + log_formatted_file_error(filename, lineno, fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From a137d03c329393397ea42f342efa44002f5a6f9f Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 22 Jul 2025 04:42:43 +0000 Subject: [PATCH 048/188] Make log_cmd_error() use variadic templates. --- kernel/log.cc | 11 ++++------- kernel/log.h | 9 +++++++-- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index ceebc3a86..0dd56a04f 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -407,13 +407,10 @@ void log_abort_internal(const char *file, int line) log_error("Abort in %s:%d.\n", file, line); } -void log_cmd_error(const char *format, ...) +void log_formatted_cmd_error(std::string str) { - va_list ap; - va_start(ap, format); - if (log_cmd_error_throw) { - log_last_error = vstringf(format, ap); + log_last_error = str; // Make sure the error message gets through any selective silencing // of log output @@ -423,7 +420,7 @@ void log_cmd_error(const char *format, ...) pop_errfile = true; } - log("ERROR: %s", log_last_error.c_str()); + log("ERROR: %s", log_last_error); log_flush(); if (pop_errfile) @@ -432,7 +429,7 @@ void log_cmd_error(const char *format, ...) throw log_cmd_error_exception(); } - log_formatted_error(vstringf(format, ap)); + log_formatted_error(str); } void log_spacer() diff --git a/kernel/log.h b/kernel/log.h index 6cd97ce11..5143524bf 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -124,8 +124,6 @@ extern int log_debug_suppressed; void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); -[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); - #ifndef NDEBUG static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; } #else @@ -194,6 +192,13 @@ template log_formatted_file_error(filename, lineno, fmt.format(args...)); } +[[noreturn]] void log_formatted_cmd_error(std::string str); +template +[[noreturn]] void log_cmd_error(FmtString...> fmt, const Args &... args) +{ + log_formatted_cmd_error(fmt.format(args...)); +} + static inline void log_suppressed() { if (log_debug_suppressed && !log_make_debug) { log("\n", log_debug_suppressed); From 75a97241fabeb898e0c801349350912cd03cf7d0 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 9 Sep 2025 10:23:15 +0200 Subject: [PATCH 049/188] Maintain logging ABI compatiblity with YosysHQ Verific Extensions The YosysHQ Verific Extensions are compiled separately using their own stripped-down version of the Yosys headers. To maintain ABI compatibility with older extension builds post C++-ification of Yosys's logging APIs, which are backwards compatible on the API but not ABI level, this commit adds ABI compatible versions of a subset of the old logging API used by the extensions. --- Makefile | 3 ++ kernel/log_compat.cc | 86 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 kernel/log_compat.cc diff --git a/Makefile b/Makefile index aedcd4d3b..fc8d361e6 100644 --- a/Makefile +++ b/Makefile @@ -633,6 +633,9 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o OBJS += kernel/log_help.o +ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1) +OBJS += kernel/log_compat.o +endif OBJS += kernel/binding.o kernel/tclapi.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o OBJS += kernel/drivertools.o kernel/functional.o diff --git a/kernel/log_compat.cc b/kernel/log_compat.cc new file mode 100644 index 000000000..e93714873 --- /dev/null +++ b/kernel/log_compat.cc @@ -0,0 +1,86 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + + +#include "kernel/log.h" + +YOSYS_NAMESPACE_BEGIN + +// ABI compatibility for the YosysHQ Verific Extensions + +// The YosysHQ Verific Extensions are compiled separately using their own +// stripped-down version of the Yosys headers. To maintain ABI compatibility +// with older extension builds post C++-ification of Yosys's logging APIs, +// which are backwards compatible on the API but not ABI level, this file +// provides ABI compatible versions of a subset of the old logging API used by +// the extensions. + +void log_cmd_error(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string formatted = vstringf(format, ap); + va_end(ap); + log_formatted_cmd_error(formatted); +} + +void log_warning(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string formatted = vstringf(format, ap); + va_end(ap); + log_formatted_warning("Warning: ", formatted); +} + +void log_warning_noprefix(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string formatted = vstringf(format, ap); + va_end(ap); + log_formatted_warning("", formatted); +} + +void log_error(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string formatted = vstringf(format, ap); + va_end(ap); + log_formatted_error(formatted); +} + +static inline void log_formatted(std::string const &str) +{ + // We use this inline wrapper as the following becomes ambiguous as soon as + // the `log` function below is declared. + return log("%s", str); +} + +void log(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + std::string formatted = vstringf(format, ap); + va_end(ap); + log_formatted(formatted); +} + +YOSYS_NAMESPACE_END From c2291c10a6f27142bc376d8aa62c66cf856fcab9 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 10 Sep 2025 00:22:30 +0000 Subject: [PATCH 050/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fc8d361e6..5da8066db 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+30 +YOSYS_VER := 0.57+52 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 9a6f25fb738cf50186dcb92fbb774e20f54d518d Mon Sep 17 00:00:00 2001 From: Xing Guo Date: Thu, 11 Sep 2025 00:47:40 +0800 Subject: [PATCH 051/188] verilog_parser: Use unique_ptr<> to store the attribute list. We can get rid of the new / delete statements and free_attr() and we don't need to manage the memory manually. --- frontends/verilog/verilog_parser.y | 298 ++++++++++++++--------------- 1 file changed, 144 insertions(+), 154 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb61e05df..3db92be01 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -69,9 +69,10 @@ struct ParseState { int port_counter; dict port_stubs; - dict> *attr_list, default_attr_list; - std::stack> *> attr_list_stack; - dict> *albuf; + std::unique_ptr>> attr_list; + dict> default_attr_list; + std::stack>>> attr_list_stack; + std::unique_ptr>> albuf; std::vector user_type_stack; dict pkg_user_types; std::vector ast_stack; @@ -97,13 +98,16 @@ bool isInLocalScope(const std::string *name); void rewriteGenForDeclInit(AstNode *loop); void ensureAsgnExprAllowed(const parser::location_type loc, bool sv_mode); - const AstNode *addIncOrDecStmt(dict> *stmt_attr, + const AstNode *addIncOrDecStmt(std::unique_ptr>> stmt_attr, std::unique_ptr lhs, - dict> *op_attr, AST::AstNodeType op, + std::unique_ptr>> op_attr, AST::AstNodeType op, parser::location_type loc); - std::unique_ptr addIncOrDecExpr(std::unique_ptr lhs, dict> *attr, AST::AstNodeType op, parser::location_type loc, bool undo, bool sv_mode); + std::unique_ptr addIncOrDecExpr(std::unique_ptr lhs, + std::unique_ptr>> attr, + AST::AstNodeType op, parser::location_type loc, bool undo, bool sv_mode); // add a binary operator assignment statement, e.g., a += b - std::unique_ptr addAsgnBinopStmt(dict> *attr, std::unique_ptr eq_lhs, AST::AstNodeType op, std::unique_ptr rhs); + std::unique_ptr addAsgnBinopStmt(std::unique_ptr>> attr, + std::unique_ptr eq_lhs, AST::AstNodeType op, std::unique_ptr rhs); }; struct ParseMode { bool noassert = false; @@ -150,26 +154,20 @@ return Location(begin.begin, end.end); } - static void append_attr(AstNode *ast, dict> *al) + static void append_attr(AstNode *ast, std::unique_ptr>> al) { for (auto &it : *al) { ast->attributes[it.first] = std::move(it.second); } - delete al; } - static void append_attr_clone(AstNode *ast, dict> *al) + static void append_attr_clone(AstNode *ast, std::unique_ptr>> &al) { for (auto &it : *al) { ast->attributes[it.first] = it.second->clone(); } } - static void free_attr(dict> *al) - { - delete al; - } - static std::unique_ptr makeRange(parser::location_type loc, int msb = 31, int lsb = 0, bool isSigned = true) { auto range = std::make_unique(loc, AST_RANGE); @@ -363,28 +361,31 @@ } // add a pre/post-increment/decrement statement - const AstNode *ParseState::addIncOrDecStmt(dict> *stmt_attr, + const AstNode *ParseState::addIncOrDecStmt(std::unique_ptr>> stmt_attr, std::unique_ptr lhs, - dict> *op_attr, AST::AstNodeType op, + std::unique_ptr>> op_attr, AST::AstNodeType op, Location loc) { auto one = AstNode::mkconst_int(loc, 1, true); auto rhs = std::make_unique(loc, op, lhs->clone(), std::move(one)); - if (op_attr != nullptr) - append_attr(rhs.get(), op_attr); + if (op_attr) + append_attr(rhs.get(), std::move(op_attr)); auto stmt_owned = std::make_unique(loc, AST_ASSIGN_EQ, std::move(lhs), std::move(rhs)); auto* stmt = stmt_owned.get(); ast_stack.back()->children.push_back(std::move(stmt_owned)); - if (stmt_attr != nullptr) - append_attr(stmt, stmt_attr); + if (stmt_attr) + append_attr(stmt, std::move(stmt_attr)); return stmt; } // create a pre/post-increment/decrement expression, and add the corresponding statement - std::unique_ptr ParseState::addIncOrDecExpr(std::unique_ptr lhs, dict> *attr, AST::AstNodeType op, Location loc, bool undo, bool sv_mode) + std::unique_ptr ParseState::addIncOrDecExpr(std::unique_ptr lhs, + std::unique_ptr>> attr, + AST::AstNodeType op, Location loc, bool undo, bool sv_mode) { ensureAsgnExprAllowed(loc, sv_mode); - const AstNode *stmt = addIncOrDecStmt(nullptr, std::move(lhs), attr, op, loc); + const AstNode *stmt = addIncOrDecStmt(nullptr, std::move(lhs), std::move(attr), op, loc); log_assert(stmt->type == AST_ASSIGN_EQ); auto expr = stmt->children[0]->clone(); if (undo) { @@ -396,7 +397,8 @@ } // add a binary operator assignment statement, e.g., a += b - std::unique_ptr ParseState::addAsgnBinopStmt(dict> *attr, std::unique_ptr eq_lhs, AST::AstNodeType op, std::unique_ptr rhs) + std::unique_ptr ParseState::addAsgnBinopStmt(std::unique_ptr>> attr, + std::unique_ptr eq_lhs, AST::AstNodeType op, std::unique_ptr rhs) { Location loc = location_range(eq_lhs->location, rhs->location); if (op == AST_SHIFT_LEFT || op == AST_SHIFT_RIGHT || @@ -409,8 +411,8 @@ auto stmt_owned = std::make_unique(loc, AST_ASSIGN_EQ, std::move(eq_lhs), std::move(eq_rhs_owned)); auto* stmt = stmt_owned.get(); ast_stack.back()->children.push_back(std::move(stmt_owned)); - if (attr != nullptr) - append_attr(stmt, attr); + if (attr) + append_attr(stmt, std::move(attr)); return ret_lhs; } }; @@ -460,7 +462,7 @@ using string_t = std::unique_ptr; using ast_t = std::unique_ptr; - using al_t = YOSYS_NAMESPACE_PREFIX dict>*; + using al_t = std::unique_ptr>>; using specify_target_ptr_t = std::unique_ptr; using specify_triple_ptr_t = std::unique_ptr; using specify_rise_fall_ptr_t = std::unique_ptr; @@ -613,15 +615,15 @@ design: attr: { - if (extra->attr_list != nullptr) - extra->attr_list_stack.push(extra->attr_list); - extra->attr_list = new dict>; + if (extra->attr_list) + extra->attr_list_stack.push(std::move(extra->attr_list)); + extra->attr_list = std::make_unique>>(); for (auto &it : extra->default_attr_list) (*extra->attr_list)[it.first] = it.second->clone(); } attr_opt { - $$ = extra->attr_list; + $$ = std::move(extra->attr_list); if (!extra->attr_list_stack.empty()) { - extra->attr_list = extra->attr_list_stack.top(); + extra->attr_list = std::move(extra->attr_list_stack.top()); extra->attr_list_stack.pop(); } else extra->attr_list = nullptr; @@ -636,14 +638,14 @@ attr_opt: defattr: DEFATTR_BEGIN { if (extra->attr_list != nullptr) - extra->attr_list_stack.push(extra->attr_list); - extra->attr_list = new dict>; + extra->attr_list_stack.push(std::move(extra->attr_list)); + extra->attr_list = std::make_unique>>(); extra->default_attr_list.clear(); } opt_attr_list { extra->attr_list->swap(extra->default_attr_list); - delete extra->attr_list; + extra->attr_list.reset(); if (!extra->attr_list_stack.empty()) { - extra->attr_list = extra->attr_list_stack.top(); + extra->attr_list = std::move(extra->attr_list_stack.top()); extra->attr_list_stack.pop(); } else extra->attr_list = nullptr; @@ -699,7 +701,7 @@ module: extra->port_stubs.clear(); extra->port_counter = 0; mod->str = *$4; - append_attr(mod, $1); + append_attr(mod, std::move($1)); } module_para_opt module_args_opt TOK_SEMICOL module_body TOK_ENDMODULE opt_label { if (extra->port_stubs.size() != 0) err_at_loc(@7, "Missing details for module port `%s'.", @@ -723,12 +725,12 @@ single_module_para: attr TOK_PARAMETER { extra->astbuf1 = std::make_unique(@$, AST_PARAMETER); extra->astbuf1->children.push_back(AstNode::mkconst_int(@2, 0, true)); - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); } param_type single_param_decl | attr TOK_LOCALPARAM { extra->astbuf1 = std::make_unique(@$, AST_LOCALPARAM); extra->astbuf1->children.push_back(AstNode::mkconst_int(@2, 0, true)); - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); } param_type single_param_decl | single_param_decl; @@ -798,7 +800,7 @@ module_arg: err_at_loc(@4, "Module port `%s' is neither input nor output.", $4->c_str()); if (node->is_reg && node->is_input && !node->is_output && !mode->sv) err_at_loc(@4, "Input port `%s' is declared as register.", $4->c_str()); - append_attr(node.get(), $1); + append_attr(node.get(), std::move($1)); extra->ast_stack.back()->children.push_back(std::move(node)); } module_arg_opt_assignment | TOK_DOT TOK_DOT TOK_DOT { @@ -812,7 +814,7 @@ package: AstNode* mod = extra->pushChild(std::make_unique(@$, AST_PACKAGE)); extra->current_ast_mod = mod; mod->str = *$4; - append_attr(mod, $1); + append_attr(mod, std::move($1)); } TOK_SEMICOL package_body TOK_ENDPACKAGE opt_label { extra->ast_stack.pop_back(); checkLabelsMatch(@9, "Package name", $4.get(), $9.get()); @@ -1114,28 +1116,28 @@ task_func_decl: attr TOK_DPI_FUNCTION TOK_ID TOK_ID { extra->current_function_or_task = extra->saveChild(std::make_unique(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@3, *$3), AstNode::mkconst_str(@4, *$4))); extra->current_function_or_task->str = *$4; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); } opt_dpi_function_args TOK_SEMICOL { extra->current_function_or_task = nullptr; } | attr TOK_DPI_FUNCTION TOK_ID TOK_EQ TOK_ID TOK_ID { extra->current_function_or_task = extra->saveChild(std::make_unique(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@5, *$5), AstNode::mkconst_str(@3, *$3))); extra->current_function_or_task->str = *$6; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); } opt_dpi_function_args TOK_SEMICOL { extra->current_function_or_task = nullptr; } | attr TOK_DPI_FUNCTION TOK_ID TOK_COL TOK_ID TOK_EQ TOK_ID TOK_ID { extra->current_function_or_task = extra->saveChild(std::make_unique(@$, AST_DPI_FUNCTION, AstNode::mkconst_str(@7, *$7), AstNode::mkconst_str(location_range(@3, @5), *$3 + ":" + RTLIL::unescape_id(*$5)))); extra->current_function_or_task->str = *$8; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); } opt_dpi_function_args TOK_SEMICOL { extra->current_function_or_task = nullptr; } | attr TOK_TASK opt_automatic TOK_ID { extra->current_function_or_task = extra->pushChild(std::make_unique(@$, AST_TASK)); extra->current_function_or_task->str = *$4; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); extra->current_function_or_task_port_id = 1; } task_func_args_opt TOK_SEMICOL task_func_body TOK_ENDTASK { extra->current_function_or_task = nullptr; @@ -1149,7 +1151,7 @@ task_func_decl: // function like a task. extra->current_function_or_task = extra->pushChild(std::make_unique(@$, AST_TASK)); extra->current_function_or_task->str = *$5; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); extra->current_function_or_task_port_id = 1; } task_func_args_opt TOK_SEMICOL task_func_body TOK_ENDFUNCTION { extra->current_function_or_task = nullptr; @@ -1158,7 +1160,7 @@ task_func_decl: attr TOK_FUNCTION opt_automatic func_return_type TOK_ID { extra->current_function_or_task = extra->pushChild(std::make_unique(@$, AST_FUNCTION)); extra->current_function_or_task->str = *$5; - append_attr(extra->current_function_or_task, $1); + append_attr(extra->current_function_or_task, std::move($1)); auto outreg = std::make_unique(@$, AST_WIRE); outreg->str = *$5; outreg->is_signed = false; @@ -1240,7 +1242,7 @@ task_func_args_opt: (void)extra->astbuf1.reset(); if (extra->astbuf2 != nullptr) (void)extra->astbuf2.reset(); - free_attr(extra->albuf); + extra->albuf.reset(); } TOK_RPAREN; task_func_args: @@ -1256,9 +1258,9 @@ task_func_port: (void)extra->astbuf1.reset(); if (extra->astbuf2 != nullptr) (void)extra->astbuf2.reset(); - free_attr(extra->albuf); + extra->albuf.reset(); } - extra->albuf = $1; + extra->albuf = std::move($1); extra->astbuf1 = std::move($2); extra->astbuf2 = checkRange(extra->astbuf1.get(), std::move($3)); if (!extra->astbuf1->is_input && !extra->astbuf1->is_output) { @@ -1272,7 +1274,7 @@ task_func_port: if (!extra->astbuf1) { if (!mode->sv) err_at_loc(@$, "task/function argument direction missing"); - extra->albuf = new dict>; + extra->albuf = std::make_unique>>(); extra->astbuf1 = std::make_unique(@$, AST_WIRE); extra->current_wire_rand = false; extra->current_wire_const = false; @@ -1601,23 +1603,23 @@ state_dependent_path_declaration: module_path_expression: module_path_primary // Flatten out unary_operator to avoid shift/reduce conflict - | TOK_EXCL attr module_path_primary { free_attr($2); } - | TOK_TILDE attr module_path_primary { free_attr($2); } - | TOK_AMP attr module_path_primary { free_attr($2); } - | OP_NAND attr module_path_primary { free_attr($2); } - | TOK_PIPE attr module_path_primary { free_attr($2); } - | OP_NOR attr module_path_primary { free_attr($2); } - | TOK_CARET attr module_path_primary { free_attr($2); } - | OP_XNOR attr module_path_primary { free_attr($2); } + | TOK_EXCL attr module_path_primary + | TOK_TILDE attr module_path_primary + | TOK_AMP attr module_path_primary + | OP_NAND attr module_path_primary + | TOK_PIPE attr module_path_primary + | OP_NOR attr module_path_primary + | TOK_CARET attr module_path_primary + | OP_XNOR attr module_path_primary // Flatten out binary_operator to avoid shift/reduce conflict - | module_path_expression OP_EQ attr module_path_expression { free_attr($3); } - | module_path_expression OP_NE attr module_path_expression { free_attr($3); } - | module_path_expression OP_LAND attr module_path_expression { free_attr($3); } - | module_path_expression OP_LOR attr module_path_expression { free_attr($3); } - | module_path_expression TOK_AMP attr module_path_expression { free_attr($3); } - | module_path_expression TOK_PIPE attr module_path_expression { free_attr($3); } - | module_path_expression TOK_CARET attr module_path_expression { free_attr($3); } - | module_path_expression OP_XNOR attr module_path_expression { free_attr($3); } + | module_path_expression OP_EQ attr module_path_expression + | module_path_expression OP_NE attr module_path_expression + | module_path_expression OP_LAND attr module_path_expression + | module_path_expression OP_LOR attr module_path_expression + | module_path_expression TOK_AMP attr module_path_expression + | module_path_expression TOK_PIPE attr module_path_expression + | module_path_expression TOK_CARET attr module_path_expression + | module_path_expression OP_XNOR attr module_path_expression // | module_path_conditional_expression ; @@ -1760,7 +1762,7 @@ param_decl: attr TOK_PARAMETER { extra->astbuf1 = std::make_unique(@$, AST_PARAMETER); extra->astbuf1->children.push_back(AstNode::mkconst_int(@$, 0, true)); - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); } param_type param_decl_list TOK_SEMICOL { (void)extra->astbuf1.reset(); }; @@ -1769,7 +1771,7 @@ localparam_decl: attr TOK_LOCALPARAM { extra->astbuf1 = std::make_unique(@$, AST_LOCALPARAM); extra->astbuf1->children.push_back(AstNode::mkconst_int(@$, 0, true)); - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); } param_type param_decl_list TOK_SEMICOL { (void)extra->astbuf1.reset(); }; @@ -1925,7 +1927,7 @@ enum_decl: enum_type enum_var_list TOK_SEMICOL { } struct_decl: attr struct_type { - append_attr(extra->astbuf2.get(), $1); + append_attr(extra->astbuf2.get(), std::move($1)); } struct_var_list TOK_SEMICOL { (void)extra->astbuf2.reset(); } @@ -2031,26 +2033,26 @@ struct_var: wire_decl: attr wire_type range_or_multirange { - extra->albuf = $1; + extra->albuf = std::move($1); extra->astbuf1 = std::move($2); extra->astbuf2 = checkRange(extra->astbuf1.get(), std::move($3)); } delay wire_name_list { (void)extra->astbuf1.reset(); if (extra->astbuf2 != nullptr) (void)extra->astbuf2.reset(); - free_attr(extra->albuf); + extra->albuf.reset(); } TOK_SEMICOL | attr TOK_SUPPLY0 TOK_ID { extra->ast_stack.back()->children.push_back(std::make_unique(@$, AST_WIRE)); extra->ast_stack.back()->children.back()->str = *$3; - append_attr(extra->ast_stack.back()->children.back().get(), $1); + append_attr(extra->ast_stack.back()->children.back().get(), std::move($1)); extra->ast_stack.back()->children.push_back(std::make_unique(@$, AST_ASSIGN, std::make_unique(@$, AST_IDENTIFIER), AstNode::mkconst_int(@$, 0, false, 1))); extra->ast_stack.back()->children.back()->children[0]->str = *$3; } opt_supply_wires TOK_SEMICOL | attr TOK_SUPPLY1 TOK_ID { extra->ast_stack.back()->children.push_back(std::make_unique(@$, AST_WIRE)); extra->ast_stack.back()->children.back()->str = *$3; - append_attr(extra->ast_stack.back()->children.back().get(), $1); + append_attr(extra->ast_stack.back()->children.back().get(), std::move($1)); extra->ast_stack.back()->children.push_back(std::make_unique(@$, AST_ASSIGN, std::make_unique(@$, AST_IDENTIFIER), AstNode::mkconst_int(@$, 1, false, 1))); extra->ast_stack.back()->children.back()->children[0]->str = *$3; } opt_supply_wires TOK_SEMICOL; @@ -2243,7 +2245,7 @@ enum_struct_type: cell_stmt: attr TOK_ID { extra->astbuf1 = std::make_unique(@$, AST_CELL); - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); extra->astbuf1->children.push_back(std::make_unique(@$, AST_CELLTYPE)); extra->astbuf1->children[0]->str = *$2; } cell_parameter_list_opt cell_list TOK_SEMICOL { @@ -2252,7 +2254,7 @@ cell_stmt: attr tok_prim_wrapper delay { extra->astbuf1 = std::make_unique(@$, AST_PRIMITIVE); extra->astbuf1->str = *$2; - append_attr(extra->astbuf1.get(), $1); + append_attr(extra->astbuf1.get(), std::move($1)); } prim_list TOK_SEMICOL { (void)extra->astbuf1.reset(); }; @@ -2378,26 +2380,22 @@ cell_port: attr { auto node = std::make_unique(@$, AST_ARGUMENT); extra->cell_hack->children.push_back(std::move(node)); - free_attr($1); } | attr expr { auto node = std::make_unique(@$, AST_ARGUMENT); node->children.push_back(std::move($2)); extra->cell_hack->children.push_back(std::move(node)); - free_attr($1); } | attr TOK_DOT TOK_ID TOK_LPAREN expr TOK_RPAREN { auto node = std::make_unique(@$, AST_ARGUMENT); node->str = *$3; node->children.push_back(std::move($5)); extra->cell_hack->children.push_back(std::move(node)); - free_attr($1); } | attr TOK_DOT TOK_ID TOK_LPAREN TOK_RPAREN { auto node = std::make_unique(@$, AST_ARGUMENT); node->str = *$3; extra->cell_hack->children.push_back(std::move(node)); - free_attr($1); } | attr TOK_DOT TOK_ID { auto node = std::make_unique(@$, AST_ARGUMENT); @@ -2405,13 +2403,11 @@ cell_port: node->children.push_back(std::make_unique(@$, AST_IDENTIFIER)); node->children.back()->str = *$3; extra->cell_hack->children.push_back(std::move(node)); - free_attr($1); } | attr TOK_WILDCARD_CONNECT { if (!mode->sv) err_at_loc(@2, "Wildcard port connections are only supported in SystemVerilog mode."); extra->cell_hack->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(@2, 1, false); - free_attr($1); }; always_comb_or_latch: @@ -2433,7 +2429,7 @@ always_or_always_ff: always_stmt: attr always_or_always_ff { AstNode* node = extra->pushChild(std::make_unique(@$, AST_ALWAYS)); - append_attr(node, $1); + append_attr(node, std::move($1)); if ($2) node->attributes[ID::always_ff] = AstNode::mkconst_int(@2, 1, false); } always_cond { @@ -2449,7 +2445,7 @@ always_stmt: } | attr always_comb_or_latch { AstNode* node = extra->pushChild(std::make_unique(@$, AST_ALWAYS)); - append_attr(node, $1); + append_attr(node, std::move($1)); if ($2) node->attributes[ID::always_latch] = AstNode::mkconst_int(@2, 1, false); else @@ -2461,7 +2457,7 @@ always_stmt: } | attr TOK_INITIAL { AstNode* node = extra->pushChild(std::make_unique(@$, AST_INITIAL)); - append_attr(node, $1); + append_attr(node, std::move($1)); (void)extra->pushChild(std::make_unique(@$, AST_BLOCK)); } behavioral_stmt { extra->ast_stack.pop_back(); @@ -2702,21 +2698,21 @@ simple_behavioral_stmt: attr lvalue TOK_EQ delay expr { AstNode* node = extra->saveChild(std::make_unique(@$, AST_ASSIGN_EQ, std::move($2), std::move($5))); SET_AST_NODE_LOC(node, @2, @5); - append_attr(node, $1); + append_attr(node, std::move($1)); } | attr lvalue attr inc_or_dec_op { - extra->addIncOrDecStmt($1, std::move($2), $3, $4, location_range(@1, @4)); + extra->addIncOrDecStmt(std::move($1), std::move($2), std::move($3), $4, location_range(@1, @4)); } | attr inc_or_dec_op attr lvalue { - extra->addIncOrDecStmt($1, std::move($4), $3, $2, location_range(@1, @4)); + extra->addIncOrDecStmt(std::move($1), std::move($4), std::move($3), $2, location_range(@1, @4)); } | attr lvalue OP_LE delay expr { AstNode* node = extra->saveChild(std::make_unique(@$, AST_ASSIGN_LE, std::move($2), std::move($5))); SET_AST_NODE_LOC(node, @2, @5); - append_attr(node, $1); + append_attr(node, std::move($1)); } | attr lvalue asgn_binop delay expr { - (void)extra->addAsgnBinopStmt($1, std::move($2), $3, std::move($5)); + (void)extra->addAsgnBinopStmt(std::move($1), std::move($2), $3, std::move($5)); }; asgn_binop: @@ -2790,13 +2786,11 @@ behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | simple_behavioral_stmt TOK_SEMICOL | - attr TOK_SEMICOL { - free_attr($1); - } | + attr TOK_SEMICOL | attr hierarchical_id { AstNode* node = extra->pushChild(std::make_unique(@$, AST_TCALL)); node->str = *$2; - append_attr(node, $1); + append_attr(node, std::move($1)); } opt_arg_list TOK_SEMICOL{ SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @5); extra->ast_stack.pop_back(); @@ -2804,7 +2798,7 @@ behavioral_stmt: attr TOK_MSG_TASKS { AstNode* node = extra->pushChild(std::make_unique(@$, AST_TCALL)); node->str = *$2; - append_attr(node, $1); + append_attr(node, std::move($1)); } opt_arg_list TOK_SEMICOL{ SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @5); extra->ast_stack.pop_back(); @@ -2813,7 +2807,7 @@ behavioral_stmt: extra->enterTypeScope(); } opt_label { AstNode* node = extra->pushChild(std::make_unique(@$, AST_BLOCK)); - append_attr(node, $1); + append_attr(node, std::move($1)); if ($4 != nullptr) node->str = *$4; } behavioral_stmt_list TOK_END opt_label { @@ -2834,7 +2828,7 @@ behavioral_stmt: } | attr TOK_FOR TOK_LPAREN { AstNode* node = extra->pushChild(std::make_unique(@$, AST_FOR)); - append_attr(node, $1); + append_attr(node, std::move($1)); } for_initialization TOK_SEMICOL expr { extra->ast_stack.back()->children.push_back(std::move($7)); } TOK_SEMICOL simple_behavioral_stmt TOK_RPAREN { @@ -2848,7 +2842,7 @@ behavioral_stmt: } | attr TOK_WHILE TOK_LPAREN expr TOK_RPAREN { AstNode* node = extra->pushChild(std::make_unique(@$, AST_WHILE)); - append_attr(node, $1); + append_attr(node, std::move($1)); auto block_owned = std::make_unique(@$, AST_BLOCK); auto* block = block_owned.get(); extra->ast_stack.back()->children.push_back(std::move($4)); @@ -2861,7 +2855,7 @@ behavioral_stmt: } | attr TOK_REPEAT TOK_LPAREN expr TOK_RPAREN { AstNode* node = extra->pushChild(std::make_unique(@$, AST_REPEAT)); - append_attr(node, $1); + append_attr(node, std::move($1)); auto block_owned = std::make_unique(@$, AST_BLOCK); auto* block = block_owned.get(); extra->ast_stack.back()->children.push_back(std::move($4)); @@ -2896,11 +2890,9 @@ behavioral_stmt: // not parallel "else if": begin new construction node_owned = std::make_unique(@$, AST_CASE); node = node_owned.get(); - append_attr(node, $1); + append_attr(node, std::move($1)); node->children.push_back(node->get_bool_attribute(ID::parallel_case) ? AstNode::mkconst_int(@$, 1, false, 1) : expr->clone()); extra->ast_stack.back()->children.push_back(std::move(node_owned)); - } else { - free_attr($1); } auto block_owned = std::make_unique(@$, AST_BLOCK); auto* block = block_owned.get(); @@ -2921,7 +2913,7 @@ behavioral_stmt: } | case_attr case_type TOK_LPAREN expr TOK_RPAREN { AstNode* node = extra->pushChild(std::make_unique(@$, AST_CASE, std::move($4))); - append_attr(node, $1); + append_attr(node, std::move($1)); SET_AST_NODE_LOC(extra->ast_stack.back(), @4, @4); } opt_synopsys_attr case_body TOK_ENDCASE { SET_AST_NODE_LOC(extra->ast_stack.back(), @2, @9); @@ -2931,21 +2923,21 @@ behavioral_stmt: if_attr: attr { - $$ = $1; + $$ = std::move($1); } | attr TOK_UNIQUE0 { AstNode *context = extra->ast_stack.back(); if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) err_at_loc(@2, "unique0 keyword cannot be used for 'else if' branch."); (*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); } | attr TOK_PRIORITY { AstNode *context = extra->ast_stack.back(); if (context && context->type == AST_BLOCK && context->get_bool_attribute(ID::promoted_if)) err_at_loc(@2, "priority keyword cannot be used for 'else if' branch."); (*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); } | attr TOK_UNIQUE { AstNode *context = extra->ast_stack.back(); @@ -2953,25 +2945,25 @@ if_attr: err_at_loc(@2, "unique keyword cannot be used for 'else if' branch."); (*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false); (*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); }; case_attr: attr { - $$ = $1; + $$ = std::move($1); } | attr TOK_UNIQUE0 { (*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); } | attr TOK_PRIORITY { (*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); } | attr TOK_UNIQUE { (*$1)[ID::full_case] = AstNode::mkconst_int(@$, 1, false); (*$1)[ID::parallel_case] = AstNode::mkconst_int(@$, 1, false); - $$ = $1; + $$ = std::move($1); }; case_type: @@ -3139,9 +3131,7 @@ module_gen_body: gen_stmt_or_module_body_stmt: gen_stmt | module_body_stmt | - attr TOK_SEMICOL { - free_attr($1); - }; + attr TOK_SEMICOL; genvar_identifier: TOK_ID { @@ -3240,10 +3230,10 @@ expr: $$->children.push_back(std::move($4)); $$->children.push_back(std::move($6)); SET_AST_NODE_LOC($$.get(), @1, @$); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | inc_or_dec_op attr rvalue { - $$ = extra->addIncOrDecExpr(std::move($3), $2, $1, location_range(@1, @3), false, mode->sv); + $$ = extra->addIncOrDecExpr(std::move($3), std::move($2), $1, location_range(@1, @3), false, mode->sv); } | // TODO: Attributes are allowed in the middle here, but they create some // non-trivial conflicts that don't seem worth solving for now. @@ -3305,18 +3295,18 @@ basic_expr: node->str = *$1; extra->ast_stack.push_back(node); SET_AST_NODE_LOC(node, @1, @1); - append_attr(node, $2); + append_attr(node, std::move($2)); } TOK_LPAREN arg_list optional_comma TOK_RPAREN { $$.reset(extra->ast_stack.back()); extra->ast_stack.pop_back(); } | TOK_TO_SIGNED attr TOK_LPAREN expr TOK_RPAREN { $$ = std::make_unique(@$, AST_TO_SIGNED, std::move($4)); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | TOK_TO_UNSIGNED attr TOK_LPAREN expr TOK_RPAREN { $$ = std::make_unique(@$, AST_TO_UNSIGNED, std::move($4)); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | TOK_LPAREN expr TOK_RPAREN { $$ = std::move($2); @@ -3333,47 +3323,47 @@ basic_expr: TOK_TILDE attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_BIT_NOT, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | basic_expr TOK_AMP attr basic_expr { $$ = std::make_unique(@$, AST_BIT_AND, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_NAND attr basic_expr { $$ = std::make_unique(@$, AST_BIT_NOT, std::make_unique(@$, AST_BIT_AND, std::move($1), std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_PIPE attr basic_expr { $$ = std::make_unique(@$, AST_BIT_OR, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_NOR attr basic_expr { $$ = std::make_unique(@$, AST_BIT_NOT, std::make_unique(@$, AST_BIT_OR, std::move($1), std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_CARET attr basic_expr { $$ = std::make_unique(@$, AST_BIT_XOR, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_XNOR attr basic_expr { $$ = std::make_unique(@$, AST_BIT_XNOR, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | TOK_AMP attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_REDUCE_AND, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | OP_NAND attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_REDUCE_AND, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); $$ = std::make_unique(@$, AST_LOGIC_NOT, std::move($$)); } | TOK_PIPE attr basic_expr %prec UNARY_OPS { @@ -3384,134 +3374,134 @@ basic_expr: OP_NOR attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_REDUCE_OR, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); $$ = std::make_unique(@$, AST_LOGIC_NOT, std::move($$)); SET_AST_NODE_LOC($$.get(), @1, @3); } | TOK_CARET attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_REDUCE_XOR, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | OP_XNOR attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_REDUCE_XNOR, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | basic_expr OP_SHL attr basic_expr { $$ = std::make_unique(@$, AST_SHIFT_LEFT, std::move($1), std::make_unique(@$, AST_TO_UNSIGNED, std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_SHR attr basic_expr { $$ = std::make_unique(@$, AST_SHIFT_RIGHT, std::move($1), std::make_unique(@$, AST_TO_UNSIGNED, std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_SSHL attr basic_expr { $$ = std::make_unique(@$, AST_SHIFT_SLEFT, std::move($1), std::make_unique(@$, AST_TO_UNSIGNED, std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_SSHR attr basic_expr { $$ = std::make_unique(@$, AST_SHIFT_SRIGHT, std::move($1), std::make_unique(@$, AST_TO_UNSIGNED, std::move($4))); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_LT attr basic_expr { $$ = std::make_unique(@$, AST_LT, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_LE attr basic_expr { $$ = std::make_unique(@$, AST_LE, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_EQ attr basic_expr { $$ = std::make_unique(@$, AST_EQ, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_NE attr basic_expr { $$ = std::make_unique(@$, AST_NE, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_EQX attr basic_expr { $$ = std::make_unique(@$, AST_EQX, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_NEX attr basic_expr { $$ = std::make_unique(@$, AST_NEX, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_GE attr basic_expr { $$ = std::make_unique(@$, AST_GE, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_GT attr basic_expr { $$ = std::make_unique(@$, AST_GT, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_PLUS attr basic_expr { $$ = std::make_unique(@$, AST_ADD, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_MINUS attr basic_expr { $$ = std::make_unique(@$, AST_SUB, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_ASTER attr basic_expr { $$ = std::make_unique(@$, AST_MUL, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_SLASH attr basic_expr { $$ = std::make_unique(@$, AST_DIV, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr TOK_PERC attr basic_expr { $$ = std::make_unique(@$, AST_MOD, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_POW attr basic_expr { $$ = std::make_unique(@$, AST_POW, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | TOK_PLUS attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_POS, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | TOK_MINUS attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_NEG, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | basic_expr OP_LAND attr basic_expr { $$ = std::make_unique(@$, AST_LOGIC_AND, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | basic_expr OP_LOR attr basic_expr { $$ = std::make_unique(@$, AST_LOGIC_OR, std::move($1), std::move($4)); SET_AST_NODE_LOC($$.get(), @1, @4); - append_attr($$.get(), $3); + append_attr($$.get(), std::move($3)); } | TOK_EXCL attr basic_expr %prec UNARY_OPS { $$ = std::make_unique(@$, AST_LOGIC_NOT, std::move($3)); SET_AST_NODE_LOC($$.get(), @1, @3); - append_attr($$.get(), $2); + append_attr($$.get(), std::move($2)); } | TOK_SIGNED OP_CAST TOK_LPAREN expr TOK_RPAREN { if (!mode->sv) From c7017f7f79899a3372678bea829fb92764f370e0 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 3 Jul 2025 23:47:25 +0000 Subject: [PATCH 052/188] Remove `log_str()` functions and convert their `log_signal()` users to return `std::string` This is a small but easy step towards removing the `log_id_cache`. See issue #5210. --- kernel/drivertools.cc | 30 +++++++++++++++--------------- kernel/drivertools.h | 11 ++++++----- kernel/functional.cc | 4 ++-- kernel/log.cc | 10 ---------- kernel/log.h | 2 -- 5 files changed, 23 insertions(+), 34 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index b8905d68c..6290f4470 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -865,41 +865,41 @@ DriveSpec DriverMap::operator()(DriveSpec spec) return result; } -const char *log_signal(DriveChunkWire const &chunk) +std::string log_signal(DriveChunkWire const &chunk) { const char *id = log_id(chunk.wire->name); if (chunk.is_whole()) return id; if (chunk.width == 1) - return log_str(stringf("%s [%d]", id, chunk.offset)); - return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset)); + return stringf("%s [%d]", id, chunk.offset); + return stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset); } -const char *log_signal(DriveChunkPort const &chunk) +std::string log_signal(DriveChunkPort const &chunk) { const char *cell_id = log_id(chunk.cell->name); const char *port_id = log_id(chunk.port); if (chunk.is_whole()) - return log_str(stringf("%s <%s>", cell_id, port_id)); + return stringf("%s <%s>", cell_id, port_id); if (chunk.width == 1) - return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset)); - return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset)); + return stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset); + return stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset); } -const char *log_signal(DriveChunkMarker const &chunk) +std::string log_signal(DriveChunkMarker const &chunk) { if (chunk.width == 1) - return log_str(stringf(" [%d]", chunk.marker, chunk.offset)); - return log_str(stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset)); + return stringf(" [%d]", chunk.marker, chunk.offset); + return stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset); } -const char *log_signal(DriveChunk const &chunk) +std::string log_signal(DriveChunk const &chunk) { switch (chunk.type()) { case DriveType::NONE: - return log_str(stringf("", chunk.size())); + return stringf("", chunk.size()); case DriveType::CONSTANT: return log_const(chunk.constant()); case DriveType::WIRE: @@ -917,14 +917,14 @@ const char *log_signal(DriveChunk const &chunk) str += log_signal(single); } str += ">"; - return log_str(str); + return str; } default: log_abort(); } } -const char *log_signal(DriveSpec const &spec) +std::string log_signal(DriveSpec const &spec) { auto &chunks = spec.chunks(); if (chunks.empty()) @@ -943,7 +943,7 @@ const char *log_signal(DriveSpec const &spec) } str += " }"; - return log_str(str); + return str; } YOSYS_NAMESPACE_END diff --git a/kernel/drivertools.h b/kernel/drivertools.h index d46217da5..ba7b2aa84 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -20,6 +20,7 @@ #ifndef DRIVERTOOLS_H #define DRIVERTOOLS_H +#include #include #include "kernel/rtlil.h" @@ -39,11 +40,11 @@ struct DriveChunk; struct DriveSpec; -const char *log_signal(DriveChunkWire const &chunk); -const char *log_signal(DriveChunkPort const &chunk); -const char *log_signal(DriveChunkMarker const &chunk); -const char *log_signal(DriveChunk const &chunk); -const char *log_signal(DriveSpec const &chunk); +std::string log_signal(DriveChunkWire const &chunk); +std::string log_signal(DriveChunkPort const &chunk); +std::string log_signal(DriveChunkMarker const &chunk); +std::string log_signal(DriveChunk const &chunk); +std::string log_signal(DriveSpec const &chunk); enum class DriveType : unsigned char { diff --git a/kernel/functional.cc b/kernel/functional.cc index 211527926..66dc2e1eb 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -638,7 +638,7 @@ private: } } } - void undriven(const char *name) { + void undriven(const std::string& name) { log_error("The design contains an undriven signal %s. This is not supported by the functional backend. " "Call setundef with appropriate options to avoid this error.\n", name); } @@ -646,7 +646,7 @@ private: void check_undriven(DriveSpec const& spec, std::string const& name) { for(auto const &chunk : spec.chunks()) if(chunk.is_none()) - undriven(name.c_str()); + undriven(name); } public: void process_queue() diff --git a/kernel/log.cc b/kernel/log.cc index 0dd56a04f..a03f16350 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -621,16 +621,6 @@ const char *log_id(const RTLIL::IdString &str) return log_id_cache.back(); } -const char *log_str(const char *str) -{ - log_id_cache.push_back(strdup(str)); - return log_id_cache.back(); -} - -const char *log_str(std::string const &str) { - return log_str(str.c_str()); -} - void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; diff --git a/kernel/log.h b/kernel/log.h index 5143524bf..1f32e8185 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -256,8 +256,6 @@ void log_check_expected(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(const RTLIL::IdString &id); -const char *log_str(const char *str); -const char *log_str(std::string const &str); template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { if (nullstr && obj == nullptr) From bc24947a849e9e5068c04cc663eb3379c0995523 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 11 Sep 2025 16:50:23 +0200 Subject: [PATCH 053/188] tests: replace CC and gcc with CXX and g++ --- tests/cxxrtl/run-test.sh | 4 ++-- tests/fmt/run-test.sh | 4 ++-- tests/tools/autotest.sh | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh index ee299fc82..4b542e180 100755 --- a/tests/cxxrtl/run-test.sh +++ b/tests/cxxrtl/run-test.sh @@ -5,7 +5,7 @@ set -ex run_subtest () { local subtest=$1; shift - ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ + ${CXX:-g++} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ ./cxxrtl-test-${subtest} } @@ -14,4 +14,4 @@ run_subtest value_fuzz # Compile-only test. ../../yosys -p "read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc" -${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc +${CXX:-g++} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh index 998047f83..88ee6e238 100644 --- a/tests/fmt/run-test.sh +++ b/tests/fmt/run-test.sh @@ -51,7 +51,7 @@ test_cxxrtl () { local subtest=$1; shift ../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc" - ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ + ${CXX:-g++} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ ./yosys-${subtest} 2>yosys-${subtest}.log iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v ./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log @@ -69,7 +69,7 @@ diff iverilog-always_full.log iverilog-always_full-1.log ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" -${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ +${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ ./yosys-display_lm_cc >yosys-display_lm_cc.log for log in yosys-display_lm.log yosys-display_lm_cc.log; do grep "^%l: \\\\bot\$" "$log" diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index f96eb8d71..47b06d575 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -26,7 +26,7 @@ xfirrtl="../xfirrtl" abcprog="$toolsdir/../../yosys-abc" if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then - ( set -ex; ${CC:-gcc} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1 + ( set -ex; ${CXX:-g++} -Wall -o "$toolsdir/cmp_tbdata" "$toolsdir/cmp_tbdata.c"; ) || exit 1 fi while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do From e0ae7b7af44a45795f68990cd16a85bf03770d2a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 11 Sep 2025 05:25:26 +0000 Subject: [PATCH 054/188] Remove .c_str() calls from log()/log_error() There are some leftovers, but this is an easy regex-based approach that removes most of them. --- backends/aiger/aiger.cc | 4 +- backends/aiger/xaiger.cc | 2 +- backends/blif/blif.cc | 2 +- backends/btor/btor.cc | 4 +- backends/edif/edif.cc | 2 +- backends/firrtl/firrtl.cc | 6 +- backends/functional/cxx.cc | 2 +- backends/functional/smtlib.cc | 2 +- backends/functional/smtlib_rosette.cc | 2 +- backends/functional/test_generic.cc | 2 +- backends/intersynth/intersynth.cc | 4 +- backends/jny/jny.cc | 4 +- backends/json/json.cc | 4 +- backends/rtlil/rtlil_backend.cc | 6 +- backends/simplec/simplec.cc | 14 +- backends/smt2/smt2.cc | 8 +- backends/smv/smv.cc | 4 +- backends/spice/spice.cc | 2 +- backends/verilog/verilog_backend.cc | 6 +- .../source/code_examples/extensions/my_cmd.cc | 2 +- docs/source/code_examples/functional/dummy.cc | 2 +- docs/source/yosys_internals/hashing.rst | 6 +- examples/cxx-api/scopeinfo_example.cc | 4 +- frontends/aiger/aigerparse.cc | 2 +- frontends/aiger2/xaiger.cc | 4 +- frontends/ast/ast.cc | 24 ++-- frontends/ast/dpicall.cc | 20 +-- frontends/ast/genrtlil.cc | 2 +- frontends/ast/simplify.cc | 26 ++-- frontends/blif/blifparse.cc | 2 +- frontends/json/jsonparse.cc | 4 +- frontends/liberty/liberty.cc | 12 +- frontends/rpc/rpc_frontend.cc | 20 +-- frontends/rtlil/rtlil_frontend.cc | 2 +- frontends/verific/verific.cc | 24 ++-- frontends/verific/verificsva.cc | 2 +- frontends/verilog/preproc.cc | 8 +- frontends/verilog/verilog_frontend.cc | 2 +- frontends/verilog/verilog_parser.y | 6 +- kernel/driver.cc | 10 +- kernel/fstdata.cc | 4 +- kernel/functional.cc | 12 +- kernel/functional.h | 6 +- kernel/gzip.cc | 2 +- kernel/log.cc | 16 +-- kernel/log.h | 2 +- kernel/log_help.cc | 6 +- kernel/register.cc | 64 ++++----- kernel/rtlil.cc | 2 +- kernel/sexpr.cc | 2 +- kernel/tclapi.cc | 2 +- kernel/yosys.cc | 18 +-- kernel/yw.cc | 30 ++--- passes/cmds/abstract.cc | 2 +- passes/cmds/add.cc | 14 +- passes/cmds/cover.cc | 2 +- passes/cmds/edgetypes.cc | 2 +- passes/cmds/exec.cc | 2 +- passes/cmds/glift.cc | 2 +- passes/cmds/internal_stats.cc | 8 +- passes/cmds/linecoverage.cc | 4 +- passes/cmds/logcmd.cc | 2 +- passes/cmds/logger.cc | 8 +- passes/cmds/plugin.cc | 6 +- passes/cmds/portarcs.cc | 2 +- passes/cmds/portlist.cc | 2 +- passes/cmds/printattrs.cc | 10 +- passes/cmds/rename.cc | 6 +- passes/cmds/scc.cc | 2 +- passes/cmds/scratchpad.cc | 18 +-- passes/cmds/select.cc | 16 +-- passes/cmds/setundef.cc | 6 +- passes/cmds/show.cc | 12 +- passes/cmds/splice.cc | 2 +- passes/cmds/stat.cc | 74 +++++------ passes/cmds/timeest.cc | 4 +- passes/cmds/viz.cc | 8 +- passes/cmds/wrapcell.cc | 4 +- passes/fsm/fsm_expand.cc | 4 +- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 6 +- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_opt.cc | 2 +- passes/fsm/fsm_recode.cc | 16 +-- passes/fsm/fsmdata.h | 2 +- passes/hierarchy/hierarchy.cc | 12 +- passes/hierarchy/submod.cc | 16 +-- passes/memory/memlib.cc | 124 +++++++++--------- passes/memory/memory_bram.cc | 4 +- passes/memory/memory_dff.cc | 4 +- passes/memory/memory_libmap.cc | 10 +- passes/memory/memory_map.cc | 2 +- passes/memory/memory_share.cc | 4 +- passes/opt/opt_clean.cc | 2 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_merge.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_reduce.cc | 14 +- passes/opt/rmports.cc | 10 +- passes/pmgen/pmgen.py | 4 +- passes/proc/proc_arst.cc | 4 +- passes/proc/proc_clean.cc | 4 +- passes/proc/proc_dff.cc | 6 +- passes/proc/proc_dlatch.cc | 2 +- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 2 +- passes/sat/eval.cc | 32 ++--- passes/sat/fminit.cc | 10 +- passes/sat/freduce.cc | 4 +- passes/sat/mutate.cc | 8 +- passes/sat/qbfsat.cc | 22 ++-- passes/sat/sat.cc | 12 +- passes/sat/sim.cc | 60 ++++----- passes/sat/synthprop.cc | 2 +- passes/techmap/abc.cc | 42 +++--- passes/techmap/abc9.cc | 6 +- passes/techmap/abc9_exe.cc | 14 +- passes/techmap/abc9_ops.cc | 4 +- passes/techmap/attrmap.cc | 4 +- passes/techmap/clkbufmap.cc | 4 +- passes/techmap/clockgate.cc | 6 +- passes/techmap/dfflegalize.cc | 6 +- passes/techmap/dfflibmap.cc | 10 +- passes/techmap/extract.cc | 16 +-- passes/techmap/extract_counter.cc | 6 +- passes/techmap/extract_reduce.cc | 4 +- passes/techmap/extractinv.cc | 2 +- passes/techmap/flowmap.cc | 2 +- passes/techmap/iopadmap.cc | 6 +- passes/techmap/libcache.cc | 4 +- passes/techmap/libparse.cc | 6 +- passes/techmap/libparse.h | 2 +- passes/techmap/techmap.cc | 10 +- passes/tests/raise_error.cc | 2 +- passes/tests/test_autotb.cc | 2 +- passes/tests/test_cell.cc | 2 +- techlibs/coolrunner2/coolrunner2_fixup.cc | 14 +- techlibs/ice40/ice40_braminit.cc | 4 +- techlibs/microchip/microchip_dffopt.cc | 2 +- techlibs/xilinx/xilinx_dffopt.cc | 2 +- 140 files changed, 623 insertions(+), 623 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index e8b8e32ce..95f4c19e2 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -1040,7 +1040,7 @@ struct AigerBackend : public Backend { std::ofstream mapf; mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) - log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno)); writer.write_map(mapf, verbose_map, no_startoffset); } @@ -1051,7 +1051,7 @@ struct AigerBackend : public Backend { PrettyJson json; if (!json.write_to_file(yw_map_filename)) - log_error("Can't open file `%s' for writing: %s\n", yw_map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", yw_map_filename, strerror(errno)); writer.write_ywmap(json); } } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 97dec40e4..988bc558b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -788,7 +788,7 @@ struct XAigerBackend : public Backend { std::ofstream mapf; mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) - log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno)); writer.write_map(mapf); } } diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 1ce1ac955..ab7861802 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -674,7 +674,7 @@ struct BlifBackend : public Backend { } if (!top_module_name.empty()) - log_error("Can't find top module `%s'!\n", top_module_name.c_str()); + log_error("Can't find top module `%s'!\n", top_module_name); for (auto module : mod_list) BlifDumper::dump(*f, module, design, config); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index c2b831a44..3cbb5defc 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -246,7 +246,7 @@ struct BtorWorker string cell_list; for (auto c : cell_recursion_guard) cell_list += stringf("\n %s", log_id(c)); - log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str()); + log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list); } cell_recursion_guard.insert(cell); @@ -1489,7 +1489,7 @@ struct BtorWorker std::ofstream f; f.open(info_filename.c_str(), std::ofstream::trunc); if (f.fail()) - log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", info_filename, strerror(errno)); for (auto &it : info_lines) f << it; f.close(); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index cda017059..83d0afaf3 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -519,7 +519,7 @@ struct EdifBackend : public Backend { continue; } else { for (auto &ref : it.second) - log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str()); + log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first); log_abort(); } } diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index cda3d4618..e54b46e63 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -347,7 +347,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f) auto modInstance = design->module(cell->type); // Ensure that we actually have a module instance if (modInstance == nullptr) { - log_error("Unknown cell type %s\n", cell->type.c_str()); + log_error("Unknown cell type %s\n", cell->type); return; } @@ -505,14 +505,14 @@ struct FirrtlWorker sinkExpr = firstName; break; default: - log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir); + log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type, log_signal(it->second), dir); break; } // Check for subfield assignment. std::string bitsString = "bits("; if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) { if (sinkSig == nullptr) - log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str()); + log_error("Unknown subfield %s.%s\n", cell_type, sinkExpr); // Don't generate the assignment here. // Add the source and sink to the "reverse_wire_map" and we'll output the assignment // as part of the coalesced subfield assignments for this wire. diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 1f677120a..7f4ad1ea7 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -268,7 +268,7 @@ struct FunctionalCxxBackend : public Backend extra_args(f, filename, args, argidx, design); for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); printCxx(*f, filename, module); } } diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 3eacf407c..1504c8fba 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -285,7 +285,7 @@ struct FunctionalSmtBackend : public Backend { extra_args(f, filename, args, argidx, design); for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); SmtModule smt(module); smt.write(*f); } diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index c9e737d19..8abfe3e41 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -307,7 +307,7 @@ struct FunctionalSmtrBackend : public Backend { } for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); SmtrModule smtr(module); smtr.write(*f); } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 42d6c2b95..a0474ea2b 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -143,7 +143,7 @@ struct FunctionalTestGeneric : public Pass */ for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); auto fir = Functional::IR::from_module(module); for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 4c098e019..78eab17da 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -100,13 +100,13 @@ struct IntersynthBackend : public Backend { } extra_args(f, filename, args, argidx); - log("Output filename: %s\n", filename.c_str()); + log("Output filename: %s\n", filename); for (auto filename : libfiles) { std::ifstream f; f.open(filename.c_str()); if (f.fail()) - log_error("Can't open lib file `%s'.\n", filename.c_str()); + log_error("Can't open lib file `%s'.\n", filename); RTLIL::Design *lib = new RTLIL::Design; Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 001492e40..ee0c0d14c 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -553,7 +553,7 @@ struct JnyPass : public Pass { ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; invk << filename; @@ -568,7 +568,7 @@ struct JnyPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } diff --git a/backends/json/json.cc b/backends/json/json.cc index f7b80d53d..b04083622 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -701,7 +701,7 @@ struct JsonPass : public Pass { ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } else { @@ -714,7 +714,7 @@ struct JsonPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } } JsonPass; diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 215e0d366..cb17432b1 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -458,7 +458,7 @@ struct RTLILBackend : public Backend { design->sort(); - log("Output filename: %s\n", filename.c_str()); + log("Output filename: %s\n", filename); *f << stringf("# Generated by %s\n", yosys_maybe_version()); RTLIL_BACKEND::dump_design(*f, design, selected, true, false); @@ -531,7 +531,7 @@ struct DumpPass : public Pass { ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } else { @@ -543,7 +543,7 @@ struct DumpPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } } DumpPass; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 1ab586e43..ed981f961 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -504,7 +504,7 @@ struct SimplecWorker while (work->dirty) { if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty())) - log(" In %s:\n", work->log_prefix.c_str()); + log(" In %s:\n", work->log_prefix); while (!work->dirty_bits.empty() || !work->dirty_cells.empty()) { @@ -517,7 +517,7 @@ struct SimplecWorker if (chunk.wire == nullptr) continue; if (verbose) - log(" Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset); + log(" Propagating %s.%s[%d:%d].\n", work->log_prefix, log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset); funct_declarations.push_back(stringf(" // Updated signal in %s: %s", work->log_prefix, log_signal(chunk))); } @@ -539,7 +539,7 @@ struct SimplecWorker work->parent->set_dirty(parent_bit); if (verbose) - log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset, + log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset, work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset); } @@ -556,11 +556,11 @@ struct SimplecWorker child->set_dirty(child_bit); if (verbose) - log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset, + log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset, work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset); } else { if (verbose) - log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)), + log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix, log_id(std::get<0>(port)), work->log_prefix.c_str(), log_id(bit.wire), bit.offset); work->set_dirty(std::get<0>(port)); } @@ -579,7 +579,7 @@ struct SimplecWorker string hiername = work->log_prefix + "." + log_id(cell); if (verbose) - log(" Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells)); + log(" Evaluating %s (%s, best of %d).\n", hiername, log_id(cell->type), GetSize(work->dirty_cells)); if (activated_cells.count(hiername)) reactivated_cells.insert(hiername); @@ -630,7 +630,7 @@ struct SimplecWorker void make_func(HierDirtyFlags *work, const string &func_name, const vector &preamble) { - log("Generating function %s():\n", func_name.c_str()); + log("Generating function %s():\n", func_name); activated_cells.clear(); reactivated_cells.clear(); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 089e73715..1d3757463 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -130,7 +130,7 @@ struct Smt2Worker for (auto &mem : memories) { if (is_smtlib2_module) - log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid.c_str()); + log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid); mem.narrow(); mem_dict[mem.memid] = &mem; @@ -620,11 +620,11 @@ struct Smt2Worker decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr)); if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str().c_str()); + log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str()); } else if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::minimize)){ decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str().c_str()); + log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str()); } bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst)); @@ -1776,7 +1776,7 @@ struct Smt2Backend : public Backend { if (args[argidx] == "-tpl" && argidx+1 < args.size()) { template_f.open(args[++argidx]); if (template_f.fail()) - log_error("Can't open template file `%s'.\n", args[argidx].c_str()); + log_error("Can't open template file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-bv" || args[argidx] == "-mem") { diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 55eadca00..a6ccbf27f 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -756,7 +756,7 @@ struct SmvBackend : public Backend { if (args[argidx] == "-tpl" && argidx+1 < args.size()) { template_f.open(args[++argidx]); if (template_f.fail()) - log_error("Can't open template file `%s'.\n", args[argidx].c_str()); + log_error("Can't open template file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-verbose") { @@ -795,7 +795,7 @@ struct SmvBackend : public Backend { modules.erase(module); if (module == nullptr) - log_error("Module '%s' not found.\n", stmt[1].c_str()); + log_error("Module '%s' not found.\n", stmt[1]); *f << stringf("-- SMV description generated by %s\n", yosys_maybe_version()); diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 573093ff7..16458d647 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -258,7 +258,7 @@ struct SpiceBackend : public Backend { if (!top_module_name.empty()) { if (top_module == NULL) - log_error("Can't find top module `%s'!\n", top_module_name.c_str()); + log_error("Can't find top module `%s'!\n", top_module_name); print_spice_module(*f, top_module, design, neg, pos, buf, ncpf, big_endian, use_inames); *f << stringf("\n"); } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b1ed2b1f0..71969f177 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -153,7 +153,7 @@ void reset_auto_counter(RTLIL::Module *module) if (verbose) for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it) - log(" renaming `%s' to `%s_%0*d_'.\n", it->first.c_str(), auto_prefix.c_str(), auto_name_digits, auto_name_offset + it->second); + log(" renaming `%s' to `%s_%0*d_'.\n", it->first, auto_prefix, auto_name_digits, auto_name_offset + it->second); } std::string next_auto_id() @@ -494,7 +494,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::ofstream extmem_f(extmem_filename, std::ofstream::trunc); if (extmem_f.fail()) - log_error("Can't open file `%s' for writing: %s\n", extmem_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", extmem_filename, strerror(errno)); else { Const data = mem.get_init_data(); @@ -2632,7 +2632,7 @@ struct VerilogBackend : public Backend { log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name)); continue; } - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); module->sort(); dump_module(*f, "", module); } diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc index e6660469c..d52268b4a 100644 --- a/docs/source/code_examples/extensions/my_cmd.cc +++ b/docs/source/code_examples/extensions/my_cmd.cc @@ -10,7 +10,7 @@ struct MyPass : public Pass { { log("Arguments to my_cmd:\n"); for (auto &arg : args) - log(" %s\n", arg.c_str()); + log(" %s\n", arg); log("Modules in current design:\n"); for (auto mod : design->modules()) diff --git a/docs/source/code_examples/functional/dummy.cc b/docs/source/code_examples/functional/dummy.cc index 3d84b84ba..42b05b339 100644 --- a/docs/source/code_examples/functional/dummy.cc +++ b/docs/source/code_examples/functional/dummy.cc @@ -16,7 +16,7 @@ struct FunctionalDummyBackend : public Backend { for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); // convert module to FunctionalIR auto ir = Functional::IR::from_module(module); diff --git a/docs/source/yosys_internals/hashing.rst b/docs/source/yosys_internals/hashing.rst index b9608d99e..1993e617a 100644 --- a/docs/source/yosys_internals/hashing.rst +++ b/docs/source/yosys_internals/hashing.rst @@ -45,9 +45,9 @@ creates a bijective map from ``K`` to the integers. For example: log("%d\n", si("world")); // will print 43 log("%d\n", si.at("world")); // will print 43 log("%d\n", si.at("dummy")); // will throw exception - log("%s\n", si[42].c_str())); // will print hello - log("%s\n", si[43].c_str())); // will print world - log("%s\n", si[44].c_str())); // will throw exception + log("%s\n", si[42])); // will print hello + log("%s\n", si[43])); // will print world + log("%s\n", si[44])); // will throw exception It is not possible to remove elements from an idict. diff --git a/examples/cxx-api/scopeinfo_example.cc b/examples/cxx-api/scopeinfo_example.cc index 0882ba804..fd5d2a781 100644 --- a/examples/cxx-api/scopeinfo_example.cc +++ b/examples/cxx-api/scopeinfo_example.cc @@ -77,9 +77,9 @@ struct ScopeinfoExamplePass : public Pass { continue; } - log("%s %s\n", wire_scope.first.path_str().c_str(), log_id(wire_scope.second)); + log("%s %s\n", wire_scope.first.path_str(), log_id(wire_scope.second)); for (auto src : index.sources(wire)) - log(" - %s\n", src.c_str()); + log(" - %s\n", src); } } } diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index c5d9bc70b..db4cb12ba 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -909,7 +909,7 @@ void AigerReader::post_process() module->rename(cell, escaped_s); } else - log_error("Symbol type '%s' not recognised.\n", type.c_str()); + log_error("Symbol type '%s' not recognised.\n", type); } } diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 616bec9e7..d983f8c41 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -91,7 +91,7 @@ struct Xaiger2Frontend : public Frontend { std::ifstream map_file; map_file.open(map_filename); if (!map_file) - log_error("Failed to open map file '%s'\n", map_filename.c_str()); + log_error("Failed to open map file '%s'\n", map_filename); unsigned int M, I, L, O, A; std::string header; @@ -388,7 +388,7 @@ struct Xaiger2Frontend : public Frontend { if (f->eof()) break; log_assert(!f->fail()); - log("input file: %s\n", scratch.c_str()); + log("input file: %s\n", scratch); } log_debug("co_counter=%d\n", co_counter); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 313161fc3..2f93ea198 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1108,9 +1108,9 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); if (defer) - log("Storing AST representation for module `%s'.\n", ast->str.c_str()); + log("Storing AST representation for module `%s'.\n", ast->str); else if (!quiet) { - log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str()); + log("Generating RTLIL representation for module `%s'.\n", ast->str); } AstModule *module = new AstModule; @@ -1411,7 +1411,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump for (auto& n : design->verilog_packages) { for (auto &o : n->children) { auto cloned_node = o->clone(); - // log("cloned node %s\n", type2str(cloned_node->type).c_str()); + // log("cloned node %s\n", type2str(cloned_node->type)); if (cloned_node->type == AST_ENUM) { for (auto &e : cloned_node->children) { log_assert(e->type == AST_ENUM_ITEM); @@ -1432,7 +1432,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump for (const auto& node : child->children) if (node->type == AST_PARAMETER && param_has_no_default(node.get())) { - log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str()); + log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str); defer_local = true; break; } @@ -1507,7 +1507,7 @@ std::pair AST::split_modport_from_type(std::string name interface_modport = seglist[1]; } else { // Erroneous port type - log_error("More than two '.' in signal port type (%s)\n", name_type.c_str()); + log_error("More than two '.' in signal port type (%s)\n", name_type); } } return std::pair(interface_type, interface_modport); @@ -1720,7 +1720,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictset_bool_attribute(ID::is_interface); } else { - log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); + log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname); } } @@ -1731,7 +1731,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictmodule(modname)->check(); } else if (!quiet) { - log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); + log("Found cached RTLIL representation for module `%s'.\n", modname); } return modname; @@ -1799,14 +1799,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictstr); if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + log("Parameter %s = %s\n", child->str, log_signal(it->second)); named_parameters.emplace_back(child->str, it->second); continue; } it = parameters.find(stringf("$%d", para_counter)); if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second)); named_parameters.emplace_back(child->str, it->second); continue; } @@ -1839,13 +1839,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictstr); if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + log("Parameter %s = %s\n", child->str, log_signal(it->second)); goto rewrite_parameter; } it = parameters.find(stringf("$%d", para_counter)); if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second)); goto rewrite_parameter; } continue; diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index d76318739..4c2a7fac9 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -40,7 +40,7 @@ static ffi_fptr resolve_fn (std::string symbol_name) plugin_name = loaded_plugin_aliases.at(plugin_name); if (loaded_plugins.count(plugin_name) == 0) - log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name.c_str(), plugin_name.c_str()); + log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name, plugin_name); void *symbol = dlsym(loaded_plugins.at(plugin_name), real_symbol_name.c_str()); @@ -61,7 +61,7 @@ static ffi_fptr resolve_fn (std::string symbol_name) if (symbol != nullptr) return (ffi_fptr) symbol; - log_error("unable to resolve '%s'.\n", symbol_name.c_str()); + log_error("unable to resolve '%s'.\n", symbol_name); } std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector &argtypes, const std::vector> &args) @@ -74,32 +74,32 @@ std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string ffi_cif cif; int status; - log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str()); + log("Calling DPI function `%s' and returning `%s':\n", fname, rtype); log_assert(GetSize(args) == GetSize(argtypes)); for (int i = 0; i < GetSize(args); i++) { if (argtypes[i] == "real") { - log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed)); + log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed)); value_store[i].f64 = args[i]->asReal(args[i]->is_signed); values[i] = &value_store[i].f64; types[i] = &ffi_type_double; } else if (argtypes[i] == "shortreal") { - log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed)); + log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed)); value_store[i].f32 = args[i]->asReal(args[i]->is_signed); values[i] = &value_store[i].f32; types[i] = &ffi_type_double; } else if (argtypes[i] == "integer") { - log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed)); + log(" arg %d (%s): %lld\n", i, argtypes[i], (long long)args[i]->asInt(args[i]->is_signed)); value_store[i].i32 = args[i]->asInt(args[i]->is_signed); values[i] = &value_store[i].i32; types[i] = &ffi_type_sint32; } else if (argtypes[i] == "chandle") { - log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false)); + log(" arg %d (%s): %llx\n", i, argtypes[i], (unsigned long long)args[i]->asInt(false)); value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed); values[i] = &value_store[i].ptr; types[i] = &ffi_type_pointer; } else { - log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i); + log_error("invalid argtype '%s' for argument %d.\n", argtypes[i], i); } } @@ -116,7 +116,7 @@ std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string types[args.size()] = &ffi_type_pointer; values[args.size()] = &value_store[args.size()].ptr; } else { - log_error("invalid rtype '%s'.\n", rtype.c_str()); + log_error("invalid rtype '%s'.\n", rtype); } if ((status = ffi_prep_cif(&cif, FFI_DEFAULT_ABI, args.size(), types[args.size()], types.data())) != FFI_OK) @@ -155,7 +155,7 @@ YOSYS_NAMESPACE_BEGIN std::unique_ptr AST::dpi_call(AstSrcLocType, const std::string&, const std::string &fname, const std::vector&, const std::vector>&) { - log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str()); + log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname); } YOSYS_NAMESPACE_END diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 896ae9bdb..a30823e24 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator if (found_anyedge_syncs) { if (found_global_syncs) always->input_error("Found non-synthesizable event list!\n"); - log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str()); + log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string()); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bf72a770f..dee4d5854 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -180,10 +180,10 @@ void AstNode::annotateTypedEnums(AstNode *template_node) if (template_node->attributes.count(ID::enum_type)) { //get reference to enum node: std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str(); - // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type)); + // log("enum_type=%s (count=%lu)\n", enum_type, current_scope.count(enum_type)); // log("current scope:\n"); // for (auto &it : current_scope) - // log(" %s\n", it.first.c_str()); + // log(" %s\n", it.first); log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); @@ -911,7 +911,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin #if 0 log("-------------\n"); - log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this); + log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename, location.begin.line, type2str(type), this); log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n", int(const_fold), int(stage), int(width_hint), int(sign_hint)); // dumpAst(nullptr, "> "); @@ -963,7 +963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS)) goto verbose_activate; - // log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags)); + // log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags)); continue; verbose_activate: @@ -978,7 +978,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } silent_activate: - // log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags)); + // log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags)); mem2reg_set.insert(mem); } @@ -1063,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true); if (str.substr(0, 8) == "$display") fmt.append_literal("\n"); - log("%s", fmt.render().c_str()); + log("%s", fmt.render()); } return false; @@ -1499,7 +1499,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin break; case AST_ENUM: - //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); + //log("\nENUM %s: %d child %d\n", str, basic_prep, children[0]->basic_prep); if (!basic_prep) { for (auto& item_node : children) { while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false)) @@ -1590,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } default: - log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str()); + log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type)); } } @@ -2297,7 +2297,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; str = try_pop_module_prefix(); for (auto& node : current_scope_ast->children) { - //log("looking at mod scope child %s\n", type2str(node->type).c_str()); + //log("looking at mod scope child %s\n", type2str(node->type)); switch (node->type) { case AST_PARAMETER: case AST_LOCALPARAM: @@ -2308,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin case AST_FUNCTION: case AST_TASK: case AST_DPI_FUNCTION: - //log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str()); + //log("found child %s, %s\n", type2str(node->type), node->str); if (str == node->str) { - //log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str()); + //log("add %s, type %s to scope\n", str, type2str(node->type)); current_scope[node->str] = node.get(); } break; @@ -2319,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin for (auto& enum_node : node->children) { log_assert(enum_node->type==AST_ENUM_ITEM); if (str == enum_node->str) { - //log("\nadding enum item %s to scope\n", str.c_str()); + //log("\nadding enum item %s to scope\n", str); current_scope[str] = enum_node.get(); } } @@ -5404,7 +5404,7 @@ std::unique_ptr AstNode::eval_const_function(AstNode *fcall, bool must_ #if 0 log("-----------------------------------\n"); for (auto &it : variables) - log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val)); + log("%20s %40s\n", it.first, log_signal(it.second.val)); stmt->dumpAst(nullptr, "stmt> "); #endif if (stmt->type == AST_WIRE) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index f6b894563..d63044923 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -618,7 +618,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool error: log_error("Syntax error in line %d!\n", line_count); error_with_reason: - log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str()); + log_error("Syntax error in line %d: %s\n", line_count, err_reason); } struct BlifFrontend : public Frontend { diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 1aab81015..f2faa669b 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -289,7 +289,7 @@ void json_parse_attr_param(dict &results, JsonNode *node) void json_import(Design *design, string &modname, JsonNode *node) { - log("Importing module %s from JSON tree.\n", modname.c_str()); + log("Importing module %s from JSON tree.\n", modname); Module *module = new RTLIL::Module; module->name = RTLIL::escape_id(modname.c_str()); @@ -367,7 +367,7 @@ void json_import(Design *design, string &modname, JsonNode *node) port_wire->port_input = true; port_wire->port_output = true; } else - log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str()); + log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string); port_wire->port_id = port_id; diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 3228f02fb..72ad8b2b7 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& std::string id = RTLIL::escape_id(std::string(expr, id_len)); if (!module->wires_.count(id)) - log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str()); + log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id)); expr += id_len; return module->wires_.at(id); @@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend { if (cell->id != "cell" || cell->args.size() != 1) continue; - // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); + // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name)); std::map> type_map = global_type_map; parse_type_map(type_map, cell); @@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend { { if (!flag_ignore_miss_dir) { - log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name)); + log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name)); } else { - log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str()); + log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0)); delete module; goto skip_cell; } @@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend { if (node->id == "bus" && node->args.size() == 1) { if (flag_ignore_buses) { - log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str()); + log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0)); delete module; goto skip_cell; } @@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend { } if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) - log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name)); + log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name)); simple_comb_cell = false; diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 4a9ce4b8a..df64ecd2f 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -167,7 +167,7 @@ struct RpcModule : RTLIL::Module { std::string parameter_info; for (auto ¶m : parameters) { - log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second))); + log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second))); parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second))); } @@ -180,7 +180,7 @@ struct RpcModule : RTLIL::Module { derived_name = "$paramod" + stripped_name + parameter_info; if (design->has(derived_name)) { - log("Found cached RTLIL representation for module `%s'.\n", derived_name.c_str()); + log("Found cached RTLIL representation for module `%s'.\n", derived_name); } else { std::string command, input; std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters); @@ -437,7 +437,7 @@ struct RpcFrontend : public Pass { command_path_len_w = SearchPathW(/*lpPath=*/NULL, /*lpFileName=*/command_w.c_str(), /*lpExtension=*/L".exe", /*nBufferLength=*/0, /*lpBuffer=*/NULL, /*lpFilePart=*/NULL); if (command_path_len_w == 0) { - log_error("SearchPathW failed: %s\n", get_last_error_str().c_str()); + log_error("SearchPathW failed: %s\n", get_last_error_str()); goto cleanup_exec; } command_path_w.resize(command_path_len_w - 1); @@ -448,19 +448,19 @@ struct RpcFrontend : public Pass { pipe_attr.bInheritHandle = TRUE; pipe_attr.lpSecurityDescriptor = NULL; if (!CreatePipe(&send_r, &send_w, &pipe_attr, /*nSize=*/0)) { - log_error("CreatePipe failed: %s\n", get_last_error_str().c_str()); + log_error("CreatePipe failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!SetHandleInformation(send_w, HANDLE_FLAG_INHERIT, 0)) { - log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str()); + log_error("SetHandleInformation failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!CreatePipe(&recv_r, &recv_w, &pipe_attr, /*nSize=*/0)) { - log_error("CreatePipe failed: %s\n", get_last_error_str().c_str()); + log_error("CreatePipe failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!SetHandleInformation(recv_r, HANDLE_FLAG_INHERIT, 0)) { - log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str()); + log_error("SetHandleInformation failed: %s\n", get_last_error_str()); goto cleanup_exec; } @@ -470,7 +470,7 @@ struct RpcFrontend : public Pass { startup_info.hStdError = GetStdHandle(STD_ERROR_HANDLE); startup_info.dwFlags |= STARTF_USESTDHANDLES; if (!CreateProcessW(/*lpApplicationName=*/command_path_w.c_str(), /*lpCommandLine=*/&command_line_w[0], /*lpProcessAttributes=*/NULL, /*lpThreadAttributes=*/NULL, /*bInheritHandles=*/TRUE, /*dwCreationFlags=*/0, /*lpEnvironment=*/NULL, /*lpCurrentDirectory=*/NULL, &startup_info, &proc_info)) { - log_error("CreateProcessW failed: %s\n", get_last_error_str().c_str()); + log_error("CreateProcessW failed: %s\n", get_last_error_str()); goto cleanup_exec; } CloseHandle(proc_info.hProcess); @@ -550,7 +550,7 @@ cleanup_exec: h = CreateFileW(path_w.c_str(), GENERIC_READ|GENERIC_WRITE, /*dwShareMode=*/0, /*lpSecurityAttributes=*/NULL, /*dwCreationDisposition=*/OPEN_EXISTING, /*dwFlagsAndAttributes=*/0, /*hTemplateFile=*/NULL); if (h == INVALID_HANDLE_VALUE) { - log_error("CreateFileW failed: %s\n", get_last_error_str().c_str()); + log_error("CreateFileW failed: %s\n", get_last_error_str()); goto cleanup_path; } @@ -586,7 +586,7 @@ cleanup_path: log_cmd_error("Failed to connect to RPC frontend.\n"); for (auto &module_name : server->get_module_names()) { - log("Linking module `%s'.\n", module_name.c_str()); + log("Linking module `%s'.\n", module_name); RpcModule *module = new RpcModule; module->name = "$abstract\\" + module_name; module->server = server; diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 2c1910d13..e8d6ac9c9 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -90,7 +90,7 @@ struct RTLILFrontend : public Frontend { } extra_args(f, filename, args, argidx); - log("Input filename: %s\n", filename.c_str()); + log("Input filename: %s\n", filename); RTLIL_FRONTEND::lexin = f; RTLIL_FRONTEND::current_design = design; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d4bedf44f..9e3436c14 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -143,7 +143,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); else - log("%s%s\n", message_prefix.c_str(), message.c_str()); + log("%s%s\n", message_prefix, message); } if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR)) verific_error_msg = message; @@ -250,7 +250,7 @@ static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ) { if (val.size()==3 && val[0]=='\'' && val.back()=='\'') return RTLIL::Const::from_string(val.substr(1,val.size()-2)); - log_error("Error parsing VHDL %s.\n", typ.c_str()); + log_error("Error parsing VHDL %s.\n", typ); } static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ) @@ -261,7 +261,7 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string c.flags |= RTLIL::CONST_FLAG_SIGNED; return c; } - log_error("Error parsing VHDL %s.\n", typ.c_str()); + log_error("Error parsing VHDL %s.\n", typ); } static const RTLIL::Const extract_vhdl_integer(std::string &val) @@ -2655,7 +2655,7 @@ struct VerificExtNets cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner(); } - log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str()); + log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A), get_full_netlist_name(B)); } void run(Netlist *nl) @@ -2679,17 +2679,17 @@ struct VerificExtNets continue; if (verific_verbose) - log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name()); + log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl), inst->Name(), port->Name()); Netlist *ext_nl = net->Owner(); if (verific_verbose) - log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str()); + log(" external net owner: %s\n", get_full_netlist_name(ext_nl)); Netlist *ca_nl = find_common_ancestor(nl, ext_nl); if (verific_verbose) - log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str()); + log(" common ancestor: %s\n", get_full_netlist_name(ca_nl)); Net *ca_net = route_up(net, !port->IsOutput(), ca_nl); Net *new_net = ca_net; @@ -3038,7 +3038,7 @@ std::string verific_import(Design *design, const std::mapChangePortBusStructures(1 /* hierarchical */); @@ -3060,7 +3060,7 @@ std::string verific_import(Design *design, const std::map 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r')) break; @@ -4232,7 +4232,7 @@ struct VerificPass : public Pass { } lines.sort(); for (auto &line : lines) - log("verific -cfg %s\n", line.c_str()); + log("verific -cfg %s\n", line); goto check_error; } @@ -4291,7 +4291,7 @@ struct VerificPass : public Pass { } if (!verific_error_msg.empty()) - log_error("%s\n", verific_error_msg.c_str()); + log_error("%s\n", verific_error_msg); } #else /* YOSYS_ENABLE_VERIFIC */ diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 8b98997f6..cc5f07004 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1024,7 +1024,7 @@ struct VerificSvaImporter [[noreturn]] void parser_error(std::string errmsg) { if (!importer->mode_keep) - log_error("%s", errmsg.c_str()); + log_error("%s", errmsg); log_warning("%s", errmsg.c_str()); throw ParserErrorException(); } diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7d011b68e..8674758ab 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -242,7 +242,7 @@ struct arg_map_t void add_arg(const std::string &name, const char *default_value) { if (find(name)) { - log_error("Duplicate macro arguments with name `%s'.\n", name.c_str()); + log_error("Duplicate macro arguments with name `%s'.\n", name); } name_to_pos[name] = args.size(); @@ -789,14 +789,14 @@ frontend_verilog_preproc(std::istream &f, else if (ifdef_pass_level > 0) ifdef_pass_level--; else - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); continue; } if (tok == "`else") { if (ifdef_fail_level == 0) { if (ifdef_pass_level == 0) - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); ifdef_pass_level--; ifdef_fail_level = 1; ifdef_already_satisfied = true; @@ -813,7 +813,7 @@ frontend_verilog_preproc(std::istream &f, std::string name = next_token(true); if (ifdef_fail_level == 0) { if (ifdef_pass_level == 0) - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); ifdef_pass_level--; ifdef_fail_level = 1; ifdef_already_satisfied = true; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 4b4f7ad8d..589b80f8d 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -497,7 +497,7 @@ struct VerilogFrontend : public Frontend { if (!flag_nopp) { code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode); if (flag_ppdump) - log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); + log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc); parse_state.lexin = new std::istringstream(code_after_preproc); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb61e05df..d61fa7830 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3261,7 +3261,7 @@ basic_expr: ConstParser p{@4}; auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); if (val == nullptr) - log_error("Value conversion failed: `%s'\n", $4->c_str()); + log_error("Value conversion failed: `%s'\n", *$4); $$ = std::make_unique(@$, AST_TO_BITS, std::move($2), std::move(val)); } | hierarchical_id integral_number { @@ -3274,7 +3274,7 @@ basic_expr: auto val = p.const2ast(*$2, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); SET_AST_NODE_LOC(val.get(), @2, @2); if (val == nullptr) - log_error("Value conversion failed: `%s'\n", $2->c_str()); + log_error("Value conversion failed: `%s'\n", *$2); $$ = std::make_unique(@$, AST_TO_BITS, std::move(bits), std::move(val)); } | integral_number { @@ -3282,7 +3282,7 @@ basic_expr: $$ = p.const2ast(*$1, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); SET_AST_NODE_LOC($$.get(), @1, @1); if ($$ == nullptr) - log_error("Value conversion failed: `%s'\n", $1->c_str()); + log_error("Value conversion failed: `%s'\n", *$1); } | TOK_REALVAL { $$ = std::make_unique(@$, AST_REALVALUE); diff --git a/kernel/driver.cc b/kernel/driver.cc index 76c11853e..bbe4e46f3 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -585,7 +585,7 @@ int main(int argc, char **argv) FILE *scriptfp = fopen(scriptfile.c_str(), "r"); if (scriptfp == nullptr) { - log_error("Failed to open file '%s' for reading.\n", scriptfile.c_str()); + log_error("Failed to open file '%s' for reading.\n", scriptfile); } if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { log_flush(); @@ -664,7 +664,7 @@ int main(int argc, char **argv) log("Warnings: %d experimental features used (not excluded with -x).\n", GetSize(log_experimentals)); #ifdef _WIN32 - log("End of script. Logfile hash: %s\n", hash.c_str()); + log("End of script. Logfile hash: %s\n", hash); #else std::string meminfo; std::string stats_divider = ", "; @@ -690,7 +690,7 @@ int main(int argc, char **argv) meminfo = stringf(", MEM: %.2f MB peak", ru_buffer.ru_maxrss / (1024.0 * 1024.0)); #endif - log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(), + log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash, stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec, ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec, meminfo.c_str()); #endif @@ -768,9 +768,9 @@ int main(int argc, char **argv) f = fopen(filename.c_str(), "a+"); if (f == NULL) - log_error("Can't create coverage file `%s'.\n", filename.c_str()); + log_error("Can't create coverage file `%s'.\n", filename); - log("\n", filename.c_str()); + log("\n", filename); for (auto &it : get_coverage_data()) fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 35e7a2865..cc558d418 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -35,7 +35,7 @@ FstData::FstData(std::string filename) : ctx(nullptr) filename_trim.erase(filename_trim.size()-4); tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir(), filename_trim); std::string cmd = stringf("vcd2fst %s %s", filename, tmp_file); - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); filename = tmp_file; @@ -44,7 +44,7 @@ FstData::FstData(std::string filename) : ctx(nullptr) const std::vector g_units = { "s", "ms", "us", "ns", "ps", "fs", "as", "zs" }; ctx = (fstReaderContext *)fstReaderOpen(filename.c_str()); if (!ctx) - log_error("Error opening '%s' as FST file\n", filename.c_str()); + log_error("Error opening '%s' as FST file\n", filename); int scale = (int)fstReaderGetTimescale(ctx); timescale = pow(10.0, scale); timescale_str = ""; diff --git a/kernel/functional.cc b/kernel/functional.cc index 211527926..de8e7e8fc 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -395,7 +395,7 @@ public: Node y = neg_if(y_flipped, sign(b)); return factory.extend(y, y_width, true); } else - log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + log_error("unhandled cell in CellSimplifier %s\n", cellType); } else { if(cellType.in(ID($mod), ID($modfloor))) return factory.extend(factory.unsigned_mod(a, b), y_width, false); @@ -458,9 +458,9 @@ public: return factory.value(state); } } else if(cellType == ID($check)) { - log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName.c_str()); + log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName); } else { - log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str()); + log_error("`%s' cells are not supported by the functional backend\n", cellType); } } }; @@ -744,7 +744,7 @@ void IR::topological_sort() { log_warning("Combinational loop:\n"); for (int *i = begin; i != end; ++i) { Node node(_graph[*i]); - log("- %s = %s\n", RTLIL::unescape_id(node.name()).c_str(), node.to_string().c_str()); + log("- %s = %s\n", RTLIL::unescape_id(node.name()), node.to_string()); } log("\n"); scc = true; @@ -836,7 +836,7 @@ void Writer::print_impl(const char *fmt, vector> &fns) else p = pe; if(index >= fns.size()) - log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt).c_str()); + log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt)); fns[index](); next_index = index + 1; } @@ -844,7 +844,7 @@ void Writer::print_impl(const char *fmt, vector> &fns) case '}': p++; if(*p != '}') - log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt).c_str()); + log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt)); *os << '}'; break; default: diff --git a/kernel/functional.h b/kernel/functional.h index 7e5becef4..073adf40a 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -552,17 +552,17 @@ namespace Functional { } IRInput &add_input(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("input `%s` was re-defined", name.c_str()); + if (!inserted) log_error("input `%s` was re-defined", name); return it->second; } IROutput &add_output(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("output `%s` was re-defined", name.c_str()); + if (!inserted) log_error("output `%s` was re-defined", name); return it->second; } IRState &add_state(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("state `%s` was re-defined", name.c_str()); + if (!inserted) log_error("state `%s` was re-defined", name); return it->second; } Node value(IRInput const& input) { diff --git a/kernel/gzip.cc b/kernel/gzip.cc index 24907d8cf..d19c06579 100644 --- a/kernel/gzip.cc +++ b/kernel/gzip.cc @@ -121,7 +121,7 @@ std::istream* uncompressed(const std::string filename, std::ios_base::openmode m } if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { #ifdef YOSYS_ENABLE_ZLIB - log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename); if (magic[2] != 8) log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", filename.c_str(), unsigned(magic[2])); diff --git a/kernel/log.cc b/kernel/log.cc index 0dd56a04f..494047cde 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -228,7 +228,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s for (int c : header_count) header_id += stringf("%s%d", header_id.empty() ? "" : ".", c); - log("%s. ", header_id.c_str()); + log("%s. ", header_id); log_formatted_string(format, std::move(str)); log_flush(); @@ -237,7 +237,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s if (log_hdump.count(header_id) && design != nullptr) for (auto &filename : log_hdump.at(header_id)) { - log("Dumping current design to '%s'.\n", filename.c_str()); + log("Dumping current design to '%s'.\n", filename); if (yosys_xtrace) IdString::xtrace_db_dump(); Pass::call(design, {"dump", "-o", filename}); @@ -635,21 +635,21 @@ void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_cell(buf, indent, cell); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_wire(RTLIL::Wire *wire, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_wire(buf, indent, wire); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_check_expected() @@ -668,7 +668,7 @@ void log_check_expected() auto check = [&](const std::string kind, std::string pattern, LogExpectedItem item) { if (item.current_count == 0) { log_warn_regexes.clear(); - log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str()); + log_error("Expected %s pattern '%s' not found !\n", kind, pattern); } if (item.current_count != item.expected_count) { log_warn_regexes.clear(); @@ -689,7 +689,7 @@ void log_check_expected() auto check_err = [&](const std::string kind, std::string pattern, LogExpectedItem item) { if (item.current_count == item.expected_count) { log_warn_regexes.clear(); - log("Expected %s pattern '%s' found !!!\n", kind.c_str(), pattern.c_str()); + log("Expected %s pattern '%s' found !!!\n", kind, pattern); yosys_shutdown(); #ifdef EMSCRIPTEN throw 0; @@ -700,7 +700,7 @@ void log_check_expected() #endif } else { log_warn_regexes.clear(); - log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str()); + log_error("Expected %s pattern '%s' not found !\n", kind, pattern); } }; for (auto &[pattern, item] : expect_error) diff --git a/kernel/log.h b/kernel/log.h index 5143524bf..2a33953ff 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -424,7 +424,7 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false") static inline void log_dump_val_worker(double v) { log("%f", v); } static inline void log_dump_val_worker(char *v) { log("%s", v); } static inline void log_dump_val_worker(const char *v) { log("%s", v); } -static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } +static inline void log_dump_val_worker(std::string v) { log("%s", v); } static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); } static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } void log_dump_val_worker(RTLIL::IdString v); diff --git a/kernel/log_help.cc b/kernel/log_help.cc index 30c06a7c3..93b91b08b 100644 --- a/kernel/log_help.cc +++ b/kernel/log_help.cc @@ -85,7 +85,7 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead if (leading_newline) log("\n"); for (std::string line; std::getline(iss, line);) { - log("%s", indent_str.c_str()); + log("%s", indent_str); auto curr_len = indent_str.length(); std::istringstream lss(line); for (std::string word; std::getline(lss, word, ' ');) { @@ -93,10 +93,10 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead word = word.substr(1, word.length()-2); if (curr_len + word.length() >= MAX_LINE_LEN-1) { curr_len = 0; - log("\n%s", indent_str.c_str()); + log("\n%s", indent_str); } if (word.length()) { - log("%s ", word.c_str()); + log("%s ", word); curr_len += word.length() + 1; } } diff --git a/kernel/register.cc b/kernel/register.cc index c82620f40..4afd7ada3 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -54,7 +54,7 @@ Pass::Pass(std::string name, std::string short_help, source_location location) : void Pass::run_register() { if (pass_register.count(pass_name) && !replace_existing_pass()) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; } @@ -123,7 +123,7 @@ void Pass::help() prettyHelp.log_help(); } else { log("\n"); - log("No help message for command `%s'.\n", pass_name.c_str()); + log("No help message for command `%s'.\n", pass_name); log("\n"); } } @@ -143,7 +143,7 @@ void Pass::cmd_log_args(const std::vector &args) return; log("Full command line:"); for (size_t i = 0; i < args.size(); i++) - log(" %s", args[i].c_str()); + log(" %s", args[i]); log("\n"); } @@ -158,7 +158,7 @@ void Pass::cmd_error(const std::vector &args, size_t argidx, std::s command_text = command_text + (command_text.empty() ? "" : " ") + args[i]; } - log("\nSyntax error in command `%s':\n", command_text.c_str()); + log("\nSyntax error in command `%s':\n", command_text); help(); log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n", @@ -257,7 +257,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) if (echo_mode) { log("%s", create_prompt(design, 0)); for (size_t i = 0; i < args.size(); i++) - log("%s%s", i ? " " : "", args[i].c_str()); + log("%s%s", i ? " " : "", args[i]); log("\n"); } @@ -330,9 +330,9 @@ bool ScriptPass::check_label(std::string label, std::string info) if (active_design == nullptr) { log("\n"); if (info.empty()) - log(" %s:\n", label.c_str()); + log(" %s:\n", label); else - log(" %s: %s\n", label.c_str(), info.c_str()); + log(" %s: %s\n", label, info); return true; } else { if (!active_run_from.empty() && active_run_from == active_run_to) { @@ -351,9 +351,9 @@ void ScriptPass::run(std::string command, std::string info) { if (active_design == nullptr) { if (info.empty()) - log(" %s\n", command.c_str()); + log(" %s\n", command); else - log(" %s %s\n", command.c_str(), info.c_str()); + log(" %s %s\n", command, info); } else { Pass::call(active_design, command); active_design->check(); @@ -364,9 +364,9 @@ void ScriptPass::run_nocheck(std::string command, std::string info) { if (active_design == nullptr) { if (info.empty()) - log(" %s\n", command.c_str()); + log(" %s\n", command); else - log(" %s %s\n", command.c_str(), info.c_str()); + log(" %s %s\n", command, info); } else { Pass::call(active_design, command); } @@ -402,11 +402,11 @@ Frontend::Frontend(std::string name, std::string short_help, source_location loc void Frontend::run_register() { if (pass_register.count(pass_name) && !replace_existing_pass()) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; if (frontend_register.count(frontend_name) && !replace_existing_pass()) - log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name.c_str()); + log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name); frontend_register[frontend_name] = this; } @@ -462,7 +462,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r')) break; @@ -548,11 +548,11 @@ Backend::Backend(std::string name, std::string short_help, source_location locat void Backend::run_register() { if (pass_register.count(pass_name)) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; if (backend_register.count(backend_name)) - log_error("Unable to register backend '%s', backend already exists!\n", backend_name.c_str()); + log_error("Unable to register backend '%s', backend already exists!\n", backend_name); backend_register[backend_name] = this; } @@ -699,12 +699,12 @@ static void log_warning_flags(Pass *pass) { if (pass->experimental_flag) { if (!has_warnings) log("\n"); has_warnings = true; - log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name.c_str()); + log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name); } if (pass->internal_flag) { if (!has_warnings) log("\n"); has_warnings = true; - log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name.c_str()); + log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name); } if (has_warnings) log("\n"); @@ -966,7 +966,7 @@ struct HelpPass : public Pass { auto cell_pair = pair(cell_help, it.second); cells.emplace(name, cell_pair); } else { - log("ERROR: Missing cell help for cell '%s'.\n", name.c_str()); + log("ERROR: Missing cell help for cell '%s'.\n", name); raise_error |= true; } } @@ -1028,7 +1028,7 @@ struct HelpPass : public Pass { if (args.size() == 1) { log("\n"); for (auto &it : pass_register) - log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str()); + log(" %-20s %s\n", it.first, it.second->short_help); log("\n"); log("Type 'help ' for more information on a command.\n"); log("Type 'help -cells' for a list of all cell types.\n"); @@ -1040,7 +1040,7 @@ struct HelpPass : public Pass { if (args[1] == "-all") { for (auto &it : pass_register) { log("\n\n"); - log("%s -- %s\n", it.first.c_str(), it.second->short_help.c_str()); + log("%s -- %s\n", it.first, it.second->short_help); for (size_t i = 0; i < it.first.size() + it.second->short_help.size() + 6; i++) log("="); log("\n"); @@ -1052,7 +1052,7 @@ struct HelpPass : public Pass { log("\n"); for (auto &it : cell_help_messages.cell_help) { SimHelper help_cell = it.second; - log(" %-15s %s\n", help_cell.name.c_str(), help_cell.ports.c_str()); + log(" %-15s %s\n", help_cell.name, help_cell.ports); } log("\n"); log("Type 'help ' for more information on a cell type.\n"); @@ -1067,34 +1067,34 @@ struct HelpPass : public Pass { auto help_cell = cell_help_messages.get(args[1]); if (is_code_getter(args[1])) { log("\n"); - log("%s\n", help_cell.code.c_str()); + log("%s\n", help_cell.code); } else { - log("\n %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str()); + log("\n %s %s\n\n", help_cell.name, help_cell.ports); if (help_cell.ver == "2" || help_cell.ver == "2a") { - if (help_cell.title != "") log("%s:\n", help_cell.title.c_str()); + if (help_cell.title != "") log("%s:\n", help_cell.title); std::stringstream ss; ss << help_cell.desc; for (std::string line; std::getline(ss, line, '\n');) { - if (line != "::") log("%s\n", line.c_str()); + if (line != "::") log("%s\n", line); } } else if (help_cell.desc.length()) { - log("%s\n", help_cell.desc.c_str()); + log("%s\n", help_cell.desc); } else { log("No help message for this cell type found.\n"); } - log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str()); + log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1]); log("\n"); } } else - log("No such command or cell type: %s\n", args[1].c_str()); + log("No such command or cell type: %s\n", args[1]); return; } else if (args.size() == 3) { // this option is undocumented as it is for internal use only if (args[1] == "-dump-cmds-json") { PrettyJson json; if (!json.write_to_file(args[2])) - log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno)); if (dump_cmds_json(json)) { log_abort(); } @@ -1103,13 +1103,13 @@ struct HelpPass : public Pass { else if (args[1] == "-dump-cells-json") { PrettyJson json; if (!json.write_to_file(args[2])) - log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno)); if (dump_cells_json(json)) { log_error("One or more cells defined in celltypes.h are missing help documentation.\n"); } } else - log("Unknown help command: `%s %s'\n", args[1].c_str(), args[2].c_str()); + log("Unknown help command: `%s %s'\n", args[1], args[2]); return; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 352fbb84e..3a8b25d1d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1056,7 +1056,7 @@ void RTLIL::Design::add(RTLIL::Binding *binding) RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) { if (modules_.count(name) != 0) - log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str()); + log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name); log_assert(refcount_modules_ == 0); RTLIL::Module *module = new RTLIL::Module; diff --git a/kernel/sexpr.cc b/kernel/sexpr.cc index 0b977d2a8..bea3376a0 100644 --- a/kernel/sexpr.cc +++ b/kernel/sexpr.cc @@ -119,7 +119,7 @@ void SExprWriter::print(SExpr const &sexpr, bool close, bool indent_rest) { _pending_nl = true; } }else - log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string().c_str()); + log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string()); } void SExprWriter::close(size_t n) { diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 31d008404..4bdb680ac 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -87,7 +87,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a tcl_command_name = "renames"; Tcl_CmdInfo info; if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { - log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); + log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first); } else { std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name, it.first); Tcl_Eval(interp, tcl_script.c_str()); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 46dc6a76f..dc640fae9 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -710,7 +710,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } else if (filename == "-") { command = "script"; } else { - log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); + log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename); } } @@ -731,7 +731,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi from_to_active = run_from.empty(); } - log("\n-- Executing script file `%s' --\n", filename.c_str()); + log("\n-- Executing script file `%s' --\n", filename); FILE *f = stdin; @@ -741,7 +741,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } if (f == NULL) - log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open script file `%s' for reading: %s\n", filename, strerror(errno)); FILE *backup_script_file = Frontend::current_script_file; Frontend::current_script_file = f; @@ -790,9 +790,9 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } if (filename == "-") { - log("\n-- Parsing stdin using frontend `%s' --\n", command.c_str()); + log("\n-- Parsing stdin using frontend `%s' --\n", command); } else { - log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str()); + log("\n-- Parsing `%s' using frontend `%s' --\n", filename, command); } if (command[0] == ' ') { @@ -811,7 +811,7 @@ void run_pass(std::string command, RTLIL::Design *design) if (design == nullptr) design = yosys_design; - log("\n-- Running command `%s' --\n", command.c_str()); + log("\n-- Running command `%s' --\n", command); Pass::call(design, command); } @@ -843,16 +843,16 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.empty()) return; else - log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename.c_str()); + log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename); } if (filename.empty()) filename = "-"; if (filename == "-") { - log("\n-- Writing to stdout using backend `%s' --\n", command.c_str()); + log("\n-- Writing to stdout using backend `%s' --\n", command); } else { - log("\n-- Writing to `%s' using backend `%s' --\n", filename.c_str(), command.c_str()); + log("\n-- Writing to `%s' using backend `%s' --\n", filename, command); } Backend::backend_call(design, NULL, filename, command); diff --git a/kernel/yw.cc b/kernel/yw.cc index f36212c7f..daad53380 100644 --- a/kernel/yw.cc +++ b/kernel/yw.cc @@ -108,38 +108,38 @@ ReadWitness::ReadWitness(const std::string &filename) : { std::ifstream f(filename.c_str()); if (f.fail() || GetSize(filename) == 0) - log_error("Cannot open file `%s`\n", filename.c_str()); + log_error("Cannot open file `%s`\n", filename); std::stringstream buf; buf << f.rdbuf(); std::string err; json11::Json json = json11::Json::parse(buf.str(), err); if (!err.empty()) - log_error("Failed to parse `%s`: %s\n", filename.c_str(), err.c_str()); + log_error("Failed to parse `%s`: %s\n", filename, err); std::string format = json["format"].string_value(); if (format.empty()) - log_error("Failed to parse `%s`: Unknown format\n", filename.c_str()); + log_error("Failed to parse `%s`: Unknown format\n", filename); if (format != "Yosys Witness Trace") - log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename.c_str(), format.c_str()); + log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename, format); for (auto &clock_json : json["clocks"].array_items()) { Clock clock; clock.path = get_path(clock_json["path"]); if (clock.path.empty()) - log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename, clock_json.dump()); auto edge_str = clock_json["edge"]; if (edge_str.string_value() == "posedge") clock.is_posedge = true; else if (edge_str.string_value() == "negedge") clock.is_negedge = true; else - log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename, clock_json.dump()); if (!clock_json["offset"].is_number()) - log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename, clock_json.dump()); clock.offset = clock_json["offset"].int_value(); if (clock.offset < 0) - log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename, clock_json.dump()); clocks.push_back(clock); } @@ -149,18 +149,18 @@ ReadWitness::ReadWitness(const std::string &filename) : signal.bits_offset = bits_offset; signal.path = get_path(signal_json["path"]); if (signal.path.empty()) - log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename, signal_json.dump()); if (!signal_json["width"].is_number()) - log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename, signal_json.dump()); signal.width = signal_json["width"].int_value(); if (signal.width < 0) - log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename, signal_json.dump()); bits_offset += signal.width; if (!signal_json["offset"].is_number()) - log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename, signal_json.dump()); signal.offset = signal_json["offset"].int_value(); if (signal.offset < 0) - log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename, signal_json.dump()); signal.init_only = signal_json["init_only"].bool_value(); signals.push_back(signal); } @@ -168,11 +168,11 @@ ReadWitness::ReadWitness(const std::string &filename) : for (auto &step_json : json["steps"].array_items()) { Step step; if (!step_json["bits"].is_string()) - log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename.c_str(), GetSize(steps)); + log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename, GetSize(steps)); step.bits = step_json["bits"].string_value(); for (char c : step.bits) { if (c != '0' && c != '1' && c != 'x' && c != '?') - log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename.c_str(), c, GetSize(steps)); + log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename, c, GetSize(steps)); } steps.push_back(step); } diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index 907a16fe0..e475ba71c 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -67,7 +67,7 @@ struct Slice { int wire_offset(RTLIL::Wire *wire, int index) const { int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index); if (rtl_offset < 0 || rtl_offset >= wire->width) { - log_error("Slice %s is out of bounds for wire %s in module %s", to_string().c_str(), log_id(wire), log_id(wire->module)); + log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module)); } return rtl_offset; } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 833d6006d..0d395f043 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -38,22 +38,22 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const log_assert(is_formal_celltype(celltype)); if (wire == nullptr) { - log_error("Could not find wire with name \"%s\".\n", name.c_str()); + log_error("Could not find wire with name \"%s\".\n", name); } else { RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); formal_cell->setPort(ID::A, wire); if(enable_name == "") { formal_cell->setPort(ID::EN, State::S1); - log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str()); + log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name); } else { RTLIL::Wire *enable_wire = module->wire(escaped_enable_name); if(enable_wire == nullptr) - log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str()); + log_error("Could not find enable wire with name \"%s\".\n", enable_name); formal_cell->setPort(ID::EN, enable_wire); - log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str()); + log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name); } } } @@ -79,7 +79,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (wire == nullptr) log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); - log("Module %s already has such an object.\n", module->name.c_str()); + log("Module %s already has such an object.\n", module->name); } else { @@ -91,7 +91,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n module->fixup_ports(); } - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + log("Added wire %s to module %s.\n", name, module->name); } if (!flag_global) @@ -110,7 +110,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; cell->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str()); + log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type); } } diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 47354f1d5..bab00c287 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -146,7 +146,7 @@ struct CoverPass : public Pass { for (auto f : out_files) fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); if (do_log) - log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + log("%-60s %10d %s\n", it.second.first, it.second.second, it.first); } #else for (auto f : out_files) diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 933bd457f..9324cf630 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -105,7 +105,7 @@ struct EdgetypePass : public Pass { edge_cache.sort(); for (auto &str : edge_cache) - log("%s\n", str.c_str()); + log("%s\n", str); } } EdgetypePass; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index 486fa1c2b..b346fc95d 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -172,7 +172,7 @@ struct ExecPass : public Pass { std::string line = linebuf.substr(0, pos); linebuf.erase(0, pos + 1); if (!flag_quiet) - log("%s\n", line.c_str()); + log("%s\n", line); if (flag_expect_stdout) for(auto &x : expect_stdout) diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 60324702c..d7264d392 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -343,7 +343,7 @@ private: //with taint signals and connect the new ports to the corresponding taint signals. RTLIL::Module *cell_module_def = module->design->module(cell->type); dict orig_ports = cell->connections(); - log("Adding cell %s\n", cell_module_def->name.c_str()); + log("Adding cell %s\n", cell_module_def->name); for (auto &it : orig_ports) { RTLIL::SigSpec port = it.second; RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port); diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc index 00456b8f9..65e74cc04 100644 --- a/passes/cmds/internal_stats.cc +++ b/passes/cmds/internal_stats.cc @@ -100,15 +100,15 @@ struct InternalStatsPass : public Pass { if (json_mode) { log("{\n"); - log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str()); + log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump()); std::stringstream invocation; std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " ")); - log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str()); + log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump()); if (auto mem = current_mem_bytes()) { - log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str()); + log(" \"memory_now\": %s,\n", std::to_string(*mem)); } auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode); - log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str()); + log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes)); } // stats go here diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 9a88dec7f..6898f33f5 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -85,7 +85,7 @@ struct CoveragePass : public Pass { if (!ofile.empty()) { fout.open(ofile, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", ofile.c_str()); + log_error("Could not open file \"%s\" with write access.\n", ofile); } std::map> uncovered_lines; @@ -128,7 +128,7 @@ struct CoveragePass : public Pass { for (const auto& file_entry : all_lines) { int lines_found = file_entry.second.size(); int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0); - log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found); + log("File %s: %d/%d lines covered\n", file_entry.first, lines_hit, lines_found); if(!ofile.empty()) { fout << "SF:" << file_entry.first << "\n"; diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 391eaea2e..57759fc90 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -106,7 +106,7 @@ struct LogPass : public Pass { if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end); if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end); if (to_log) { - if (!header) log("%s%s", text.c_str(), line_end); + if (!header) log("%s%s", text, line_end); else log_header(design, "%s%s", text.c_str(), line_end); } } diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index a9762f630..37240bb7e 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -108,7 +108,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to warn list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to warn list.\n", pattern); log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -120,7 +120,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to nowarn list.\n", pattern); log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -132,7 +132,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to werror list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to werror list.\n", pattern); log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -152,7 +152,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-experimental" && argidx+1 < args.size()) { std::string value = args[++argidx]; - log("Added '%s' experimental ignore list.\n", value.c_str()); + log("Added '%s' experimental ignore list.\n", value); log_experimentals_ignored.insert(value); continue; } diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index a653844b7..6c7921d53 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -187,11 +187,11 @@ struct PluginPass : public Pass { log("Loaded plugins:\n"); for (auto &it : loaded_plugins) - log(" %s\n", it.first.c_str()); + log(" %s\n", it.first); #ifdef WITH_PYTHON for (auto &it : loaded_python_plugins) - log(" %s\n", it.first.c_str()); + log(" %s\n", it.first); #endif if (!loaded_plugin_aliases.empty()) { @@ -200,7 +200,7 @@ struct PluginPass : public Pass { for (auto &it : loaded_plugin_aliases) max_alias_len = max(max_alias_len, GetSize(it.first)); for (auto &it : loaded_plugin_aliases) - log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str()); + log("Alias: %-*s %s\n", max_alias_len, it.first, it.second); } } } diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 73ca98d88..36870489a 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -278,7 +278,7 @@ struct PortarcsPass : Pass { log("\n"); for (auto bit : outputs) { - log(" %10s ", bit_str(bit).c_str()); + log(" %10s ", bit_str(bit)); int *p = annotations.at(canonical_bit(bit)); for (auto i = 0; i < inputs.size(); i++) log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay); diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index f78d9d3b6..b109ce22a 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -75,7 +75,7 @@ struct PortlistPass : public Pass { } log("module %s%s\n", log_id(module), m_mode ? " (" : ""); for (int i = 0; i < GetSize(ports); i++) - log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : ""); + log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : ""); if (m_mode) log(");\nendmodule\n"); }; diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index c8b0a1d1f..e4e78b0ea 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass { static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { if (x.flags & RTLIL::CONST_FLAG_STRING) - log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str()); + log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string()); else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED) - log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str()); + log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string()); else log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail } @@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass { for (auto mod : design->selected_modules()) { if (design->selected_whole_module(mod)) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name)); + log("%s%s\n", get_indent_str(indent), log_id(mod->name)); indent += 2; for (auto &it : mod->attributes) log_const(it.first, it.second, indent); } for (auto cell : mod->selected_cells()) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name)); + log("%s%s\n", get_indent_str(indent), log_id(cell->name)); indent += 2; for (auto &it : cell->attributes) log_const(it.first, it.second, indent); @@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass { } for (auto wire : mod->selected_wires()) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name)); + log("%s%s\n", get_indent_str(indent), log_id(wire->name)); indent += 2; for (auto &it : wire->attributes) log_const(it.first, it.second, indent); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 1f3d0992e..c4bb7135e 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -577,7 +577,7 @@ struct RenamePass : public Pass { new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name)); auto new_name = new_wire_names[wire].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) - log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str()); + log_error("Failed to rename wire %s -> %s\n", name, new_name); } for (auto cell : module->selected_cells()) { @@ -590,7 +590,7 @@ struct RenamePass : public Pass { new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name)); auto new_name = new_cell_names[cell].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) - log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str()); + log_error("Failed to rename cell %s -> %s\n", name, new_name); } for (auto &it : new_wire_names) @@ -629,7 +629,7 @@ struct RenamePass : public Pass { if (module_to_rename != nullptr) { to_name = RTLIL::escape_id(to_name); - log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str()); + log("Renaming module %s to %s.\n", module_to_rename->name, to_name); design->rename(module_to_rename, to_name); } else log_cmd_error("Object `%s' not found!\n", from_name.c_str()); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index e55e63828..680531f25 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -101,7 +101,7 @@ struct SccWorker design(design), module(module), sigmap(module) { if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); return; } diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 4a63f2f60..f64ce943c 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -76,18 +76,18 @@ struct ScratchpadPass : public Pass { if (args[argidx] == "-get" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier)) { - log("%s\n", design->scratchpad_get_string(identifier).c_str()); + log("%s\n", design->scratchpad_get_string(identifier)); } else if (RTLIL::constpad.count(identifier)) { - log("%s\n", RTLIL::constpad.at(identifier).c_str()); + log("%s\n", RTLIL::constpad.at(identifier)); } else { - log("\"%s\" not set\n", identifier.c_str()); + log("\"%s\" not set\n", identifier); } continue; } if (args[argidx] == "-set" && argidx+2 < args.size()) { string identifier = args[++argidx]; if (RTLIL::constpad.count(identifier)) - log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str()); + log_error("scratchpad entry \"%s\" is a global constant\n", identifier); string value = args[++argidx]; if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2); design->scratchpad_set_string(identifier, value); @@ -107,9 +107,9 @@ struct ScratchpadPass : public Pass { else if (RTLIL::constpad.count(identifier_from)) value = RTLIL::constpad.at(identifier_from); else - log_error("\"%s\" not set\n", identifier_from.c_str()); + log_error("\"%s\" not set\n", identifier_from); if (RTLIL::constpad.count(identifier_to)) - log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str()); + log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to); design->scratchpad_set_string(identifier_to, value); continue; } @@ -118,7 +118,7 @@ struct ScratchpadPass : public Pass { string expected = args[++argidx]; if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2); if (design->scratchpad.count(identifier) == 0) - log_error("scratchpad entry '%s' is not defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is not defined\n", identifier); string value = design->scratchpad_get_string(identifier); if (value != expected) { log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n", @@ -129,13 +129,13 @@ struct ScratchpadPass : public Pass { if (args[argidx] == "-assert-set" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier) == 0) - log_error("scratchpad entry '%s' is not defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is not defined\n", identifier); continue; } if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier) > 0) - log_error("scratchpad entry '%s' is defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is defined\n", identifier); continue; } break; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 901f923f8..7fcf5cfcd 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -632,20 +632,20 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char if (rule.cell_types.size() > 0) { log(" cell types:"); for (auto &it : rule.cell_types) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } if (rule.port_names.size() > 0) { log(" port names:"); for (auto &it : rule.port_names) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } } if (limits.size() > 0) { log(" limits:"); for (auto &it : limits) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } #endif @@ -1443,7 +1443,7 @@ struct SelectPass : public Pass { std::ifstream f(read_file); yosys_input_files.insert(read_file); if (f.fail()) - log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno)); + log_error("Can't open '%s' for reading: %s\n", read_file, strerror(errno)); auto sel = RTLIL::Selection::EmptySelection(design); string line; @@ -1518,7 +1518,7 @@ struct SelectPass : public Pass { f = fopen(write_file.c_str(), "w"); yosys_output_files.insert(write_file); if (f == nullptr) - log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno)); + log_error("Can't open '%s' for writing: %s\n", write_file, strerror(errno)); } if (work_stack.size() > 0) design->push_selection(work_stack.back()); @@ -1573,7 +1573,7 @@ struct SelectPass : public Pass { RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); std::string desc = describe_selection_for_assert(design, sel, true); - log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str()); + log_error("Assertion failed: selection is not empty:%s\n%s", sel_str, desc); } return; } @@ -1588,7 +1588,7 @@ struct SelectPass : public Pass { RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); std::string desc = describe_selection_for_assert(design, sel, true); - log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str()); + log_error("Assertion failed: selection is empty:%s\n%s", sel_str, desc); } return; } @@ -1645,7 +1645,7 @@ struct SelectPass : public Pass { if (!unset_name.empty()) { if (!design->selection_vars.erase(unset_name)) - log_error("Selection '%s' does not exist!\n", unset_name.c_str()); + log_error("Selection '%s' does not exist!\n", unset_name); return; } diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index dce33c05b..c4a555e6a 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -41,7 +41,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width if (module->count_id(name) != 0) { - log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + log("Module %s already has such an object %s.\n", module->name, name); name += "$"; return add_wire(module, name, width, flag_input, flag_output); } @@ -56,7 +56,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width module->fixup_ports(); } - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + log("Added wire %s to module %s.\n", name, module->name); } return wire; @@ -319,7 +319,7 @@ struct SetundefPass : public Pass { wire = add_wire(module, name, c.width, true, false); module->connect(RTLIL::SigSig(c, wire)); } - log("Exposing undriven wire %s as input.\n", wire->name.c_str()); + log("Exposing undriven wire %s as input.\n", wire->name); } module->fixup_ports(); } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 9ea29bc4e..49032a0e0 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -188,7 +188,7 @@ struct ShowWorker if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; - log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str()); + log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id); } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { @@ -895,7 +895,7 @@ struct ShowPass : public Pass { f.open(filename.c_str()); yosys_input_files.insert(filename); if (f.fail()) - log_error("Can't open lib file `%s'.\n", filename.c_str()); + log_error("Can't open lib file `%s'.\n", filename); RTLIL::Design *lib = new RTLIL::Design; Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); @@ -907,7 +907,7 @@ struct ShowPass : public Pass { std::string dot_file = stringf("%s.dot", prefix); std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format); - log("Writing dot description to `%s'.\n", dot_file.c_str()); + log("Writing dot description to `%s'.\n", dot_file); FILE *f = fopen(dot_file.c_str(), "w"); if (custom_prefix) yosys_output_files.insert(dot_file); @@ -934,7 +934,7 @@ struct ShowPass : public Pass { #endif std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); #if !defined(YOSYS_DISABLE_SPAWN) if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); @@ -954,7 +954,7 @@ struct ShowPass : public Pass { #else std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } else @@ -964,7 +964,7 @@ struct ShowPass : public Pass { #else std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 4ad0d2b25..2993c3d3a 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -345,7 +345,7 @@ struct SplicePass : public Pass { for (auto module : design->selected_modules()) { if (module->processes.size()) { - log("Skipping module %s as it contains processes.\n", module->name.c_str()); + log("Skipping module %s as it contains processes.\n", module->name); continue; } diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 9281f3327..1b9e6106c 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -285,7 +285,7 @@ struct statdata_t { cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } } else { - log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type.c_str(), + log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type, (int)cell_data.double_parameter_area.size()); } } @@ -452,22 +452,22 @@ struct statdata_t { if (print_area) { if (print_hierarchical) { - log(" %s %s %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), count_local_str.c_str(), + log(" %s %s %s %s %s%s\n", count_global_str, area_global_str, count_local_str, area_local_str.c_str(), indent.c_str(), name.c_str()); } else if (print_global_only) { - log(" %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_global_str, area_global_str, indent, name); } else { if (count_local > 0) - log(" %s %s %s%s\n", count_local_str.c_str(), area_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_local_str, area_local_str, indent, name); } } else { if (print_hierarchical) { - log(" %s %s %s%s\n", count_global_str.c_str(), count_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_global_str, count_local_str, indent, name); } else if (print_global_only) { - log(" %s %s%s\n", count_global_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s%s\n", count_global_str, indent, name); } else { if (count_local > 0) - log(" %s %s%s\n", count_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s%s\n", count_local_str, indent, name); } } } @@ -540,13 +540,13 @@ struct statdata_t { if (!unknown_cell_area.empty()) { log("\n"); for (auto cell_type : unknown_cell_area) - log(" Area for cell type %s is unknown!\n", cell_type.c_str()); + log(" Area for cell type %s is unknown!\n", cell_type); } if (area != 0) { log("\n"); if (print_hierarchical || print_global_only) { - log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area); log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area); } else { double local_area = 0; @@ -555,7 +555,7 @@ struct statdata_t { double local_sequential_area = 0; for (auto &it : local_seq_area_cells_by_type) local_sequential_area += it.second; - log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area); log(" of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area, 100.0 * local_sequential_area / local_area); } @@ -587,19 +587,19 @@ struct statdata_t { if (!first_module) log(",\n"); if (hierarchical) { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); - log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0).c_str()); - log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0).c_str()); - log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0).c_str()); - log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0).c_str()); - log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0).c_str()); - log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0).c_str()); - log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0).c_str()); - log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0).c_str()); - log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0).c_str()); - log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area).c_str()); - log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area).c_str()); - log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area).c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); + log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0)); + log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0)); + log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0)); + log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0)); + log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0)); + log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0)); + log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0)); + log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0)); + log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0)); + log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area)); + log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area)); + log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area)); log(" \"num_cells_by_type\": {\n"); bool first_line = true; @@ -607,7 +607,7 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(), + log(" %s: %s", json11::Json(log_id(it.first)).dump(), json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0, local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second, area_cells_by_type.at(it.first)) @@ -621,7 +621,7 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(), + log(" %s: %s", json11::Json(log_id(it.first)).dump(), json_line(0, 0, it.second, submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0) .c_str()); @@ -640,7 +640,7 @@ struct statdata_t { } else { if (global_only) { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); log(" \"num_wires\": %u,\n", num_wires); log(" \"num_wire_bits\": %u,\n", num_wire_bits); log(" \"num_pub_wires\": %u,\n", num_pub_wires); @@ -662,20 +662,20 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } for (auto &it : num_submodules_by_type) if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } log("\n"); log(" }"); } else { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); log(" \"num_wires\": %u,\n", local_num_wires); log(" \"num_wire_bits\": %u,\n", local_num_wire_bits); log(" \"num_pub_wires\": %u,\n", local_num_pub_wires); @@ -697,14 +697,14 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } for (auto &it : num_submodules_by_type) if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } log("\n"); @@ -824,11 +824,11 @@ void read_liberty_cellarea(dict &cell_area, string libert double value = std::stod(s); single_parameter_area.push_back(value); } catch (const std::exception &e) { - log_error("Failed to parse single parameter area value '%s': %s\n", s.c_str(), e.what()); + log_error("Failed to parse single parameter area value '%s': %s\n", s, e.what()); } } if (single_parameter_area.size() == 0) - log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1].c_str()); + log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1]); // check if it is a double parameterised area } const LibertyAst *dar = cell->find("double_area_parameterised"); @@ -857,12 +857,12 @@ void read_liberty_cellarea(dict &cell_area, string libert value = std::stod(s); cast_sub_array.push_back(value); } catch (const std::exception &e) { - log_error("Failed to parse double parameter area value for '%s': %s\n", s.c_str(), e.what()); + log_error("Failed to parse double parameter area value for '%s': %s\n", s, e.what()); } } double_parameter_area.push_back(cast_sub_array); if (cast_sub_array.size() == 0) - log_error("double paramter array has size 0: %s\n", s.c_str()); + log_error("double paramter array has size 0: %s\n", s); } } const LibertyAst *par = cell->find("port_names"); @@ -973,10 +973,10 @@ struct StatPass : public Pass { if (json_mode) { log("{\n"); - log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str()); + log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump()); std::stringstream invocation; std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " ")); - log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str()); + log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump()); log(" \"modules\": {\n"); } diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index f0e4943de..86a529520 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -322,7 +322,7 @@ struct EstimateSta { std::string src_attr = cell->get_src_attribute(); cell_src = stringf(" source: %s", src_attr); } - log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str()); + log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src); printed.insert(cell); } } else { @@ -333,7 +333,7 @@ struct EstimateSta { std::string src_attr = bit.wire->get_src_attribute(); wire_src = stringf(" source: %s", src_attr); } - log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]); + log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src, levels[node]); } } diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 323b9cb34..fd45d6ba0 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -988,7 +988,7 @@ struct VizPass : public Pass { if (custom_prefix) yosys_output_files.insert(dot_file); - log("Writing dot description to `%s'.\n", dot_file.c_str()); + log("Writing dot description to `%s'.\n", dot_file); FILE *f = nullptr; auto open_dot_file = [&]() { if (f != nullptr) return; @@ -1028,7 +1028,7 @@ struct VizPass : public Pass { #endif std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); #if !defined(YOSYS_DISABLE_SPAWN) if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); @@ -1047,7 +1047,7 @@ struct VizPass : public Pass { #else std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } else @@ -1057,7 +1057,7 @@ struct VizPass : public Pass { #else std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc index f7d9fbeed..4c6f44ed7 100644 --- a/passes/cmds/wrapcell.cc +++ b/passes/cmds/wrapcell.cc @@ -59,7 +59,7 @@ std::optional format_with_params(std::string fmt, const dict format_with_params(std::string fmt, const dicttype.c_str(), cell->name.c_str()); + log(" merging %s cell %s.\n", cell->type, cell->name); merged_set.insert(cell); already_optimized = false; @@ -243,7 +243,7 @@ struct FsmExpand void execute() { log("\n"); - log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str()); + log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name); already_optimized = false; limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int(); diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 65dda1267..7c79a53cc 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -76,7 +76,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st kiss_file.open(kiss_name, std::ios::out | std::ios::trunc); if (!kiss_file.is_open()) { - log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str()); + log_error("Could not open file \"%s\" with write access.\n", kiss_name); } fsm_data.copy_from_cell(cell); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index a0fd50097..d83cff5cdc 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -71,7 +71,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL { RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) { - log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); + log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name); return false; } @@ -255,7 +255,7 @@ undef_bit_in_next_state: static void extract_fsm(RTLIL::Wire *wire) { - log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str()); + log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name); // get input and output signals for state ff @@ -274,7 +274,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q) continue; - log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); + log(" found %s cell for state register: %s\n", cell->type, cell->name); RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q)); RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D)); clk = cell->getPort(ID::CLK); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 711a81db2..8a18d259a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapname.c_str(), module->name.c_str()); + log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name, module->name); FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 2db011cd0..99771f90a 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -293,7 +293,7 @@ struct FsmOpt FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module) { - log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str()); + log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name); fsm_data.copy_from_cell(cell); this->cell = cell; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index bcdea9d87..8ee03329f 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -56,15 +56,15 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs { std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto"; - log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); + log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding); if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { - log(" unknown encoding `%s': using auto instead.\n", encoding.c_str()); + log(" unknown encoding `%s': using auto instead.\n", encoding); encoding = "auto"; } if (encoding == "none" || encoding == "user") { - log(" nothing to do for encoding `%s'.\n", encoding.c_str()); + log(" nothing to do for encoding `%s'.\n", encoding); return; } @@ -79,7 +79,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs encoding = default_encoding; else encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary"; - log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str()); + log(" mapping auto encoding to `%s` for this FSM.\n", encoding); } if (encoding == "one-hot") { @@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs } fsm_data.state_bits = new_num_state_bits; } else - log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); + log_error("FSM encoding `%s' is not supported!\n", encoding); if (encfile) fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str()); @@ -113,7 +113,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs } else log_abort(); - log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str()); + log(" %s -> %s\n", fsm_data.state_table[i].as_string(), new_code.as_string()); if (encfile) fprintf(encfile, ".map %s %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str()); fsm_data.state_table[i] = new_code; @@ -165,13 +165,13 @@ struct FsmRecodePass : public Pass { if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) { fm_set_fsm_file = fopen(args[++argidx].c_str(), "w"); if (fm_set_fsm_file == NULL) - log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno)); + log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx], strerror(errno)); continue; } if (arg == "-encfile" && argidx+1 < args.size() && encfile == NULL) { encfile = fopen(args[++argidx].c_str(), "w"); if (encfile == NULL) - log_error("Can't open encfile `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno)); + log_error("Can't open encfile `%s' for writing: %s\n", args[argidx], strerror(errno)); continue; } if (arg == "-encoding" && argidx+1 < args.size() && default_encoding.empty()) { diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 1c6aaf65f..9aa12241e 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -134,7 +134,7 @@ struct FsmData { log("-------------------------------------\n"); log("\n"); - log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str()); + log(" Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string()); log("\n"); log(" Number of input signals: %3d\n", num_inputs); log(" Number of output signals: %3d\n", num_outputs); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 69ef744ca..6fec628c2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -59,7 +59,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, std::set portnames; std::set parameters; std::map portwidths; - log("Generate module for cell type %s:\n", celltype.c_str()); + log("Generate module for cell type %s:\n", celltype); for (auto mod : design->modules()) for (auto cell : mod->cells()) @@ -605,9 +605,9 @@ void hierarchy_worker(RTLIL::Design *design, std::setname.c_str()); + log("Top module: %s\n", mod->name); else if (!mod->get_blackbox_attribute()) - log("Used module: %*s%s\n", indent, "", mod->name.c_str()); + log("Used module: %*s%s\n", indent, "", mod->name); used.insert(mod); for (auto cell : mod->cells()) { @@ -647,7 +647,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) for (auto mod : del_modules) { if (!purge_lib && mod->get_blackbox_attribute()) continue; - log("Removing unused module `%s'.\n", mod->name.c_str()); + log("Removing unused module `%s'.\n", mod->name); design->remove(mod); del_counter++; } @@ -873,11 +873,11 @@ struct HierarchyPass : public Pass { log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output"); if (decl.index >= 1) log(" [at position %d]", decl.index); - log(" %s\n", decl.portname.c_str()); + log(" %s\n", decl.portname); generate_ports.push_back(decl); continue; is_celltype: - log("Celltype: %s\n", args[argidx].c_str()); + log("Celltype: %s\n", args[argidx]); generate_cells.push_back(RTLIL::unescape_id(args[argidx])); } continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 8d88a8919..d77d65359 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker void handle_submodule(SubModule &submod) { - log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str()); + log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name); wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { @@ -192,13 +192,13 @@ struct SubmodWorker } if (new_wire->port_input && new_wire->port_output) - log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: inout %s\n", wire->name, new_wire->name); else if (new_wire->port_input) - log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: input %s\n", wire->name, new_wire->name); else if (new_wire->port_output) - log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: output %s\n", wire->name, new_wire->name); else - log(" signal %s: internal\n", wire->name.c_str()); + log(" signal %s: internal\n", wire->name); flags.new_wire = new_wire; } @@ -214,7 +214,7 @@ struct SubmodWorker log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags.at(bit.wire).new_wire; } - log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); + log(" cell %s (%s)\n", new_cell->name, new_cell->type); if (!copy_mode) module->remove(cell); } @@ -250,12 +250,12 @@ struct SubmodWorker return; if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); return; } if (module->memories.size() > 0) { - log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name); return; } diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index fb256e41c..61589cab0 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -134,7 +134,7 @@ struct Parser { rewrite_filename(filename); infile.open(filename); if (infile.fail()) { - log_error("failed to open %s\n", filename.c_str()); + log_error("failed to open %s\n", filename); } parse(); infile.close(); @@ -181,14 +181,14 @@ struct Parser { void eat_token(std::string expected) { std::string token = get_token(); if (token != expected) { - log_error("%s:%d: expected `%s`, got `%s`.\n", filename.c_str(), line_number, expected.c_str(), token.c_str()); + log_error("%s:%d: expected `%s`, got `%s`.\n", filename, line_number, expected, token); } } IdString get_id() { std::string token = get_token(); if (token.empty() || (token[0] != '$' && token[0] != '\\')) { - log_error("%s:%d: expected id string, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected id string, got `%s`.\n", filename, line_number, token); } return IdString(token); } @@ -203,14 +203,14 @@ struct Parser { if (!isalnum(c) && c != '_') valid = false; if (!valid) - log_error("%s:%d: expected name, got `%s`.\n", filename.c_str(), line_number, res.c_str()); + log_error("%s:%d: expected name, got `%s`.\n", filename, line_number, res); return res; } std::string get_string() { std::string token = get_token(); if (token.size() < 2 || token[0] != '"' || token[token.size()-1] != '"') { - log_error("%s:%d: expected string, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected string, got `%s`.\n", filename, line_number, token); } return token.substr(1, token.size()-2); } @@ -225,7 +225,7 @@ struct Parser { char *endptr; long res = strtol(token.c_str(), &endptr, 0); if (token.empty() || *endptr || res > INT_MAX) { - log_error("%s:%d: expected int, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected int, got `%s`.\n", filename, line_number, token); } return res; } @@ -235,7 +235,7 @@ struct Parser { char *endptr; double res = strtod(token.c_str(), &endptr); if (token.empty() || *endptr) { - log_error("%s:%d: expected float, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected float, got `%s`.\n", filename, line_number, token); } return res; } @@ -248,7 +248,7 @@ struct Parser { void get_semi() { std::string token = get_token(); if (token != ";") { - log_error("%s:%d: expected `;`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `;`, got `%s`.\n", filename, line_number, token); } } @@ -387,7 +387,7 @@ struct Parser { exit_portoption(); } else if (token == "clock") { if (port.kind == PortKind::Ar) { - log_error("%s:%d: `clock` not allowed in async read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `clock` not allowed in async read port.\n", filename, line_number); } ClockDef def; token = get_token(); @@ -398,7 +398,7 @@ struct Parser { } else if (token == "negedge") { def.kind = ClkPolKind::Negedge; } else { - log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename, line_number, token); } if (peek_string()) { def.name = get_string(); @@ -407,13 +407,13 @@ struct Parser { add_cap(port.clock, def); } else if (token == "clken") { if (port.kind == PortKind::Ar) { - log_error("%s:%d: `clken` not allowed in async read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `clken` not allowed in async read port.\n", filename, line_number); } get_semi(); add_cap(port.clken, {}); } else if (token == "wrbe_separate") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) { - log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename, line_number); } get_semi(); add_cap(port.wrbe_separate, {}); @@ -424,14 +424,14 @@ struct Parser { if (token == "tied") { get_token(); if (!is_rw) - log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename, line_number); while (peek_int()) def.wr_widths.push_back(get_int()); def.tied = true; } else if (token == "mix") { get_token(); if (!is_rw) - log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename, line_number); while (peek_int()) def.wr_widths.push_back(get_int()); def.rd_widths = def.wr_widths; @@ -439,7 +439,7 @@ struct Parser { } else if (token == "rd") { get_token(); if (!is_rw) - log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename, line_number); do { def.rd_widths.push_back(get_int()); } while (peek_int()); @@ -451,7 +451,7 @@ struct Parser { } else if (token == "wr") { get_token(); if (!is_rw) - log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename, line_number); do { def.wr_widths.push_back(get_int()); } while (peek_int()); @@ -470,12 +470,12 @@ struct Parser { add_cap(port.width, def); } else if (token == "rden") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename, line_number); get_semi(); add_cap(port.rden, {}); } else if (token == "rdwr") { if (port.kind != PortKind::Srsw) - log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename, line_number); RdWrKind kind; token = get_token(); if (token == "undefined") { @@ -489,13 +489,13 @@ struct Parser { } else if (token == "new_only") { kind = RdWrKind::NewOnly; } else { - log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdwr, kind); } else if (token == "rdinit") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); ResetValKind kind; token = get_token(); if (token == "none") { @@ -507,13 +507,13 @@ struct Parser { } else if (token == "no_undef") { kind = ResetValKind::NoUndef; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdinit, kind); } else if (token == "rdarst") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); ResetValKind kind; token = get_token(); if (token == "none") { @@ -527,13 +527,13 @@ struct Parser { } else if (token == "init") { kind = ResetValKind::Init; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdarst, kind); } else if (token == "rdsrst") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); SrstDef def; token = get_token(); if (token == "none") { @@ -547,7 +547,7 @@ struct Parser { } else if (token == "init") { def.val = ResetValKind::Init; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token); } if (def.val == ResetValKind::None) { def.kind = SrstKind::None; @@ -560,7 +560,7 @@ struct Parser { } else if (token == "gated_rden") { def.kind = SrstKind::GatedRdEn; } else { - log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename, line_number, token); } } def.block_wr = false; @@ -572,14 +572,14 @@ struct Parser { add_cap(port.rdsrst, def); } else if (token == "wrprio") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) - log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename, line_number); do { add_cap(port.wrprio, get_string()); } while (peek_string()); get_semi(); } else if (token == "wrtrans") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) - log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename, line_number); token = peek_token(); RawWrTransDef def; if (token == "all") { @@ -595,7 +595,7 @@ struct Parser { } else if (token == "old") { def.kind = WrTransKind::Old; } else { - log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.wrtrans, def); @@ -609,9 +609,9 @@ struct Parser { get_semi(); add_cap(port.optional_rw, {}); } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing port item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing port item.\n", filename, line_number); } else { - log_error("%s:%d: unknown port-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown port-level item `%s`.\n", filename, line_number, token); } } @@ -646,14 +646,14 @@ struct Parser { } else if (token == "abits") { int val = get_int(); if (val < 0) - log_error("%s:%d: abits %d nagative.\n", filename.c_str(), line_number, val); + log_error("%s:%d: abits %d nagative.\n", filename, line_number, val); get_semi(); add_cap(ram.abits, val); } else if (token == "width") { WidthsDef def; int w = get_int(); if (w <= 0) - log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w); + log_error("%s:%d: width %d not positive.\n", filename, line_number, w); def.widths.push_back(w); def.mode = WidthMode::Single; get_semi(); @@ -664,9 +664,9 @@ struct Parser { do { int w = get_int(); if (w <= 0) - log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w); + log_error("%s:%d: width %d not positive.\n", filename, line_number, w); if (w < last * 2) - log_error("%s:%d: width %d smaller than %d required for progression.\n", filename.c_str(), line_number, w, last * 2); + log_error("%s:%d: width %d smaller than %d required for progression.\n", filename, line_number, w, last * 2); last = w; def.widths.push_back(w); } while(peek_int()); @@ -676,7 +676,7 @@ struct Parser { } else if (token == "per_port") { def.mode = WidthMode::PerPort; } else { - log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(ram.widths, def); @@ -702,7 +702,7 @@ struct Parser { } else if (token == "byte") { int val = get_int(); if (val <= 0) - log_error("%s:%d: byte width %d not positive.\n", filename.c_str(), line_number, val); + log_error("%s:%d: byte width %d not positive.\n", filename, line_number, val); add_cap(ram.byte, val); get_semi(); } else if (token == "init") { @@ -717,7 +717,7 @@ struct Parser { } else if (token == "none") { kind = MemoryInitKind::None; } else { - log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(ram.init, kind); @@ -743,7 +743,7 @@ struct Parser { } else if (token == "srsw") { port.kind = PortKind::Srsw; } else { - log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename, line_number, token); } do { port.names.push_back(get_string()); @@ -752,9 +752,9 @@ struct Parser { if (active) add_cap(ram.ports, port); } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename, line_number); } else { - log_error("%s:%d: unknown ram-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown ram-level item `%s`.\n", filename, line_number, token); } } @@ -787,7 +787,7 @@ struct Parser { } else if (token == "huge") { ram.kind = RamKind::Huge; } else { - log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename, line_number, token); } ram.id = get_id(); parse_ram_block(); @@ -795,9 +795,9 @@ struct Parser { compile_ram(orig_line); } } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing top item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing top item.\n", filename, line_number); } else { - log_error("%s:%d: unknown top-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown top-level item `%s`.\n", filename, line_number, token); } } @@ -816,7 +816,7 @@ struct Parser { if (!opts_ok(cap.portopts, portopts)) continue; if (res) - log_error("%s:%d: duplicate %s cap.\n", filename.c_str(), line_number, name); + log_error("%s:%d: duplicate %s cap.\n", filename, line_number, name); res = &cap.val; } return res; @@ -860,7 +860,7 @@ struct Parser { } else { const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock"); if (!cdef) - log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line); + log_error("%s:%d: missing clock capability.\n", filename, orig_line); var.clk_pol = cdef->kind; if (cdef->name.empty()) { var.clk_shared = -1; @@ -876,7 +876,7 @@ struct Parser { } else { var.clk_shared = it->second; if (cram.shared_clocks[var.clk_shared].anyedge != anyedge) { - log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename.c_str(), orig_line, cdef->name.c_str()); + log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename, orig_line, cdef->name); } } } @@ -885,7 +885,7 @@ struct Parser { const PortWidthDef *wdef = find_single_cap(pdef.width, cram.options, portopts, "width"); if (wdef) { if (cram.width_mode != WidthMode::PerPort) - log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename.c_str(), orig_line); + log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename, orig_line); compile_widths(var, cram.dbits, *wdef); } else { var.width_tied = true; @@ -908,9 +908,9 @@ struct Parser { var.rdsrstmode = srv->kind; var.rdsrst_block_wr = srv->block_wr; if (srv->kind == SrstKind::GatedClkEn && !var.clk_en) - log_error("%s:%d: `gated_clken` used without `clken`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `gated_clken` used without `clken`.\n", filename, orig_line); if (srv->kind == SrstKind::GatedRdEn && !var.rd_en) - log_error("%s:%d: `gated_rden` used without `rden`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `gated_rden` used without `rden`.\n", filename, orig_line); } else { var.rdsrstval = ResetValKind::None; var.rdsrstmode = SrstKind::None; @@ -918,13 +918,13 @@ struct Parser { } if (var.rdarstval == ResetValKind::Init || var.rdsrstval == ResetValKind::Init) { if (var.rdinitval != ResetValKind::Any && var.rdinitval != ResetValKind::NoUndef) { - log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename.c_str(), orig_line); + log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename, orig_line); } } } var.wrbe_separate = find_single_cap(pdef.wrbe_separate, cram.options, portopts, "wrbe_separate"); if (var.wrbe_separate && cram.byte == 0) { - log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename, orig_line); } for (auto &def: pdef.wrprio) { if (!opts_ok(def.opts, cram.options)) @@ -948,18 +948,18 @@ struct Parser { grp.variants.push_back(var); } if (grp.variants.empty()) { - log_error("%s:%d: all port option combinations are forbidden.\n", filename.c_str(), orig_line); + log_error("%s:%d: all port option combinations are forbidden.\n", filename, orig_line); } cram.port_groups.push_back(grp); } void compile_ram(int orig_line) { if (ram.abits.empty()) - log_error("%s:%d: `dims` capability should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: `dims` capability should be specified.\n", filename, orig_line); if (ram.widths.empty()) - log_error("%s:%d: `widths` capability should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: `widths` capability should be specified.\n", filename, orig_line); if (ram.ports.empty()) - log_error("%s:%d: at least one port group should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: at least one port group should be specified.\n", filename, orig_line); for (auto opts: make_opt_combinations(ram.opts)) { bool forbidden = false; for (auto &fdef: ram.forbid) { @@ -1003,7 +1003,7 @@ struct Parser { const int *byte = find_single_cap(ram.byte, opts, Options(), "byte"); cram.byte = byte ? *byte : 0; if (GetSize(cram.dbits) - 1 > cram.abits) - log_error("%s:%d: abits %d too small for dbits progression.\n", filename.c_str(), line_number, cram.abits); + log_error("%s:%d: abits %d too small for dbits progression.\n", filename, line_number, cram.abits); validate_byte(widths->widths, cram.byte); const MemoryInitKind *ik = find_single_cap(ram.init, opts, Options(), "init"); cram.init = ik ? *ik : MemoryInitKind::None; @@ -1037,18 +1037,18 @@ struct Parser { if (widths[0] % byte == 0) { for (int j = 1; j < GetSize(widths); j++) if (widths[j] % byte != 0) - log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte); return; } for (int i = 0; i < GetSize(widths); i++) { if (widths[i] == byte) { for (int j = i + 1; j < GetSize(widths); j++) if (widths[j] % byte != 0) - log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte); return; } } - log_error("%s:%d: byte width %d invalid for dbits.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: byte width %d invalid for dbits.\n", filename, line_number, byte); } void compile_widths(PortVariant &var, const std::vector &widths, const PortWidthDef &width) { @@ -1073,13 +1073,13 @@ struct Parser { if (dbits[i] == widths[0]) { for (int j = 0; j < GetSize(widths); j++) { if (i+j >= GetSize(dbits) || dbits[i+j] != widths[j]) { - log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename.c_str(), line_number, widths[j]); + log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename, line_number, widths[j]); } } return {i, i + GetSize(widths) - 1}; } } - log_error("%s:%d: port width %d invalid for dbits.\n", filename.c_str(), line_number, widths[0]); + log_error("%s:%d: port width %d invalid for dbits.\n", filename, line_number, widths[0]); } void parse() { diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 9bc8ad9b0..8ef2c4271 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -369,7 +369,7 @@ struct rules_t attr_icase = false; if (infile.fail()) - log_error("Can't open rules file `%s'.\n", filename.c_str()); + log_error("Can't open rules file `%s'.\n", filename); while (next_line()) { @@ -1020,7 +1020,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals) log(" Properties:"); for (auto &it : match_properties) - log(" %s=%d", it.first.c_str(), it.second); + log(" %s=%d", it.first, it.second); log("\n"); pool> failed_brams; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 75c6e6a3a..916b21233 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -334,7 +334,7 @@ struct MemoryDffWorker void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str()); + log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, module->name); std::vector muxdata; SigSpec data = walk_muxes(port.data, muxdata); @@ -554,7 +554,7 @@ struct MemoryDffWorker void handle_rd_port_addr(Mem &mem, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port address `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str()); + log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, module->name); FfData ff; pool> bits; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 4c7d9636d..0fb4608b1 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -548,20 +548,20 @@ void MemMapping::determine_style() { // Nothing. } else if (val_s == "logic" || val_s == "registers") { kind = RamKind::Logic; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "distributed") { kind = RamKind::Distributed; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") { kind = RamKind::Block; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "huge" || val_s == "ultra") { kind = RamKind::Huge; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else { kind = RamKind::NotLogic; style = val_s; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid), val_s.c_str()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s); } return; } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 126ec65b5..cc8dce13e 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -192,7 +192,7 @@ struct MemoryMapWorker } } - log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str()); + log("Mapping memory %s in module %s:\n", mem.memid, module->name); int abits = ceil_log2(mem.size); std::vector data_reg_in(1 << abits); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index a19807f22..6a424952a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -371,9 +371,9 @@ struct MemoryShareWorker ports += std::to_string(idx); } if (!some_port.clk_enable) { - log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str()); + log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports); } else { - log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str()); + log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports); } // Okay, time to actually run the SAT solver. diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 620b38813..4dd5ba616 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -597,7 +597,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit) { if (verbose) - log("Finding unused cells or wires in module %s..\n", module->name.c_str()); + log("Finding unused cells or wires in module %s..\n", module->name); std::vector delcells; for (auto cell : module->cells()) diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 1625b86ea..97147fc48 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -99,7 +99,7 @@ struct OptLutWorker } for (int i = 0; i < GetSize(dlogic); i++) { - log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]); + log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]); } } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 6c81ee241..fbfdb9b63 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -228,7 +228,7 @@ struct OptMergeWorker ct.cell_types.erase(ID($allseq)); ct.cell_types.erase(ID($allconst)); - log("Finding identical cells in module `%s'.\n", module->name.c_str()); + log("Finding identical cells in module `%s'.\n", module->name); assign_map.set(module); initvals.set(&assign_map, module); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 809353f8c..2f7d26dcf 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -205,7 +205,7 @@ struct OptMuxtreeWorker OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module), removed_count(0) { - log("Running muxtree optimizer on module %s..\n", module->name.c_str()); + log("Running muxtree optimizer on module %s..\n", module->name); log(" Creating internal representation of mux trees.\n"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d27878fa7..6d6cadfe7 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -93,7 +93,7 @@ struct OptReduceWorker new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1; if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { - log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); + log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a)); did_something = true; total_count++; } @@ -155,7 +155,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::B, new_sig_b); @@ -242,7 +242,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size()) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::A, new_sig_a); @@ -308,7 +308,7 @@ struct OptReduceWorker if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0) return; - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; @@ -388,7 +388,7 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); if (cell->type != ID($bmux)) { log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); @@ -479,7 +479,7 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); @@ -515,7 +515,7 @@ struct OptReduceWorker OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) : design(design), module(module), assign_map(module) { - log(" Optimizing cells in module %s.\n", module->name.c_str()); + log(" Optimizing cells in module %s.\n", module->name); total_count = 0; did_something = true; diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 0ac391790..3a39570b4 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -64,7 +64,7 @@ struct RmportsPassPass : public Pass { void CleanupModule(Module *module, dict> &removed_ports) { - log("Removing now-unused cell ports in module %s\n", module->name.c_str()); + log("Removing now-unused cell ports in module %s\n", module->name); auto cells = module->cells(); for(auto cell : cells) @@ -88,7 +88,7 @@ struct RmportsPassPass : public Pass { void ScanModule(Module* module, dict> &removed_ports) { - log("Finding unconnected ports in module %s\n", module->name.c_str()); + log("Finding unconnected ports in module %s\n", module->name); pool used_ports; @@ -113,7 +113,7 @@ struct RmportsPassPass : public Pass { if( (w1 == NULL) || (w2 == NULL) ) continue; - //log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str()); + //log(" conn %s, %s\n", w1->name, w2->name); if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) ) used_ports.insert(w1->name); @@ -136,7 +136,7 @@ struct RmportsPassPass : public Pass { if(sig == NULL) continue; - // log(" sig %s\n", sig->name.c_str()); + // log(" sig %s\n", sig->name); if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) ) used_ports.insert(sig->name); } @@ -155,7 +155,7 @@ struct RmportsPassPass : public Pass { // Print the ports out as we go through them for(auto port : unused_ports) { - log(" removing unused port %s\n", port.c_str()); + log(" removing unused port %s\n", port); removed_ports[module->name].insert(port); // Remove from ports list diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 97c6f5600..d2adbbdd9 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -454,7 +454,7 @@ with open(outfile, "w") as f: print(" SigSpec port(Cell *cell, IdString portname) {", file=f) print(" try {", file=f) print(" return sigmap(cell->getPort(portname));", file=f) - print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname.c_str()); }", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f) print(" }", file=f) print("", file=f) print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f) @@ -465,7 +465,7 @@ with open(outfile, "w") as f: print(" Const param(Cell *cell, IdString paramname) {", file=f) print(" try {", file=f) print(" return cell->getParam(paramname);", file=f) - print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname.c_str()); }", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname); }", file=f) print(" }", file=f) print("", file=f) print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f) diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 3cd3f6fe4..92d8d0569 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -204,7 +204,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { if (edge_syncs.size() > 1) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; arst_syncs.push_back(sync); edge_syncs.erase(it); @@ -223,7 +223,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) sync->mem_write_actions.clear(); eliminate_const(mod, &proc->root_case, root_sig, polarity); } else { - log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); eliminate_const(mod, &proc->root_case, root_sig, !polarity); } did_something = true; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index b8bd74f50..19c2be4ca 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -171,7 +171,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool proc_clean_case(&proc->root_case, did_something, count, -1); } if (count > 0 && !quiet) - log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str()); + log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name, proc->name); total_count += count; } @@ -215,7 +215,7 @@ struct ProcCleanPass : public Pass { if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 && proc->root_case.actions.size() == 0) { if (!quiet) - log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str()); + log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name); delme.push_back(proc); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 7e3c56552..06c740a88 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -106,7 +106,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set cell->setPort(ID::CLK, clk); cell->setPort(ID::ALOAD, set); - log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), + log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name, clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); } @@ -136,9 +136,9 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT cell->setPort(ID::CLK, clk); if (!clk.empty()) - log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); + log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative"); else - log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str()); + log(" created %s cell `%s' with global clock", cell->type, cell->name); if (arst) log(" and %s level reset", arst_polarity ? "positive" : "negative"); log(".\n"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index f170dbf36..bda2d272f 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -404,7 +404,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) for (auto &bit : lhs) { State val = db.initvals(bit); if (db.initvals(bit) != State::Sx) { - log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str()); + log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name, log_signal(bit), db.module->name, proc->name); } db.initvals.remove_init(bit); } diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 817ced404..99cacf5fd 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -31,7 +31,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) for (auto &sync : proc->syncs) if (sync->type == RTLIL::SyncType::STi) { - log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str()); + log("Found init rule in `%s.%s'.\n", mod->name, proc->name); for (auto &action : sync->actions) { diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 21afdf134..68127d1bc 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -412,7 +412,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) { - log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str()); + log("Creating decoders for process `%s.%s'.\n", mod->name, proc->name); SigSnippets sigsnip; sigsnip.insert(&proc->root_case); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 7008e35e1..bde5e1ecb 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -87,7 +87,7 @@ struct BruteForceEquivChecker BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) : mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1) { - log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str()); + log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name, mod2->name); for (auto w : mod1->wires()) { if (w->port_id == 0) @@ -264,7 +264,7 @@ struct VlogHammerReporter if (!ce.eval(sig)) log_error("Can't read back value for port %s!\n", log_id(inputs[i])); input_pattern_list += stringf(" %s", sig.as_const().as_string()); - log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str()); + log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string()); } } @@ -280,7 +280,7 @@ struct VlogHammerReporter ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } - log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); + log("++VAL++ %d %s %s #\n", idx, module_name, sig.as_const().as_string()); if (module_name == "rtl") { rtl_sig = sig; @@ -294,7 +294,7 @@ struct VlogHammerReporter sig[i] = RTLIL::State::Sx; } - log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); + log("++RPT++ %d%s %s %s\n", idx, input_pattern_list, sig.as_const().as_string(), module_name); } log("++RPT++ ----\n"); @@ -307,8 +307,8 @@ struct VlogHammerReporter for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); if (design->module(esc_name) == nullptr) - log_error("Can't find module %s in current design!\n", name.c_str()); - log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); + log_error("Can't find module %s in current design!\n", name); + log("Using module %s (%s).\n", esc_name, name); modules.push_back(design->module(esc_name)); module_names.push_back(name); } @@ -319,15 +319,15 @@ struct VlogHammerReporter RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { if (mod->wire(esc_name) == nullptr) - log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name)); + log_error("Can't find input %s in module %s!\n", name, log_id(mod->name)); RTLIL::Wire *port = mod->wire(esc_name); if (!port->port_input || port->port_output) - log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name)); + log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name)); if (width >= 0 && width != port->width) - log_error("Port %s has different sizes in the different modules!\n", name.c_str()); + log_error("Port %s has different sizes in the different modules!\n", name); width = port->width; } - log("Using input port %s with width %d.\n", esc_name.c_str(), width); + log("Using input port %s with width %d.\n", esc_name, width); inputs.push_back(esc_name); input_widths.push_back(width); total_input_width += width; @@ -341,9 +341,9 @@ struct VlogHammerReporter pattern = pattern.substr(1); } if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const()) - log_error("Failed to parse pattern %s!\n", pattern.c_str()); + log_error("Failed to parse pattern %s!\n", pattern); if (sig.size() < total_input_width) - log_error("Pattern %s is to short!\n", pattern.c_str()); + log_error("Pattern %s is to short!\n", pattern); patterns.push_back(sig.as_const()); if (invert_pattern) { for (auto &bit : patterns.back().bits()) @@ -352,7 +352,7 @@ struct VlogHammerReporter else if (bit == RTLIL::State::S1) bit = RTLIL::State::S0; } - log("Using pattern %s.\n", patterns.back().as_string().c_str()); + log("Using pattern %s.\n", patterns.back().as_string()); } } }; @@ -415,9 +415,9 @@ struct EvalPass : public Pass { std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); if (design->module(mod1_name) == nullptr) - log_error("Can't find module `%s'!\n", mod1_name.c_str()); + log_error("Can't find module `%s'!\n", mod1_name); if (design->module(mod2_name) == nullptr) - log_error("Can't find module `%s'!\n", mod2_name.c_str()); + log_error("Can't find module `%s'!\n", mod2_name); BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivalent!\n"); @@ -574,7 +574,7 @@ struct EvalPass : public Pass { for (auto &row : tab) { for (size_t i = 0; i < row.size(); i++) { int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i; - log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str()); + log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k]); } log("\n"); if (first) { diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 547082164..4627a6c96 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -109,7 +109,7 @@ struct FminitPass : public Pass { SigSpec clksig; if (!clocksignal.empty()) { if (!SigSpec::parse(clksig, module, clocksignal)) - log_error("Error parsing expression '%s'.\n", clocksignal.c_str()); + log_error("Error parsing expression '%s'.\n", clocksignal); } for (auto &it : setdata) @@ -117,10 +117,10 @@ struct FminitPass : public Pass { SigSpec lhs, rhs; if (!SigSpec::parse(lhs, module, it.first)) - log_error("Error parsing expression '%s'.\n", it.first.c_str()); + log_error("Error parsing expression '%s'.\n", it.first); if (!SigSpec::parse_rhs(lhs, rhs, module, it.second)) - log_error("Error parsing expression '%s'.\n", it.second.c_str()); + log_error("Error parsing expression '%s'.\n", it.second); SigSpec final_lhs, final_rhs; @@ -144,7 +144,7 @@ struct FminitPass : public Pass { SigSpec lhs, rhs; if (!SigSpec::parse(lhs, module, it.first)) - log_error("Error parsing expression '%s'.\n", it.first.c_str()); + log_error("Error parsing expression '%s'.\n", it.first); for (int i = 0; i < GetSize(it.second); i++) { @@ -183,7 +183,7 @@ struct FminitPass : public Pass { SigSpec final_lhs, final_rhs; if (!SigSpec::parse_rhs(lhs, rhs, module, it.second[i])) - log_error("Error parsing expression '%s'.\n", it.second[i].c_str()); + log_error("Error parsing expression '%s'.\n", it.second[i]); for (int i = 0; i < GetSize(rhs); i++) if (rhs[i] != State::Sz) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 870df7b55..4b0669c25 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -247,7 +247,7 @@ struct PerformReduction string loop_signals; for (auto loop_bit : recursion_guard) loop_signals += string(" ") + log_signal(loop_bit); - log_error("Found logic loop:%s\n", loop_signals.c_str()); + log_error("Found logic loop:%s\n", loop_signals); } recursion_guard.insert(out); @@ -596,7 +596,7 @@ struct FreduceWorker void dump() { std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); - log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str()); + log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); } diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 7aef9ea38..58d932f20 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -539,7 +539,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena std::ofstream sout; sout.open(srcsfile, std::ios::out | std::ios::trunc); if (!sout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str()); + log_error("Could not open file \"%s\" with write access.\n", srcsfile); sources.sort(); for (auto &s : sources) sout << s << std::endl; @@ -550,7 +550,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena if (!filename.empty()) { fout.open(filename, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", filename.c_str()); + log_error("Could not open file \"%s\" with write access.\n", filename); } int ctrl_value = opts.ctrl_value; @@ -561,7 +561,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++); str += " -mode none"; if (filename.empty()) - log("%s\n", str.c_str()); + log("%s\n", str); else fout << str << std::endl; } @@ -588,7 +588,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena for (auto &s : entry.src) str += stringf(" -src %s", s); if (filename.empty()) - log("%s\n", str.c_str()); + log("%s\n", str); else fout << str << std::endl; } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index c7ddb9168..20cee7956 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -122,7 +122,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { for (auto &it : hole_assignments) { RTLIL::SigSpec lhs(it.first); RTLIL::SigSpec rhs(it.second); - log("Specializing %s from file with %s = %d.\n", module->name.c_str(), log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0); + log("Specializing %s from file with %s = %d.\n", module->name, log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0); module->connect(lhs, rhs); } } @@ -151,7 +151,7 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet = RTLIL::SigSpec lhs(hole_sigbit.wire, hole_sigbit.offset, 1); RTLIL::State hole_bit_val = hole_value[bit_idx] == '1'? RTLIL::State::S1 : RTLIL::State::S0; if (!quiet) - log("Specializing %s with %s = %d.\n", module->name.c_str(), log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1) + log("Specializing %s with %s = %d.\n", module->name, log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1) ; module->connect(lhs, hole_bit_val); } @@ -168,7 +168,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool &input_wi allconst->setPort(ID::Y, input); allconst->set_src_attribute(input->get_src_attribute()); input->port_input = false; - log("Replaced input %s with $allconst cell.\n", n.c_str()); + log("Replaced input %s with $allconst cell.\n", n); } module->fixup_ports(); } @@ -184,7 +184,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) { else { log("Adding $assume cell for output(s): "); for (auto w : wires_to_assume) - log("\"%s\" ", w->name.c_str()); + log("\"%s\" ", w->name); log("\n"); } @@ -236,10 +236,10 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str()); else if (opt.show_smtbmc && !quiet) - log("smtbmc output: %s", line.c_str()); + log("smtbmc output: %s", line); }; log_header(mod->design, "Solving QBF-SAT problem.\n"); - if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd.c_str()); + if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd); int64_t begin = PerformanceTimer::query(); run_command(smtbmc_cmd, process_line); int64_t end = PerformanceTimer::query(); @@ -303,7 +303,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { log_assert(wire_to_optimize_name != ""); log_assert(module->wire(wire_to_optimize_name) != nullptr); - log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name.c_str()); + log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name); //If maximizing, grow until we get a failure. Then bisect success and failure. while (failure == 0 || difference(success, failure) > 1) { @@ -316,7 +316,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { : module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1)); - log("Trying to solve with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), cur_thresh); + log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh); } ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num); @@ -337,7 +337,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { log_assert(value.is_fully_const()); success = value.as_const().as_int(); best_soln = ret; - log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name.c_str(), success); + log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name, success); Pass::call(design, "design -pop"); module = design->module(module_name); @@ -355,7 +355,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { break; } else - log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), failure); + log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), failure); } iter_num++; @@ -367,7 +367,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { cur_thresh = (success + failure) / 2; //bisection } if (success != 0 || failure != 0) { - log("Wire %s is %s at %d.\n", wire_to_optimize_name.c_str(), (maximize? "maximized" : "minimized"), success); + log("Wire %s is %s at %d.\n", wire_to_optimize_name, (maximize? "maximized" : "minimized"), success); ret = best_soln; } } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 60e099097..967cb0472 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -652,9 +652,9 @@ struct SatHelper log(" "); if (info.width <= 32 && !found_undef) - log("%-*s %11d %9x %*s\n", maxModelName+5, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+3, value.as_string().c_str()); + log("%-*s %11d %9x %*s\n", maxModelName+5, info.description, value.as_int(), value.as_int(), maxModelWidth+3, value.as_string()); else - log("%-*s %11s %9s %*s\n", maxModelName+5, info.description.c_str(), "--", "--", maxModelWidth+3, value.as_string().c_str()); + log("%-*s %11s %9s %*s\n", maxModelName+5, info.description, "--", "--", maxModelWidth+3, value.as_string()); } if (last_timestep == -2) @@ -668,7 +668,7 @@ struct SatHelper if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); - log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str()); + log("Dumping SAT model to VCD file %s\n", vcd_file_name); time_t timestamp; struct tm* now; @@ -772,7 +772,7 @@ struct SatHelper if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno)); - log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name.c_str()); + log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name); int mintime = 1, maxtime = 0, maxwidth = 0;; dict>> wavedata; @@ -1530,7 +1530,7 @@ struct SatPass : public Pass { if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); - log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); inductstep.ez->printDIMACS(f, false); @@ -1634,7 +1634,7 @@ struct SatPass : public Pass { if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); - log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); sathelper.ez->printDIMACS(f, false); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 044bd8acb..0510bc7df 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -60,10 +60,10 @@ static double stringToTime(std::string str) long value = strtol(str.c_str(), &endptr, 10); if (g_units.find(endptr)==g_units.end()) - log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr); + log_error("Cannot parse '%s', bad unit '%s'\n", str, endptr); if (value < 0) - log_error("Time value '%s' must be positive\n", str.c_str()); + log_error("Time value '%s' must be positive\n", str); return value * pow(10.0, g_units.at(endptr)); } @@ -430,7 +430,7 @@ struct SimInstance value.bits().push_back(State::Sz); if (shared->debug) - log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); return value; } @@ -449,7 +449,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value)); return did_something; } @@ -551,7 +551,7 @@ struct SimInstance if (has_y) sig_y = cell->getPort(ID::Y); if (shared->debug) - log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type)); + log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type)); // Simple (A -> Y) and (A,B -> Y) cells if (has_a && !has_c && !has_d && !has_s && has_y) { @@ -793,14 +793,14 @@ struct SimInstance static void log_source(RTLIL::AttrObject *src) { for (auto src : src->get_strpool_attribute(ID::src)) - log(" %s\n", src.c_str()); + log(" %s\n", src); } void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell) { log_assert(cell->module == module); bool has_src = cell->has_attribute(ID::src); - log("%s %s%s\n", opening_verbiage.c_str(), + log("%s %s%s\n", opening_verbiage, log_id(cell), has_src ? " at" : ""); log_source(cell); @@ -894,7 +894,7 @@ struct SimInstance } std::string rendered = print.fmt.render(); - log("%s", rendered.c_str()); + log("%s", rendered); shared->display_output.emplace_back(shared->step, this, cell, rendered); } } @@ -921,15 +921,15 @@ struct SimInstance } if (cell->type == ID($cover) && en == State::S1 && a == State::S1) - log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str()); + log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label); if (cell->type == ID($assume) && en == State::S1 && a != State::S1) - log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label); if (cell->type == ID($assert) && en == State::S1 && a != State::S1) { log_cell_w_hierarchy("Failed assertion", cell); if (shared->serious_asserts) - log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); else log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); } @@ -952,7 +952,7 @@ struct SimInstance { if (!ff_database.empty() || !mem_database.empty()) { if (wbmods.count(module)) - log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module)); + log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module)); wbmods.insert(module); } @@ -1192,7 +1192,7 @@ struct SimInstance } } if (!found) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name))); } } } @@ -1478,7 +1478,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); } for (auto portname : clockn) @@ -1490,7 +1490,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); } @@ -1500,7 +1500,7 @@ struct SimWorker : SimShared if (wire->port_input) { fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); top->fst_inputs[wire] = id; } } @@ -1623,9 +1623,9 @@ struct SimWorker : SimShared else if (type == "latch") mem_latches[variable] = { memid, offset }; else - log_error("Map file addressing cell %s as type %s\n", symbol.c_str(), type.c_str()); + log_error("Map file addressing cell %s as type %s\n", symbol, type); } else { - log_error("Cell %s in map file is not memory cell\n", symbol.c_str()); + log_error("Cell %s in map file is not memory cell\n", symbol); } } else { if (index < w->start_offset || index > w->start_offset + w->width) @@ -1645,7 +1645,7 @@ struct SimWorker : SimShared std::ifstream f; f.open(sim_filename.c_str()); if (f.fail() || GetSize(sim_filename) == 0) - log_error("Can not open file `%s`\n", sim_filename.c_str()); + log_error("Can not open file `%s`\n", sim_filename); int state = 0; std::string status; @@ -1729,7 +1729,7 @@ struct SimWorker : SimShared if (pos==std::string::npos) { pos = name.find_first_of("#"); if (pos==std::string::npos) - log_error("Line does not contain proper signal name `%s`\n", name.c_str()); + log_error("Line does not contain proper signal name `%s`\n", name); } return name.substr(0, pos); } @@ -1744,7 +1744,7 @@ struct SimWorker : SimShared std::ifstream f; f.open(sim_filename.c_str()); if (f.fail() || GetSize(sim_filename) == 0) - log_error("Can not open file `%s`\n", sim_filename.c_str()); + log_error("Can not open file `%s`\n", sim_filename); int state = 0; int cycle = 0; @@ -1874,7 +1874,7 @@ struct SimWorker : SimShared if (item.wire != nullptr) { if (paths.count(path)) { if (debug) - log("witness hierarchy: found wire %s\n", path.str().c_str()); + log("witness hierarchy: found wire %s\n", path.str()); bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second; if (!inserted) log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); @@ -1883,7 +1883,7 @@ struct SimWorker : SimShared auto it = mem_paths.find(path); if (it != mem_paths.end()) { if (debug) - log("witness hierarchy: found mem %s\n", path.str().c_str()); + log("witness hierarchy: found mem %s\n", path.str()); IdPath word_path = path; word_path.emplace_back(); for (auto addr_part : it->second) { @@ -1951,7 +1951,7 @@ struct SimWorker : SimShared Const value = yw.get_bits(t, signal.bits_offset, signal.width); if (debug) - log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value)); + log("yw: set %s to %s\n", signal.path.str(), log_const(value)); if (found_path.wire != nullptr) { found_path.instance->set_state_parent_drivers( @@ -2052,7 +2052,7 @@ struct SimWorker : SimShared PrettyJson json; if (!json.write_to_file(summary_filename)) - log_error("Can't open file `%s' for writing: %s\n", summary_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", summary_filename, strerror(errno)); json.begin_object(); json.entry("version", "Yosys sim summary"); @@ -2134,7 +2134,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); clocks[w] = id; } @@ -2147,7 +2147,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); clocks[w] = id; } @@ -2159,7 +2159,7 @@ struct SimWorker : SimShared for (auto wire : topmod->wires()) { fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0 && (wire->port_input || wire->port_output)) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); if (wire->port_input) if (clocks.find(wire)==clocks.end()) inputs[wire] = id; @@ -2236,7 +2236,7 @@ struct SimWorker : SimShared f << "\n"; f << "\tinteger i;\n"; uint64_t prev_time = startCount; - log("Writing data to `%s`\n", (tb_filename+".txt").c_str()); + log("Writing data to `%s`\n", (tb_filename+".txt")); std::ofstream data_file(tb_filename+".txt"); std::stringstream initstate; unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX; @@ -2292,7 +2292,7 @@ struct SimWorker : SimShared f << "\tend\n"; f << "endmodule\n"; - log("Writing testbench to `%s`\n", (tb_filename+".v").c_str()); + log("Writing testbench to `%s`\n", (tb_filename+".v")); std::ofstream tb_file(tb_filename+".v"); tb_file << f.str(); diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 4703e4ad7..d94b4a7f7 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -170,7 +170,7 @@ void SynthPropWorker::run() std::ofstream fout; fout.open(map_file, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", map_file.c_str()); + log_error("Could not open file \"%s\" with write access.\n", map_file); for (auto name : tracing_data[module].names) { fout << name << std::endl; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d45a652fc..7d81b52d2 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -751,7 +751,7 @@ struct abc_output_filter return; } if (ch == '\n') { - log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str()); + log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -936,7 +936,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab std::string buffer = stringf("%s/abc.script", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, "%s\n", abc_script.c_str()); fclose(f); @@ -991,7 +991,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/input.blif", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, ".model netlist\n"); @@ -1118,7 +1118,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/stdcells.genlib", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_))); @@ -1163,14 +1163,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); for (int i = 0; i < GetSize(config.lut_costs); i++) fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i)); fclose(f); } buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); - log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str()); + log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); #ifndef YOSYS_LINK_ABC abc_output_filter filt(*this, tempdir_name, config.show_tempdir); @@ -1220,7 +1220,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab temp_stdouterr_r.close(); #endif if (ret != 0) { - log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); return; } did_run_abc = true; @@ -1239,7 +1239,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) - log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); + log_error("Can't open ABC output file `%s'.\n", buffer); bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; @@ -1490,7 +1490,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL cell_stats.sort(); for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); + log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second); int in_wires = 0, out_wires = 0; for (auto &si : signal_list) if (si.is_port) { @@ -1582,7 +1582,7 @@ struct AbcPass : public Pass { #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -1597,41 +1597,41 @@ struct AbcPass : public Pass { log(" if no -script parameter is given, the following scripts are used:\n"); log("\n"); log(" for -liberty/-genlib without -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB)); log("\n"); log(" for -liberty/-genlib with -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR)); log("\n"); log(" for -lut/-luts (only one LUT size):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}")); log("\n"); log(" for -lut/-luts (different LUT sizes):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT)); log("\n"); log(" for -sop:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP)); log("\n"); log(" otherwise:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL)); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); log("\n"); log(" for -liberty/-genlib without -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB)); log("\n"); log(" for -liberty/-genlib with -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR)); log("\n"); log(" for -lut/-luts:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT)); log("\n"); log(" for -sop:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP)); log("\n"); log(" otherwise:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL)); log("\n"); log(" -liberty \n"); log(" generate netlists for the specified cell library (using the liberty\n"); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b79d9dc96..2cf28f849 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -106,7 +106,7 @@ struct Abc9Pass : public ScriptPass #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -119,12 +119,12 @@ struct Abc9Pass : public ScriptPass log(" replaced with blanks before the string is passed to ABC.\n"); log("\n"); log(" if no -script parameter is given, the following scripts are used:\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos))); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos))); log("\n"); log(" -D \n"); log(" set delay target. the string {D} in the default scripts above is\n"); diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 34348fd00..d7a7e3d4a 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -140,7 +140,7 @@ struct abc9_output_filter return; } if (ch == '\n') { - log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str()); + log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -271,14 +271,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == NULL) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); for (int i = 0; i < GetSize(lut_costs); i++) fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i)); fclose(f); } buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name); - log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); + log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir)); #ifndef YOSYS_LINK_ABC abc9_output_filter filt(tempdir_name, show_tempdir); @@ -331,7 +331,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe if (check_file_exists(stringf("%s/output.aig", tempdir_name))) log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); else - log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); } } @@ -352,7 +352,7 @@ struct Abc9ExePass : public Pass { #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -365,12 +365,12 @@ struct Abc9ExePass : public Pass { log(" replaced with blanks before the string is passed to ABC.\n"); log("\n"); log(" if no -script parameter is given, the following scripts are used:\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos))); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos))); log("\n"); log(" -constr \n"); log(" pass this file with timing constraints to ABC.\n"); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 85a1099ed..91149ac55 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -787,7 +787,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (auto cell_name : it) { auto cell = module->cell(cell_name); log_assert(cell); - log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str()); + log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute()); } } } @@ -1444,7 +1444,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) } for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); + log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second); int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 7f5bfc94f..58ac25f51 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -130,14 +130,14 @@ void attrmap_apply(string objname, vector> &actio goto delete_this_attr; if (new_attr != attr) - log("Changed attribute on %s: %s=%s -> %s=%s\n", objname.c_str(), + log("Changed attribute on %s: %s=%s -> %s=%s\n", objname, log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second)); new_attributes[new_attr.first] = new_attr.second; if (0) delete_this_attr: - log("Removed attribute on %s: %s=%s\n", objname.c_str(), log_id(attr.first), log_const(attr.second)); + log("Removed attribute on %s: %s=%s\n", objname, log_id(attr.first), log_const(attr.second)); } attributes.swap(new_attributes); diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index a7b96a9c6..7003c6656 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -257,14 +257,14 @@ struct ClkbufmapPass : public Pass { RTLIL::Cell *cell = nullptr; bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top); if (!buf_celltype.empty() && (!is_input || buffer_inputs)) { - log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i); + log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i); cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); iwire = module->addWire(NEW_ID); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); } if (is_input) { - log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); + log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i); RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); if (iwire) { cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 508e66d23..b834b8f35 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -81,7 +81,7 @@ static std::pair, std::optional> } else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) { clk_pol = false; } else { - log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str()); + log("Ignoring ICG primitive %s of kind '%s'\n", cell_name, icg_kind); continue; } @@ -176,11 +176,11 @@ static std::pair, std::optional> std::optional pos; std::optional neg; if (best_pos) { - log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str()); + log("Selected rising edge ICG %s from Liberty file\n", best_pos->name); pos.emplace(*best_pos); } if (best_neg) { - log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str()); + log("Selected falling edge ICG %s from Liberty file\n", best_neg->name); neg.emplace(*best_neg); } return std::make_pair(pos, neg); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 9dfc20896..facea2e90 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1111,7 +1111,7 @@ struct DffLegalizePass : public Pass { pol_r = celltype[13]; } else { unrecognized: - log_error("unrecognized cell type %s.\n", celltype.c_str()); + log_error("unrecognized cell type %s.\n", celltype); } int mask = 0; int match = 0; @@ -1140,12 +1140,12 @@ unrecognized: initmask = 0x555; } else if (inittype == "r") { if (srval == 0) - log_error("init type r not valid for cell type %s.\n", celltype.c_str()); + log_error("init type r not valid for cell type %s.\n", celltype); initmask = 0x537; } else if (inittype == "01") { initmask = 0x777; } else { - log_error("unrecognized init type %s for cell type %s.\n", inittype.c_str(), celltype.c_str()); + log_error("unrecognized init type %s for cell type %s.\n", inittype, celltype); } if (srval == '0') { initmask &= 0x0ff; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 70d0f4ef5..062a63ec3 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -36,9 +36,9 @@ static std::map cell_mappings; static void logmap(IdString dff) { if (cell_mappings.count(dff) == 0) { - log(" unmapped dff cell: %s\n", dff.c_str()); + log(" unmapped dff cell: %s\n", dff); } else { - log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str()); + log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1)); bool first = true; for (auto &port : cell_mappings[dff].ports) { char arg[3] = { port.second, 0, 0 }; @@ -46,7 +46,7 @@ static void logmap(IdString dff) arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~'; else arg[1] = arg[0], arg[0] = ' '; - log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg); + log("%s.%s(%s)", first ? "" : ", ", port.first, arg); first = false; } log(");\n"); @@ -488,7 +488,7 @@ static void find_cell_sr(std::vector cells, IdString cell_ty static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) { - log("Mapping DFF cells in module `%s':\n", module->name.c_str()); + log("Mapping DFF cells in module `%s':\n", module->name); dict> notmap; SigMap sigmap(module); @@ -690,7 +690,7 @@ struct DfflibmapPass : public Pass { dfflegalize_cmd += stringf(" -cell %s 01", it.first); dfflegalize_cmd += " t:$_DFF* t:$_SDFF*"; if (info_mode) { - log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str()); + log("dfflegalize command line: %s\n", dfflegalize_cmd); } else { Pass::call(design, dfflegalize_cmd); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index ea6ba5ddb..6527b683e 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -627,7 +627,7 @@ struct ExtractPass : public Pass { for (auto module : map->modules()) { SubCircuit::Graph mod_graph; std::string graph_name = "needle_" + RTLIL::unescape_id(module->name); - log("Creating needle graph %s.\n", graph_name.c_str()); + log("Creating needle graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports)) { solver.addGraph(graph_name, mod_graph); needle_map[graph_name] = module; @@ -638,7 +638,7 @@ struct ExtractPass : public Pass { for (auto module : design->modules()) { SubCircuit::Graph mod_graph; std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name); - log("Creating haystack graph %s.\n", graph_name.c_str()); + log("Creating haystack graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) { solver.addGraph(graph_name, mod_graph); haystack_map[graph_name] = module; @@ -654,7 +654,7 @@ struct ExtractPass : public Pass { for (auto needle : needle_list) for (auto &haystack_it : haystack_map) { - log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str()); + log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first); solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false); } log("Found %d matches.\n", GetSize(results)); @@ -665,11 +665,11 @@ struct ExtractPass : public Pass { for (int i = 0; i < int(results.size()); i++) { auto &result = results[i]; - log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str()); + log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId, result.haystackGraphId); for (const auto &it : result.mappings) { - log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str()); + log(" %s -> %s", it.first, it.second.haystackNodeId); for (const auto & it2 : it.second.portMapping) - log(" %s:%s", it2.first.c_str(), it2.second.c_str()); + log(" %s:%s", it2.first, it2.second); log("\n"); } RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result); @@ -693,7 +693,7 @@ struct ExtractPass : public Pass { log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits); log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name)); for (auto &node : result.nodes) - log(" %s", RTLIL::unescape_id(node.nodeId).c_str()); + log(" %s", RTLIL::unescape_id(node.nodeId)); log("\n"); for (auto &it : result.matchesPerGraph) log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second); @@ -744,7 +744,7 @@ struct ExtractPass : public Pass { rewrite_filename(mine_outfile); f.open(mine_outfile.c_str(), std::ofstream::trunc); if (f.fail()) - log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); + log_error("Can't open output file `%s'.\n", mine_outfile); Backend::backend_call(map, &f, mine_outfile, "rtlil"); f.close(); } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index b780f7df0..c45792f66 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -847,7 +847,7 @@ struct ExtractCounterPass : public Pass { else if (arg == "no") settings.allow_arst = false; else - log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str()); + log_error("Invalid -allow_arst value \"%s\"\n", arg); continue; } @@ -861,7 +861,7 @@ struct ExtractCounterPass : public Pass { else if (arg == "both") settings.allowed_dirs = 2; else - log_error("Invalid -dir value \"%s\"\n", arg.c_str()); + log_error("Invalid -dir value \"%s\"\n", arg); continue; } } @@ -893,7 +893,7 @@ struct ExtractCounterPass : public Pass { for(auto cpair : cells_to_rename) { - //log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second.c_str()); + //log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second); module->rename(cpair.first, cpair.second); } } diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 892e9a364..1ad880be0 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -133,7 +133,7 @@ struct ExtractReducePass : public Pass else continue; - log("Working on cell %s...\n", cell->name.c_str()); + log("Working on cell %s...\n", cell->name); // If looking for a single chain, follow linearly to the sink pool sinks; @@ -220,7 +220,7 @@ struct ExtractReducePass : public Pass //We have our list, go act on it for(auto head_cell : sinks) { - log(" Head cell is %s\n", head_cell->name.c_str()); + log(" Head cell is %s\n", head_cell->name); //Avoid duplication if we already were covered if(consumed_cells.count(head_cell)) diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 48d9600fa..5050e1464 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass { RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype)); icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i)); icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]); - log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i); + log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i); sig[i] = SigBit(iwire, i); } cell->setPort(port.first, sig); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 61966195c..7fbe54849 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -598,7 +598,7 @@ struct FlowmapWorker continue; if (!cell->known()) - log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell)); + log_error("Cell %s (%s.%s) is unknown.\n", cell->type, log_id(module), log_id(cell)); pool fanout; for (auto conn : cell->connections()) diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 322eb7779..d929de300 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -324,7 +324,7 @@ struct IopadmapPass : public Pass { if (wire->port_input) { - log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str()); + log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype); Cell *cell = module->addCell( module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), @@ -348,7 +348,7 @@ struct IopadmapPass : public Pass { if (!tinoutpad_portname_pad.empty()) rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad)); } else { - log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str()); + log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype); Cell *cell = module->addCell( module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), @@ -421,7 +421,7 @@ struct IopadmapPass : public Pass { continue; } - log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); + log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype); if (flag_bits) { diff --git a/passes/techmap/libcache.cc b/passes/techmap/libcache.cc index e299f43ec..c833a6046 100644 --- a/passes/techmap/libcache.cc +++ b/passes/techmap/libcache.cc @@ -117,9 +117,9 @@ if (list) { log("Caching is %s by default.\n", LibertyAstCache::instance.cache_by_default ? "enabled" : "disabled"); for (auto const &entry : LibertyAstCache::instance.cache_path) - log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first.c_str()); + log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first); for (auto const &entry : LibertyAstCache::instance.cached) - log("Data for `%s' is currently cached.\n", entry.first.c_str()); + log("Data for `%s' is currently cached.\n", entry.first); } else if (enable || disable) { if (all) { LibertyAstCache::instance.cache_by_default = enable; diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index b60e0b84b..c89495c62 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -42,7 +42,7 @@ std::shared_ptr LibertyAstCache::cached_ast(const std::string if (it == cached.end()) return nullptr; if (verbose) - log("Using cached data for liberty file `%s'\n", fname.c_str()); + log("Using cached data for liberty file `%s'\n", fname); return it->second; } @@ -53,7 +53,7 @@ void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr if (!should_cache) return; if (verbose) - log("Caching data for liberty file `%s'\n", fname.c_str()); + log("Caching data for liberty file `%s'\n", fname); cached.emplace(fname, ast); } @@ -671,7 +671,7 @@ void LibertyParser::error(const std::string &str) const std::stringstream ss; ss << "Syntax error in liberty file on line " << line << ".\n"; ss << " " << str << "\n"; - log_error("%s", ss.str().c_str()); + log_error("%s", ss.str()); } #else diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index ee0f3db42..44b5d3d47 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -204,7 +204,7 @@ namespace Yosys } ast = shared_ast.get(); if (!ast) { - log_error("No entries found in liberty file `%s'.\n", fname.c_str()); + log_error("No entries found in liberty file `%s'.\n", fname); } } #endif diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index dd82958fa..2a22258b7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -247,7 +247,7 @@ struct TechmapWorker portname = positional_ports.at(portname); if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { if (portname.begins_with("$")) - log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname, cell->name, tpl->name); continue; } @@ -562,7 +562,7 @@ struct TechmapWorker if (extmapper_name == "wrap") { std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); - log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + log("Running \"%s\" on wrapper %s.\n", cmd_string, log_id(extmapper_module)); mkdebug.on(); Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); log_continue = true; @@ -580,7 +580,7 @@ struct TechmapWorker auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); } @@ -589,7 +589,7 @@ struct TechmapWorker auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); @@ -951,7 +951,7 @@ struct TechmapWorker auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc index 588a40806..7233e78fa 100644 --- a/passes/tests/raise_error.cc +++ b/passes/tests/raise_error.cc @@ -85,7 +85,7 @@ struct RaiseErrorPass : public Pass { if (use_stderr) { std::cerr << err_msg << std::endl; } else { - log_error("%s\n", err_msg.c_str()); + log_error("%s\n", err_msg); } } diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index bcaf097a1..52cb8e28c 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -109,7 +109,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s continue; int count_ports = 0; - log("Generating test bench for module `%s'.\n", mod->name.c_str()); + log("Generating test bench for module `%s'.\n", mod->name); for (auto wire : mod->wires()) { if (wire->port_output) { count_ports++; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index a08a6ec29..286ef757d 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -722,7 +722,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: } if (verbose) - log("EVAL: %s\n", out_val.as_string().c_str()); + log("EVAL: %s\n", out_val.as_string()); if (!nosat) { diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index 50710e2bd..2b2249596 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -298,7 +298,7 @@ struct Coolrunner2FixupPass : public Pass { if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) || (sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell)) { - log("Buffering input to \"%s\"\n", cell->name.c_str()); + log("Buffering input to \"%s\"\n", cell->name); auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str()); @@ -320,7 +320,7 @@ struct Coolrunner2FixupPass : public Pass { if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock]) { - log("Buffering clock to \"%s\"\n", cell->name.c_str()); + log("Buffering clock to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, clock); @@ -338,7 +338,7 @@ struct Coolrunner2FixupPass : public Pass { { if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set]) { - log("Buffering set to \"%s\"\n", cell->name.c_str()); + log("Buffering set to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, set); @@ -352,7 +352,7 @@ struct Coolrunner2FixupPass : public Pass { { if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset]) { - log("Buffering reset to \"%s\"\n", cell->name.c_str()); + log("Buffering reset to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, reset); @@ -369,7 +369,7 @@ struct Coolrunner2FixupPass : public Pass { ce = sigmap(cell->getPort(ID(CE))[0]); if (!sig_fed_by_pterm[ce]) { - log("Buffering clock enable to \"%s\"\n", cell->name.c_str()); + log("Buffering clock enable to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, ce); @@ -389,7 +389,7 @@ struct Coolrunner2FixupPass : public Pass { if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) || packed_reg_out[input]) { - log("Buffering input to \"%s\"\n", cell->name.c_str()); + log("Buffering input to \"%s\"\n", cell->name); auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str()); @@ -404,7 +404,7 @@ struct Coolrunner2FixupPass : public Pass { oe = sigmap(cell->getPort(ID::E)[0]); if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe]) { - log("Buffering output enable to \"%s\"\n", cell->name.c_str()); + log("Buffering output enable to \"%s\"\n", cell->name); auto pterm_to_oe_wire = makeptermbuffer(module, oe); diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 955860740..0d07e2522 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -46,12 +46,12 @@ static void run_ice40_braminit(Module *module) continue; /* Open file */ - log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str()); + log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file); std::ifstream f; f.open(init_file.c_str()); if (f.fail()) { - log("Can not open file `%s`.\n", init_file.c_str()); + log("Can not open file `%s`.\n", init_file); continue; } diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index cbd05cb3e..8a13c4325 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -294,7 +294,7 @@ struct MicrochipDffOptPass : public Pass { ports += " + S"; if (worthy_post_ce) ports += " + CE"; - log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); // Okay, we're doing it. Unmap ports. diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index edd906048..bca3deef9 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -305,7 +305,7 @@ unmap: if (worthy_post_r) ports += " + R"; if (worthy_post_s) ports += " + S"; if (worthy_post_ce) ports += " + CE"; - log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); // Okay, we're doing it. Unmap ports. if (worthy_post_r) { From 727998f6635fc4cd6142d12a41fccedd47be3675 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 12 Sep 2025 00:22:43 +0000 Subject: [PATCH 055/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5da8066db..a22f3fb00 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+52 +YOSYS_VER := 0.57+55 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From b98e54416f912c9e723f2b72084322d560240f92 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 05:29:22 +0000 Subject: [PATCH 056/188] When looking up the IdString table, it can never be empty after we've called prepopulate, so remove some dead code. --- kernel/rtlil.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 9112ae64b..fc0087442 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -230,11 +230,6 @@ struct RTLIL::IdString #ifndef YOSYS_NO_IDS_REFCNT if (global_free_idx_list_.empty()) { - if (global_id_storage_.empty()) { - global_refcount_storage_.push_back(0); - global_id_storage_.push_back((char*)""); - global_id_index_[global_id_storage_.back()] = 0; - } log_assert(global_id_storage_.size() < 0x40000000); global_free_idx_list_.push_back(global_id_storage_.size()); global_id_storage_.push_back(nullptr); @@ -247,10 +242,6 @@ struct RTLIL::IdString global_id_index_[global_id_storage_.at(idx)] = idx; global_refcount_storage_.at(idx)++; #else - if (global_id_storage_.empty()) { - global_id_storage_.push_back((char*)""); - global_id_index_[global_id_storage_.back()] = 0; - } int idx = global_id_storage_.size(); global_id_storage_.push_back(strdup(p)); global_id_index_[global_id_storage_.back()] = idx; From 6f0c8f56a3f9ce6dfadd4a483435d0388f5f83ad Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 05:50:18 +0000 Subject: [PATCH 057/188] Convert btorf()/infof() to C++ stringf machinery --- backends/btor/btor.cc | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index c2b831a44..aa95c512e 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -102,20 +102,16 @@ struct BtorWorker PrettyJson ywmap_json; - void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3)) + template + void btorf(FmtString...> fmt, const Args &... args) { - va_list ap; - va_start(ap, fmt); - f << indent << vstringf(fmt, ap); - va_end(ap); + f << indent << fmt.format(args...); } - void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3)) + template + void infof(FmtString...> fmt, const Args &... args) { - va_list ap; - va_start(ap, fmt); - info_lines.push_back(vstringf(fmt, ap)); - va_end(ap); + info_lines.push_back(fmt.format(args...)); } template From ff5177ce8e5255dd34a9af770878da937864aa4f Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 05:53:59 +0000 Subject: [PATCH 058/188] Remove .c_str() from parameters to btorf() and infof() --- backends/btor/btor.cc | 60 +++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index aa95c512e..50ce46bbf 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -318,12 +318,12 @@ struct BtorWorker btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero); nid = next_nid++; - btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str()); + btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell)); } else { nid = next_nid++; - btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); + btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -364,7 +364,7 @@ struct BtorWorker int sid = get_bv_sid(width); int nid = next_nid++; - btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); + btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell)); SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -390,12 +390,12 @@ struct BtorWorker if (cell->type == ID($_ANDNOT_)) { btorf("%d not %d %d\n", nid1, sid, nid_b); - btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); + btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell)); } if (cell->type == ID($_ORNOT_)) { btorf("%d not %d %d\n", nid1, sid, nid_b); - btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); + btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -417,13 +417,13 @@ struct BtorWorker if (cell->type == ID($_OAI3_)) { btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c); - btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str()); + btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell)); } if (cell->type == ID($_AOI3_)) { btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c); - btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str()); + btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -448,14 +448,14 @@ struct BtorWorker btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2); - btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str()); + btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell)); } if (cell->type == ID($_AOI4_)) { btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2); - btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str()); + btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -487,9 +487,9 @@ struct BtorWorker int nid = next_nid++; if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) { - btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); + btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell)); } else { - btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); + btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -524,7 +524,7 @@ struct BtorWorker log_assert(!btor_op.empty()); int sid = get_bv_sid(width); nid = next_nid++; - btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); + btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); } if (GetSize(sig) < width) { @@ -564,9 +564,9 @@ struct BtorWorker int nid = next_nid++; if (btor_op != "not") - btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); + btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell)); else - btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); + btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -597,11 +597,11 @@ struct BtorWorker if (cell->type == ID($reduce_xnor)) { int nid2 = next_nid++; - btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); + btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); btorf("%d not %d %d\n", nid2, sid, nid); nid = nid2; } else { - btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); + btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell)); } SigSpec sig = sigmap(cell->getPort(ID::Y)); @@ -636,9 +636,9 @@ struct BtorWorker int tmp = nid; nid = next_nid++; btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a); - btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str()); + btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell)); } else { - btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str()); + btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell)); } add_nid_sig(nid, sig_y); @@ -661,7 +661,7 @@ struct BtorWorker int nid_s = get_sig_nid(sig_s.extract(i)); int nid2 = next_nid++; if (i == GetSize(sig_s)-1) - btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str()); + btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell)); else btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid); nid = nid2; @@ -749,7 +749,7 @@ struct BtorWorker int sid = get_bv_sid(GetSize(sig_y)); int nid = next_nid++; - btorf("%d state %d%s\n", nid, sid, getinfo(cell).c_str()); + btorf("%d state %d%s\n", nid, sid, getinfo(cell)); ywmap_state(sig_y); @@ -772,7 +772,7 @@ struct BtorWorker int one_nid = get_sig_nid(State::S1); int zero_nid = get_sig_nid(State::S0); initstate_nid = next_nid++; - btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell).c_str()); + btorf("%d state %d%s\n", initstate_nid, sid, getinfo(cell)); btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid); btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid); @@ -1047,7 +1047,7 @@ struct BtorWorker if (consts.count(c) == 0) { int sid = get_bv_sid(GetSize(c)); int nid = next_nid++; - btorf("%d const %d %s\n", nid, sid, c.as_string().c_str()); + btorf("%d const %d %s\n", nid, sid, c.as_string()); consts[c] = nid; nid_width[nid] = GetSize(c); } @@ -1211,7 +1211,7 @@ struct BtorWorker int sid = get_bv_sid(GetSize(sig)); int nid = next_nid++; - btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str()); + btorf("%d input %d%s\n", nid, sid, getinfo(wire)); ywmap_input(wire); add_nid_sig(nid, sig); @@ -1256,7 +1256,7 @@ struct BtorWorker btorf_push(stringf("output %s", log_id(wire))); int nid = get_sig_nid(wire); - btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str()); + btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire)); btorf_pop(stringf("output %s", log_id(wire))); } @@ -1298,10 +1298,10 @@ struct BtorWorker bad_properties.push_back(nid_en_and_not_a); } else { if (cover_mode) { - infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str()); + infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true)); } else { int nid = next_nid++; - btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str()); + btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true)); } } @@ -1323,7 +1323,7 @@ struct BtorWorker bad_properties.push_back(nid_en_and_a); } else { int nid = next_nid++; - btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str()); + btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true)); } btorf_pop(log_id(cell)); @@ -1344,7 +1344,7 @@ struct BtorWorker continue; int this_nid = next_nid++; - btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str()); + btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire)); if (info_clocks.count(nid)) info_clocks[this_nid] |= info_clocks[nid]; @@ -1367,7 +1367,7 @@ struct BtorWorker SigSpec sig = sigmap(cell->getPort(ID::D)); int nid_q = get_sig_nid(sig); int sid = get_bv_sid(GetSize(sig)); - btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str()); + btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell)); btorf_pop(stringf("next %s", log_id(cell))); } @@ -1426,7 +1426,7 @@ struct BtorWorker } int nid2 = next_nid++; - btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem)).c_str()); + btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem))); btorf_pop(stringf("next %s", log_id(mem->memid))); } From ad4ef8b775f67c2394779c08bb519cf0db51c0da Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 06:01:32 +0000 Subject: [PATCH 059/188] Make AstNode::input_error use C++ stringf machinery --- frontends/ast/ast.cc | 6 ++---- frontends/ast/ast.h | 7 ++++++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 313161fc3..9af355109 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1922,11 +1922,9 @@ void AstModule::loadconfig() const flag_autowire = autowire; } -void AstNode::input_error(const char *format, ...) const +void AstNode::formatted_input_error(std::string str) const { - va_list ap; - va_start(ap, format); - logv_file_error(*location.begin.filename, location.begin.line, format, ap); + log_formatted_file_error(*location.begin.filename, location.begin.line, std::move(str)); } YOSYS_NAMESPACE_END diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index fdf4d1ec9..fd8ecddd7 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -378,7 +378,12 @@ namespace AST AstNode *get_struct_member() const; // helper to print errors from simplify/genrtlil code - [[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3)); + [[noreturn]] void formatted_input_error(std::string str) const; + template + [[noreturn]] void input_error(FmtString...> fmt, const Args &... args) const + { + formatted_input_error(fmt.format(args...)); + } }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code From 733b6f01242ad212cc482b7e936fc527b10c028e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 06:03:05 +0000 Subject: [PATCH 060/188] Remove unnecessary usage of .c_str() in parameters to input_error() --- frontends/ast/ast.cc | 6 +-- frontends/ast/genrtlil.cc | 68 +++++++++++++++---------------- frontends/ast/simplify.cc | 84 +++++++++++++++++++-------------------- 3 files changed, 79 insertions(+), 79 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 9af355109..0d90498f6 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -193,7 +193,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) auto& attr = attributes.at(id); if (attr->type != AST_CONSTANT) - attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str()); + attr->input_error("Attribute `%s' with non-constant value!\n", id); return attr->integer != 0; } @@ -1143,7 +1143,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d { for (auto& node : ast->children) if (node->type == AST_PARAMETER && param_has_no_default(node.get())) - node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str()); + node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str); bool blackbox_module = flag_lib; @@ -1256,7 +1256,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d for (auto &attr : ast->attributes) { log_assert((bool)attr.second.get()); if (attr.second->type != AST_CONSTANT) - ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + ast->input_error("Attribute `%s' with non-constant value!\n", attr.first); module->attributes[attr.first] = attr.second->asAttrConst(); } for (size_t i = 0; i < ast->children.size(); i++) { diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 896ae9bdb..26819de18 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -56,7 +56,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -88,7 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s if (that != nullptr) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -114,7 +114,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -149,7 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -352,7 +352,7 @@ struct AST_INTERNAL::ProcessGenerator set_src_attr(proc, always.get()); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) - always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + always->input_error("Attribute `%s' with non-constant value!\n", attr.first); proc->attributes[attr.first] = attr.second->asAttrConst(); } current_case = &proc->root_case; @@ -630,7 +630,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + ast->input_error("Attribute `%s' with non-constant value!\n", attr.first); sw->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1007,7 +1007,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun } } if (!id_ast) - input_error("Failed to resolve identifier %s for width detection!\n", str.c_str()); + input_error("Failed to resolve identifier %s for width detection!\n", str); if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) { if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; @@ -1017,7 +1017,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); else - input_error("Failed to detect width for parameter %s!\n", str.c_str()); + input_error("Failed to detect width for parameter %s!\n", str); } if (children.size() != 0) range = children[0].get(); @@ -1030,7 +1030,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // log("---\n"); // id_ast->dumpAst(nullptr, "decl> "); // dumpAst(nullptr, "ref> "); - input_error("Failed to detect width of signal access `%s'!\n", str.c_str()); + input_error("Failed to detect width of signal access `%s'!\n", str); } } else { this_width = id_ast->range_left - id_ast->range_right + 1; @@ -1041,7 +1041,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = 32; } else if (id_ast->type == AST_MEMORY) { if (!id_ast->children[0]->range_valid) - input_error("Failed to detect width of memory access `%s'!\n", str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", str); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; if (children.size() > 1) range = children[1].get(); @@ -1049,7 +1049,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun auto tmp_range = make_index_range(id_ast); this_width = tmp_range->range_left - tmp_range->range_right + 1; } else - input_error("Failed to detect width for identifier %s!\n", str.c_str()); + input_error("Failed to detect width for identifier %s!\n", str); if (range) { if (range->children.size() == 1) this_width = 1; @@ -1059,7 +1059,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (left_at_zero_ast->simplify(true, 1, -1, false)) { } while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str); this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } else this_width = range->range_left - range->range_right + 1; @@ -1193,7 +1193,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id2ast->is_signed) sign_hint = false; if (!id2ast->children[0]->range_valid) - input_error("Failed to detect width of memory access `%s'!\n", str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", str); this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; width_hint = max(width_hint, this_width); break; @@ -1266,7 +1266,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // item expressions. const AstNode *func = current_scope.at(str); if (func->type != AST_FUNCTION) - input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str()); + input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str)); const AstNode *wire = nullptr; for (const auto& child : func->children) if (child->str == func->str) { @@ -1302,7 +1302,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod; for (auto f : log_files) current_scope_ast->dumpAst(f, "verilog-ast> "); - input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); + input_error("Don't know how to detect sign and width for %s node!\n", type2str(type)); } @@ -1406,7 +1406,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (flag_pwires) { if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT) - input_error("Parameter `%s' with non-constant value!\n", str.c_str()); + input_error("Parameter `%s' with non-constant value!\n", str); RTLIL::Const val = children[0]->bitsAsConst(); RTLIL::IdString id = str; @@ -1420,7 +1420,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first); wire->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1429,10 +1429,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { if (!range_valid) - input_error("Signal `%s' with non-constant width!\n", str.c_str()); + input_error("Signal `%s' with non-constant width!\n", str); if (!(range_left + 1 >= range_right)) - input_error("Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); + input_error("Signal `%s' with invalid width range %d!\n", str, range_left - range_right + 1); RTLIL::IdString id = str; check_unique_id(current_module, id, this, "signal"); @@ -1448,7 +1448,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first); wire->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1464,7 +1464,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_assert(children[1]->type == AST_RANGE); if (!children[0]->range_valid || !children[1]->range_valid) - input_error("Memory `%s' with non-constant width or size!\n", str.c_str()); + input_error("Memory `%s' with non-constant width or size!\n", str); RTLIL::Memory *memory = new RTLIL::Memory; set_src_attr(memory, this); @@ -1482,7 +1482,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first); memory->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1539,11 +1539,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (flag_autowire) log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str()); else - input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str); } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) { if (id2ast->children[0]->type != AST_CONSTANT) - input_error("Parameter %s does not evaluate to constant value!\n", str.c_str()); + input_error("Parameter %s does not evaluate to constant value!\n", str); chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } @@ -1558,11 +1558,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) is_interface = true; } else { - input_error("Identifier `%s' doesn't map to any signal!\n", str.c_str()); + input_error("Identifier `%s' doesn't map to any signal!\n", str); } if (id2ast->type == AST_MEMORY) - input_error("Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); + input_error("Identifier `%s' does map to an unexpanded memory!\n", str); // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface' // This makes it possible for the hierarchy pass to see what are interface connections and then replace them @@ -1610,7 +1610,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) while (left_at_zero_ast->simplify(true, 1, -1, false)) { } while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; auto fake_ast = std::make_unique(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); @@ -2032,7 +2032,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) set_src_attr(cell, this); for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } cell->setParam(ID(FLAVOR), flavor); @@ -2148,7 +2148,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value.\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } if (cell->type == ID($specify2)) { @@ -2203,7 +2203,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_warning(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$error") { if (sz > 0) - input_error("%s.\n", children[0]->str.c_str()); + input_error("%s.\n", children[0]->str); else input_error("\n"); } else if (str == "$fatal") { @@ -2212,11 +2212,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // dollar_finish(sz ? children[0] : 1); // perhaps create & use log_file_fatal() if (sz > 0) - input_error("FATAL: %s.\n", children[0]->str.c_str()); + input_error("FATAL: %s.\n", children[0]->str); else input_error("FATAL.\n"); } else { - input_error("Unknown elaboration system task '%s'.\n", str.c_str()); + input_error("Unknown elaboration system task '%s'.\n", str); } } break; @@ -2245,7 +2245,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (width <= 0) - input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); + input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str)); Cell *cell = current_module->addCell(myid, str.substr(1)); set_src_attr(cell, this); @@ -2272,7 +2272,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) default: for (auto f : log_files) current_ast_mod->dumpAst(f, "verilog-ast> "); - input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str()); + input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type)); } return RTLIL::SigSpec(); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bf72a770f..e208a1063 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -250,7 +250,7 @@ static int range_width(AstNode *node, AstNode *rnode) { log_assert(rnode->type==AST_RANGE); if (!rnode->range_valid) { - node->input_error("Non-constant range in declaration of %s\n", node->str.c_str()); + node->input_error("Non-constant range in declaration of %s\n", node->str); } // note: range swapping has already been checked for return rnode->range_left - rnode->range_right + 1; @@ -265,7 +265,7 @@ static int add_dimension(AstNode *node, AstNode *rnode) [[noreturn]] static void struct_array_packing_error(AstNode *node) { - node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str()); + node->input_error("Unpacked array in packed struct/union member %s\n", node->str); } static int size_packed_struct(AstNode *snode, int base_offset) @@ -358,7 +358,7 @@ static int size_packed_struct(AstNode *snode, int base_offset) } else { if (packed_width != width) - node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width); + node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str, width, packed_width); } } else { @@ -481,7 +481,7 @@ std::unique_ptr AstNode::make_index_range(AstNode *decl_node, bool unpa dim--; // Step back to the final index / slice } else { - input_error("Unsupported range operation for %s\n", str.c_str()); + input_error("Unsupported range operation for %s\n", str); } std::unique_ptr index_range = std::make_unique(rnode->location, AST_RANGE); @@ -1135,7 +1135,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode.get(); else - input_error("enum item %s already exists in current scope\n", enode->str.c_str()); + input_error("enum item %s already exists in current scope\n", enode->str); } } } @@ -1209,7 +1209,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin continue; wires_are_incompatible: if (stage > 1) - input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str()); + input_error("Incompatible re-declaration of wire %s.\n", node->str); continue; } this_wire_scope[node->str] = node; @@ -1228,7 +1228,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode.get(); else - input_error("enum item %s already exists\n", enode->str.c_str()); + input_error("enum item %s already exists\n", enode->str); } } } @@ -1268,7 +1268,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode.get(); else - input_error("enum item %s already exists in package\n", enode->str.c_str()); + input_error("enum item %s already exists in package\n", enode->str); } } } @@ -1561,10 +1561,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin const std::string &type_name = child->children[0]->str; if (!current_scope.count(type_name)) - input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); + input_error("Unknown identifier `%s' used as type name\n", type_name); AstNode *resolved_type_node = current_scope.at(type_name); if (resolved_type_node->type != AST_TYPEDEF) - input_error("`%s' does not name a type\n", type_name.c_str()); + input_error("`%s' does not name a type\n", type_name); log_assert(resolved_type_node->children.size() == 1); auto* template_node = resolved_type_node->children[0].get(); @@ -1909,7 +1909,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } if (pos == std::string::npos) - input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); + input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname)); paramname = "\\" + paramname.substr(pos+1); @@ -1943,11 +1943,11 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin log_assert(children[0]->type == AST_WIRETYPE); auto type_name = children[0]->str; if (!current_scope.count(type_name)) { - input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); + input_error("Unknown identifier `%s' used as type name\n", type_name); } AstNode *resolved_type_node = current_scope.at(type_name); if (resolved_type_node->type != AST_TYPEDEF) - input_error("`%s' does not name a type\n", type_name.c_str()); + input_error("`%s' does not name a type\n", type_name); log_assert(resolved_type_node->children.size() == 1); auto& template_node = resolved_type_node->children[0]; @@ -1985,7 +1985,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin // Cannot add packed dimensions if unpacked dimensions are already specified. if (add_packed_dimensions && newNode->type == AST_MEMORY) - input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name.c_str()); + input_error("Cannot extend unpacked type `%s' with packed dimensions\n", type_name); // Add packed dimensions. if (add_packed_dimensions) { @@ -2030,7 +2030,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin children.insert(children.begin(), std::move(expr)); if (children[1]->type == AST_MEMORY) - input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); + input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str); fixup_hierarchy_flags(); did_something = true; } @@ -2331,7 +2331,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } if (current_scope.count(str) == 0) { if (current_ast_mod == nullptr) { - input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared outside of a module.\n", str); } else if (flag_autowire || str == "\\$global_clock") { auto auto_wire = std::make_unique(location, AST_AUTOWIRE); auto_wire->str = str; @@ -2339,7 +2339,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin current_ast_mod->children.push_back(std::move(auto_wire)); did_something = true; } else { - input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str); } } if (id2ast != current_scope[str]) { @@ -2562,7 +2562,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } if (buf->type != AST_CONSTANT) - input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str()); + input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type)); varbuf->children[0] = std::move(buf); } @@ -2778,7 +2778,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (type == AST_PRIMITIVE) { if (children.size() < 2) - input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str()); + input_error("Insufficient number of arguments for primitive `%s'!\n", str); std::vector> children_list; for (auto& child : children) { @@ -2792,7 +2792,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) - input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str()); + input_error("Invalid number of arguments for primitive `%s'!\n", str); std::vector z_const(1, RTLIL::State::Sz); @@ -2894,7 +2894,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin auto& range = children[0]->children[0]; if (!try_determine_range_width(range.get(), result_width)) - input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str); if (range->children.size() >= 2) shift_expr = range->children[1]->clone(); @@ -3285,7 +3285,7 @@ skip_dynamic_range_lvalue_expansion:; int width; if (!try_determine_range_width(the_range.get(), width)) - input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str); if (the_range->children.size() >= 2) offset_ast = the_range->children[1]->clone(); @@ -3405,7 +3405,7 @@ skip_dynamic_range_lvalue_expansion:; auto buf = children[1]->clone(); while (buf->simplify(true, stage, -1, false)) { } if (buf->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant value.\n", str); num_steps = buf->asInt(true); } @@ -3516,7 +3516,7 @@ skip_dynamic_range_lvalue_expansion:; auto buf = children[0]->clone(); while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant value.\n", str); RTLIL::Const arg_value = buf->bitsAsConst(); if (arg_value.as_bool()) @@ -3563,7 +3563,7 @@ skip_dynamic_range_lvalue_expansion:; if (id_ast == nullptr && current_scope.count(buf->str)) id_ast = current_scope.at(buf->str); if (!id_ast) - input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); + input_error("Failed to resolve identifier %s for width detection!\n", buf->str); if (id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) { // Check for item in packed struct / union @@ -3578,7 +3578,7 @@ skip_dynamic_range_lvalue_expansion:; // TODO: IEEE Std 1800-2017 20.7: "If the first argument to an array query function would cause $dimensions to return 0 // or if the second argument is out of range, then 'x shall be returned." if (dim < 1 || dim > dims) - input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str.c_str(), dims); + input_error("Dimension %d out of range in `%s', as it only has %d dimensions!\n", dim, id_ast->str, dims); expr_dimensions = dims - dim + 1; expr_unpacked_dimensions = std::max(id_ast->unpacked_dimensions - dim + 1, 0); @@ -3712,9 +3712,9 @@ skip_dynamic_range_lvalue_expansion:; auto& node = children[i]; while (node->simplify(true, stage, -1, false)) { } if (node->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str); if (node->bits.size() != 1) - input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str); control_bits.push_back(node->bits[0]); } @@ -3817,7 +3817,7 @@ skip_dynamic_range_lvalue_expansion:; if (current_scope.count(str) == 0) str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) - input_error("Can't resolve function name `%s'.\n", str.c_str()); + input_error("Can't resolve function name `%s'.\n", str); } if (type == AST_TCALL) @@ -3825,9 +3825,9 @@ skip_dynamic_range_lvalue_expansion:; if (str == "$finish" || str == "$stop") { if (!current_always || current_always->type != AST_INITIAL) - input_error("System task `%s' outside initial block is unsupported.\n", str.c_str()); + input_error("System task `%s' outside initial block is unsupported.\n", str); - input_error("System task `%s' executed.\n", str.c_str()); + input_error("System task `%s' executed.\n", str); } if (str == "\\$readmemh" || str == "\\$readmemb") @@ -3839,12 +3839,12 @@ skip_dynamic_range_lvalue_expansion:; auto node_filename = children[0]->clone(); while (node_filename->simplify(true, stage, width_hint, sign_hint)) { } if (node_filename->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str); auto node_memory = children[1]->clone(); while (node_memory->simplify(true, stage, width_hint, sign_hint)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) - input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str); int start_addr = -1, finish_addr = -1; @@ -3852,7 +3852,7 @@ skip_dynamic_range_lvalue_expansion:; auto node_addr = children[2]->clone(); while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str); start_addr = int(node_addr->asInt(false)); } @@ -3860,7 +3860,7 @@ skip_dynamic_range_lvalue_expansion:; auto node_addr = children[3]->clone(); while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str); finish_addr = int(node_addr->asInt(false)); } @@ -3888,7 +3888,7 @@ skip_dynamic_range_lvalue_expansion:; if (current_scope.count(str) == 0) str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) - input_error("Can't resolve task name `%s'.\n", str.c_str()); + input_error("Can't resolve task name `%s'.\n", str); } @@ -3928,7 +3928,7 @@ skip_dynamic_range_lvalue_expansion:; if (in_param) input_error("Non-constant function call in constant expression.\n"); if (require_const_eval) - input_error("Function %s can only be called with constant arguments.\n", str.c_str()); + input_error("Function %s can only be called with constant arguments.\n", str); } size_t arg_count = 0; @@ -4050,7 +4050,7 @@ skip_dynamic_range_lvalue_expansion:; goto tcall_incompatible_wires; } else { tcall_incompatible_wires: - input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str()); + input_error("Incompatible re-declaration of wire %s.\n", child->str); } } } @@ -4476,7 +4476,7 @@ std::unique_ptr AstNode::readmem(bool is_readmemh, std::string mem_file yosys_input_files.insert(mem_filename); } if (f.fail() || GetSize(mem_filename) == 0) - input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); + input_error("Can not open file `%s` for %s.\n", mem_filename, str); log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; @@ -4522,7 +4522,7 @@ std::unique_ptr AstNode::readmem(bool is_readmemh, std::string mem_file char *endptr; cursor = strtol(nptr, &endptr, 16); if (!*nptr || *endptr) - input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str()); + input_error("Can not parse address `%s` for %s.\n", nptr, str); continue; } @@ -5421,7 +5421,7 @@ std::unique_ptr AstNode::eval_const_function(AstNode *fcall, bool must_ // if this variable has already been declared as an input, check the // sizes match if it already had an explicit size if (variable.arg && variable.explicitly_sized && variable.val.size() != width) { - input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str()); + input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str); } variable.val = RTLIL::Const(RTLIL::State::Sx, width); variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right; @@ -5503,7 +5503,7 @@ std::unique_ptr AstNode::eval_const_function(AstNode *fcall, bool must_ if (!range->range_valid) { if (!must_succeed) goto finished; - range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str()); + range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string()); } int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; From 8cd3c069d662d12e727f75bb40bbfdc5d05e0308 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 06:13:13 +0000 Subject: [PATCH 061/188] Use C++ stringf machinery in verilog_error --- frontends/verilog/verilog_error.cc | 35 +++++------------------------- frontends/verilog/verilog_error.h | 16 ++++++++++++-- 2 files changed, 20 insertions(+), 31 deletions(-) diff --git a/frontends/verilog/verilog_error.cc b/frontends/verilog/verilog_error.cc index 491b8c7f5..b968b3e21 100644 --- a/frontends/verilog/verilog_error.cc +++ b/frontends/verilog/verilog_error.cc @@ -32,37 +32,14 @@ USING_YOSYS_NAMESPACE */ [[noreturn]] -static void verr_at(std::string filename, int begin_line, char const *fmt, va_list ap) +void VERILOG_FRONTEND::formatted_err_at_loc(Location loc, std::string str) { - char buffer[1024]; - char *p = buffer; - p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); - p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); - YOSYS_NAMESPACE_PREFIX log_file_error(filename, begin_line, "%s", buffer); - exit(1); + YOSYS_NAMESPACE_PREFIX log_file_error(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, + "%s\n", std::move(str)); } -static void vwarn_at(std::string filename, int begin_line, char const *fmt, va_list ap) +void VERILOG_FRONTEND::formatted_warn_at_loc(Location loc, std::string str) { - char buffer[1024]; - char *p = buffer; - p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); - p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); - YOSYS_NAMESPACE_PREFIX log_file_warning(filename, begin_line, "%s", buffer); + YOSYS_NAMESPACE_PREFIX log_file_warning(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, + "%s\n", std::move(str)); } - -[[noreturn]] -void VERILOG_FRONTEND::err_at_loc(Location loc, char const *fmt, ...) -{ - va_list args; - va_start(args, fmt); - verr_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args); -} -void VERILOG_FRONTEND::warn_at_loc(Location loc, char const *fmt, ...) -{ - va_list args; - va_start(args, fmt); - vwarn_at(loc.begin.filename ? *(loc.begin.filename) : "UNKNOWN", loc.begin.line, fmt, args); - va_end(args); -} - diff --git a/frontends/verilog/verilog_error.h b/frontends/verilog/verilog_error.h index b36de19b8..ede489b26 100644 --- a/frontends/verilog/verilog_error.h +++ b/frontends/verilog/verilog_error.h @@ -10,8 +10,20 @@ YOSYS_NAMESPACE_BEGIN namespace VERILOG_FRONTEND { [[noreturn]] - void err_at_loc(Location loc, char const *fmt, ...); - void warn_at_loc(Location loc, char const *fmt, ...); + void formatted_err_at_loc(Location loc, std::string str); + template + [[noreturn]] + void err_at_loc(Location loc, FmtString...> fmt, const Args &... args) + { + formatted_err_at_loc(std::move(loc), fmt.format(args...)); + } + + void formatted_warn_at_loc(Location loc, std::string str); + template + void warn_at_loc(Location loc, FmtString...> fmt, const Args &... args) + { + formatted_warn_at_loc(std::move(loc), fmt.format(args...)); + } }; YOSYS_NAMESPACE_END From f4699e2b10b959cd3700b3509df93b5b147fe7c5 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 12 Sep 2025 06:18:03 +0000 Subject: [PATCH 062/188] Remove unnecessary c_str() calls from err_at_loc/warn_at_loc --- frontends/verilog/verilog_frontend.cc | 2 +- frontends/verilog/verilog_parser.y | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 4b4f7ad8d..69313ed3b 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -51,7 +51,7 @@ static std::list> verilog_defaults_stack; static void error_on_dpi_function(AST::AstNode *node) { if (node->type == AST::AST_DPI_FUNCTION) - err_at_loc(node->location, "Found DPI function %s.\n", node->str.c_str()); + err_at_loc(node->location, "Found DPI function %s.\n", node->str); for (auto& child : node->children) error_on_dpi_function(child.get()); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 3db92be01..9168b195a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -420,7 +420,7 @@ void frontend_verilog_yy::parser::error(const frontend_verilog_yy::parser::location_type& loc, const std::string& msg) { - err_at_loc(loc, "%s", msg.c_str()); + err_at_loc(loc, "%s", msg); } } @@ -772,7 +772,7 @@ module_arg: extra->ast_stack.back()->children.push_back(std::move(node)); } else { if (extra->port_stubs.count(*$1) != 0) - err_at_loc(@1, "Duplicate module port `%s'.", $1->c_str()); + err_at_loc(@1, "Duplicate module port `%s'.", *$1); extra->port_stubs[*$1] = ++extra->port_counter; } } module_arg_opt_assignment | @@ -782,7 +782,7 @@ module_arg: extra->astbuf1->children[0]->str = *$1; } TOK_ID { /* SV interfaces */ if (!mode->sv) - err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str()); + err_at_loc(@3, "Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", *$3); extra->astbuf2 = extra->astbuf1->clone(); // really only needed if multiple instances of same type. extra->astbuf2->str = *$3; extra->astbuf2->port_id = ++extra->port_counter; @@ -797,9 +797,9 @@ module_arg: if (range != nullptr) node->children.push_back(std::move(range)); if (!node->is_input && !node->is_output) - err_at_loc(@4, "Module port `%s' is neither input nor output.", $4->c_str()); + err_at_loc(@4, "Module port `%s' is neither input nor output.", *$4); if (node->is_reg && node->is_input && !node->is_output && !mode->sv) - err_at_loc(@4, "Input port `%s' is declared as register.", $4->c_str()); + err_at_loc(@4, "Input port `%s' is declared as register.", *$4); append_attr(node.get(), std::move($1)); extra->ast_stack.back()->children.push_back(std::move(node)); } module_arg_opt_assignment | @@ -1381,7 +1381,7 @@ specify_item: TOK_ID TOK_LPAREN specify_edge expr specify_condition TOK_COMMA specify_edge expr specify_condition TOK_COMMA specify_triple specify_opt_triple TOK_RPAREN TOK_SEMICOL { if (*$1 != "$setup" && *$1 != "$hold" && *$1 != "$setuphold" && *$1 != "$removal" && *$1 != "$recovery" && *$1 != "$recrem" && *$1 != "$skew" && *$1 != "$timeskew" && *$1 != "$fullskew" && *$1 != "$nochange") - err_at_loc(@1, "Unsupported specify rule type: %s", $1->c_str()); + err_at_loc(@1, "Unsupported specify rule type: %s", *$1); auto src_pen = AstNode::mkconst_int(@3, $3 != 0, false, 1); auto src_pol = AstNode::mkconst_int(@3, $3 == 'p', false, 1); @@ -2156,21 +2156,21 @@ wire_name: node->port_id = extra->current_function_or_task_port_id++; } else if (extra->ast_stack.back()->type == AST_GENBLOCK) { if (node->is_input || node->is_output) - err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", $1->c_str()); + err_at_loc(@1, "Cannot declare module port `%s' within a generate block.", *$1); } else { if (extra->do_not_require_port_stubs && (node->is_input || node->is_output) && extra->port_stubs.count(*$1) == 0) { extra->port_stubs[*$1] = ++extra->port_counter; } if (extra->port_stubs.count(*$1) != 0) { if (!node->is_input && !node->is_output) - err_at_loc(@1, "Module port `%s' is neither input nor output.", $1->c_str()); + err_at_loc(@1, "Module port `%s' is neither input nor output.", *$1); if (node->is_reg && node->is_input && !node->is_output && !mode->sv) - err_at_loc(@1, "Input port `%s' is declared as register.", $1->c_str()); + err_at_loc(@1, "Input port `%s' is declared as register.", *$1); node->port_id = extra->port_stubs[*$1]; extra->port_stubs.erase(*$1); } else { if (node->is_input || node->is_output) - err_at_loc(@1, "Module port `%s' is not declared in module header.", $1->c_str()); + err_at_loc(@1, "Module port `%s' is not declared in module header.", *$1); } } //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column... @@ -3247,7 +3247,7 @@ basic_expr: } | TOK_LPAREN expr TOK_RPAREN integral_number { if ($4->compare(0, 1, "'") != 0) - err_at_loc(@4, "Cast operation must be applied on sized constants e.g. () , while %s is not a sized constant.", $4->c_str()); + err_at_loc(@4, "Cast operation must be applied on sized constants e.g. () , while %s is not a sized constant.", *$4); ConstParser p{@4}; auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); if (val == nullptr) @@ -3256,7 +3256,7 @@ basic_expr: } | hierarchical_id integral_number { if ($2->compare(0, 1, "'") != 0) - err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. \'d0, while %s is not a sized constant.", $2->c_str()); + err_at_loc(@2, "Cast operation must be applied on sized constants, e.g. \'d0, while %s is not a sized constant.", *$2); auto bits = std::make_unique(@$, AST_IDENTIFIER); bits->str = *$1; SET_AST_NODE_LOC(bits.get(), @1, @1); From f102b259141d78b6b05bf16bb4d28b975d05168f Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 12 Sep 2025 09:27:29 +1200 Subject: [PATCH 063/188] Reapply "Merge pull request #5301 from KrystalDelusion/krys/re_5280" This reverts commit 88eb83a0c3e19c1c1cca42658aeb762abe2ed913. --- .github/workflows/extra-builds.yml | 16 +++- .github/workflows/test-build.yml | 44 ++++++----- .github/workflows/test-compile.yml | 16 +++- .github/workflows/test-sanitizers.yml | 109 ++++++++++++++++++++++++++ .github/workflows/test-verific.yml | 16 +++- passes/memory/memlib.cc | 2 +- passes/memory/memlib.h | 2 +- 7 files changed, 171 insertions(+), 34 deletions(-) create mode 100644 .github/workflows/test-sanitizers.yml diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 9c15c3383..503145e97 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -1,6 +1,14 @@ name: Test extra build flows -on: [push, pull_request] +on: + # always test main + push: + branches: + - main + # test PRs + pull_request: + # allow triggering tests, ignores skip check + workflow_dispatch: jobs: pre_job: @@ -11,11 +19,11 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: + # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' # cancel previous builds if a new commit is pushed - cancel_others: 'true' - # only run on push *or* pull_request, not both - concurrent_skipping: 'same_content_newer' + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} vs-prep: name: Prepare Visual Studio build diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index f9574594a..16ad98bec 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -1,6 +1,14 @@ name: Build and run tests -on: [push, pull_request] +on: + # always test main + push: + branches: + - main + # test PRs + pull_request: + # allow triggering tests, ignores skip check + workflow_dispatch: jobs: pre_job: @@ -11,11 +19,12 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: + # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' # cancel previous builds if a new commit is pushed - cancel_others: 'true' - # only run on push *or* pull_request, not both - concurrent_skipping: 'same_content_newer' + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} + pre_docs_job: runs-on: ubuntu-latest outputs: @@ -24,15 +33,16 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: + # don't run on readme changes paths_ignore: '["**/README.md"]' # cancel previous builds if a new commit is pushed - cancel_others: 'true' - # only run on push *or* pull_request, not both - concurrent_skipping: 'same_content_newer' + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} build-yosys: name: Reusable build runs-on: ${{ matrix.os }} + # pre_job is a subset of pre_docs_job, so we can always build for pre_docs_job needs: pre_docs_job if: needs.pre_docs_job.outputs.should_skip != 'true' env: @@ -40,7 +50,6 @@ jobs: strategy: matrix: os: [ubuntu-latest, macos-latest] - sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -58,7 +67,6 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf make -f ../Makefile -j$procs ENABLE_LTO=1 - name: Log yosys-config output @@ -74,7 +82,7 @@ jobs: - name: Store build artifact uses: actions/upload-artifact@v4 with: - name: build-${{ matrix.os }}-${{ matrix.sanitizer }} + name: build-${{ matrix.os }} path: build.tar retention-days: 1 @@ -85,12 +93,9 @@ jobs: if: needs.pre_job.outputs.should_skip != 'true' env: CC: clang - ASAN_OPTIONS: halt_on_error=1 - UBSAN_OPTIONS: halt_on_error=1 strategy: matrix: os: [ubuntu-latest, macos-latest] - sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -102,11 +107,12 @@ jobs: uses: ./.github/actions/setup-build-env - name: Get iverilog + id: get-iverilog shell: bash run: | git clone https://github.com/steveicarus/iverilog.git cd iverilog - echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT - name: Get vcd2fst shell: bash @@ -123,7 +129,7 @@ jobs: uses: actions/cache@v4 with: path: .local/ - key: ${{ matrix.os }}-${IVERILOG_GIT} + key: ${{ matrix.os }}-${{ steps.get-iverilog.outputs.IVERILOG_GIT }} - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' @@ -139,7 +145,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }}-${{ matrix.sanitizer }} + name: build-${{ matrix.os }} - name: Uncompress build shell: bash @@ -171,7 +177,6 @@ jobs: strategy: matrix: os: [ubuntu-latest] - sanitizer: [undefined] steps: - name: Checkout Yosys uses: actions/checkout@v4 @@ -184,7 +189,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }}-${{ matrix.sanitizer }} + name: build-${{ matrix.os }} - name: Uncompress build shell: bash @@ -209,7 +214,6 @@ jobs: strategy: matrix: os: [ubuntu-latest] - sanitizer: [undefined, address] fail-fast: false steps: - name: Checkout Yosys @@ -223,7 +227,7 @@ jobs: - name: Download build artifact uses: actions/download-artifact@v4 with: - name: build-${{ matrix.os }}-${{ matrix.sanitizer }} + name: build-${{ matrix.os }} - name: Uncompress build shell: bash diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 95c6ea4c1..45d3d7b90 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -1,6 +1,14 @@ name: Compiler testing -on: [push, pull_request] +on: + # always test main + push: + branches: + - main + # test PRs + pull_request: + # allow triggering tests, ignores skip check + workflow_dispatch: jobs: pre_job: @@ -11,11 +19,11 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: + # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' # cancel previous builds if a new commit is pushed - cancel_others: 'true' - # only run on push *or* pull_request, not both - concurrent_skipping: 'same_content_newer' + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} test-compile: runs-on: ${{ matrix.os }} diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml new file mode 100644 index 000000000..255b9daa5 --- /dev/null +++ b/.github/workflows/test-sanitizers.yml @@ -0,0 +1,109 @@ +name: Check clang sanitizers + +on: + # always test main + push: + branches: + - main + # ignore PRs due to time needed + # allow triggering tests, ignores skip check + workflow_dispatch: + +jobs: + pre_job: + runs-on: ubuntu-latest + outputs: + should_skip: ${{ steps.skip_check.outputs.should_skip }} + steps: + - id: skip_check + uses: fkirc/skip-duplicate-actions@v5 + with: + # don't run on documentation changes + paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' + + run_san: + name: Build and run tests + runs-on: ${{ matrix.os }} + needs: pre_job + if: needs.pre_job.outputs.should_skip != 'true' + env: + CC: clang + ASAN_OPTIONS: halt_on_error=1 + UBSAN_OPTIONS: halt_on_error=1 + strategy: + matrix: + os: [ubuntu-latest, macos-latest] + sanitizer: ['undefined,address'] + fail-fast: false + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + submodules: true + persist-credentials: false + + - name: Setup environment + uses: ./.github/actions/setup-build-env + + - name: Get iverilog + id: get-iverilog + shell: bash + run: | + git clone https://github.com/steveicarus/iverilog.git + cd iverilog + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT + + - name: Get vcd2fst + shell: bash + run: | + git clone https://github.com/mmicko/libwave.git + mkdir -p ${{ github.workspace }}/.local/ + cd libwave + cmake . -DCMAKE_INSTALL_PREFIX=${{ github.workspace }}/.local + make -j$procs + make install + + - name: Cache iverilog + id: cache-iverilog + uses: actions/cache@v4 + with: + path: .local/ + key: ${{ matrix.os }}-${{ steps.get-iverilog.outputs.IVERILOG_GIT }} + + - name: Build iverilog + if: steps.cache-iverilog.outputs.cache-hit != 'true' + shell: bash + run: | + mkdir -p ${{ github.workspace }}/.local/ + cd iverilog + autoconf + CC=gcc CXX=g++ ./configure --prefix=${{ github.workspace }}/.local + make -j$procs + make install + + - name: Check iverilog + shell: bash + run: | + iverilog -V + + - name: Build + shell: bash + run: | + make config-$CC + echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf + make -j$procs ENABLE_LTO=1 + + - name: Log yosys-config output + run: | + ./yosys-config || true + + - name: Run tests + shell: bash + run: | + make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC + + - name: Report errors + if: ${{ failure() }} + shell: bash + run: | + find tests/**/*.err -print -exec cat {} \; diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 013c9f8ca..9af07b920 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -1,6 +1,14 @@ name: Build and run tests with Verific (Linux) -on: [push, pull_request] +on: + # always test main + push: + branches: + - main + # test PRs + pull_request: + # allow triggering tests, ignores skip check + workflow_dispatch: jobs: pre-job: @@ -11,11 +19,11 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: + # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' # cancel previous builds if a new commit is pushed - cancel_others: 'true' - # only run on push *or* pull_request, not both - concurrent_skipping: 'same_content_newer' + # but never cancel main + cancel_others: ${{ github.ref != 'refs/heads/main' }} test-verific: needs: pre-job diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index fb256e41c..4bb2350d2 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -880,7 +880,7 @@ struct Parser { } } } - var.clk_en = find_single_cap(pdef.clken, cram.options, portopts, "clken"); + var.clk_en = find_single_cap(pdef.clken, cram.options, portopts, "clken") != nullptr; } const PortWidthDef *wdef = find_single_cap(pdef.width, cram.options, portopts, "width"); if (wdef) { diff --git a/passes/memory/memlib.h b/passes/memory/memlib.h index 43dec7386..7394baf4e 100644 --- a/passes/memory/memlib.h +++ b/passes/memory/memlib.h @@ -109,7 +109,7 @@ struct PortVariant { PortKind kind; int clk_shared; ClkPolKind clk_pol; - bool clk_en; + bool clk_en = false; bool width_tied; int min_wr_wide_log2; int max_wr_wide_log2; From 7e1292dd2da13851d2b6df4f24c12d0c48f9b021 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 12 Sep 2025 11:09:26 +1200 Subject: [PATCH 064/188] CI: brew install autoconf for iverilog --- .github/workflows/test-build.yml | 6 ++++++ .github/workflows/test-sanitizers.yml | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 16ad98bec..65d931797 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -131,6 +131,12 @@ jobs: path: .local/ key: ${{ matrix.os }}-${{ steps.get-iverilog.outputs.IVERILOG_GIT }} + - name: iverilog macOS deps + if: steps.cache-iverilog.outputs.cache-hit != 'true' && runner.os == 'macOS' + shell: bash + run: | + brew install autoconf + - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' shell: bash diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 255b9daa5..2ffd2db15 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -70,6 +70,12 @@ jobs: path: .local/ key: ${{ matrix.os }}-${{ steps.get-iverilog.outputs.IVERILOG_GIT }} + - name: iverilog macOS deps + if: steps.cache-iverilog.outputs.cache-hit != 'true' && runner.os == 'macOS' + shell: bash + run: | + brew install autoconf + - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' shell: bash From fa02d71f65b39c502c8b8c8dde5a749876ecb6ca Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 13 Sep 2025 00:20:53 +0000 Subject: [PATCH 065/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a22f3fb00..d565ead16 100644 --- a/Makefile +++ b/Makefile @@ -159,7 +159,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+55 +YOSYS_VER := 0.57+72 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 3d2bb1db17e119efbf58134acc089c2b5867a451 Mon Sep 17 00:00:00 2001 From: Xing Guo Date: Sat, 13 Sep 2025 11:19:29 +0800 Subject: [PATCH 066/188] verilog_parser: replace manual AST node allocation with typed midrule actions Use Bison's typed midrule actions to construct AST_FCALL nodes with std::unique_ptr, replacing manual 'new' and extra->ast_stack management. This improves type safety, ensures proper ownership, and eliminates potential memory leaks. Ref: https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html --- frontends/verilog/verilog_parser.y | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index d8b0088b9..ef8427679 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3289,15 +3289,19 @@ basic_expr: $$ = AstNode::mkconst_str(@1, *$1); SET_AST_NODE_LOC($$.get(), @1, @1); } | - hierarchical_id attr { - // super sketchy! Orphaned pointer in non-owning extra->ast_stack - AstNode *node = new AstNode(@1, AST_FCALL); - node->str = *$1; - extra->ast_stack.push_back(node); - SET_AST_NODE_LOC(node, @1, @1); - append_attr(node, std::move($2)); + hierarchical_id attr { + // Here we use "Typed Midrule Actions". + // https://www.gnu.org/software/bison/manual/html_node/Typed-Midrule-Actions.html + auto fcall = std::make_unique(@1, AST_FCALL); + AstNode *fcall_node = fcall.get(); + fcall_node->str = *$1; + extra->ast_stack.push_back(fcall_node); + SET_AST_NODE_LOC(fcall_node, @1, @1); + append_attr(fcall_node, std::move($2)); + $$ = std::move(fcall); } TOK_LPAREN arg_list optional_comma TOK_RPAREN { - $$.reset(extra->ast_stack.back()); + log_assert($3 != nullptr); + $$ = std::move($3); extra->ast_stack.pop_back(); } | TOK_TO_SIGNED attr TOK_LPAREN expr TOK_RPAREN { From 1c422fcb6ed31ab9c5f1491c278cbdb97fc85bc1 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 15 Sep 2025 16:48:56 +0200 Subject: [PATCH 067/188] CODEOWNERS: add myself for read_verilog and AST --- CODEOWNERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CODEOWNERS b/CODEOWNERS index ef8c803ed..46d37ad2f 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -30,8 +30,8 @@ docs/source/using_yosys/synthesis/abc.rst @KrystalDelusion @Ravenslofty # These still override previous lines, so be careful not to # accidentally disable any of the above rules. -frontends/verilog/ @zachjs -frontends/ast/ @zachjs +frontends/verilog/ @widlarizer +frontends/ast/ @widlarizer techlibs/intel_alm/ @Ravenslofty techlibs/gowin/ @pepijndevos From 13b3418a7f8cf24bd2706fb8dc8a4530d8ef9e0d Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 15 Jul 2025 04:25:07 +0000 Subject: [PATCH 068/188] Split `abc_module()` into `prepare_module()` and `run_abc()` `prepare_module()` will have to run on the main thread. --- passes/techmap/abc.cc | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 7d81b52d2..680428096 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -180,8 +180,9 @@ struct AbcModuleState { std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr); void dump_loop_graph(FILE *f, int &nr, dict> &edges, pool &workpool, std::vector &in_counts); void handle_loops(AbcSigMap &assign_map, RTLIL::Module *module); - void abc_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector &cells, + void prepare_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector &cells, bool dff_mode, std::string clk_str); + void run_abc(); void extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module); void finish(); }; @@ -775,7 +776,7 @@ struct abc_output_filter } }; -void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector &cells, +void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector &cells, bool dff_mode, std::string clk_str) { map_autoidx = autoidx++; @@ -987,9 +988,12 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab mark_port(assign_map, srst_sig); handle_loops(assign_map, module); +} - buffer = stringf("%s/input.blif", tempdir_name); - f = fopen(buffer.c_str(), "wt"); +void AbcModuleState::run_abc() +{ + std::string buffer = stringf("%s/input.blif", tempdir_name); + FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -1111,8 +1115,6 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab log_push(); if (count_output > 0) { - log_header(design, "Executing ABC.\n"); - auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost(); buffer = stringf("%s/stdcells.genlib", tempdir_name); @@ -1522,8 +1524,6 @@ void AbcModuleState::finish() log("Removing temp directory.\n"); remove_directory(tempdir_name); } - - log_pop(); } // For every signal that connects cells from different sets, or a cell in a set to a cell not in any set, @@ -2163,7 +2163,8 @@ struct AbcPass : public Pass { assign_cell_connection_ports(mod, {&cells}, assign_map); AbcModuleState state(config, initvals); - state.abc_module(design, mod, assign_map, cells, dff_mode, clk_str); + state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str); + state.run_abc(); state.extract(assign_map, design, mod); state.finish(); continue; @@ -2333,7 +2334,8 @@ struct AbcPass : public Pass { state.arst_sig = assign_map(std::get<5>(it.first)); state.srst_polarity = std::get<6>(it.first); state.srst_sig = assign_map(std::get<7>(it.first)); - state.abc_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$"); + state.prepare_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$"); + state.run_abc(); state.extract(assign_map, design, mod); state.finish(); } From 222f457a045e474bcf6712ad167a85d688b55b48 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 15 Jul 2025 05:33:09 +0000 Subject: [PATCH 069/188] Only write out stdcells/lutcosts once for all ABC runs --- passes/techmap/abc.cc | 141 ++++++++++++++++++++++++------------------ 1 file changed, 82 insertions(+), 59 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 680428096..03417b7f2 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -119,6 +119,7 @@ bool cmos_cost; struct AbcConfig { + std::string global_tempdir_name; std::string script_file; std::string exe_file; std::vector liberty_files; @@ -878,9 +879,9 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module abc_script += stringf("read_constr -v \"%s\"; ", config.constr_file); } else if (!config.lut_costs.empty()) - abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name); + abc_script += stringf("read_lut %s/lutdefs.txt; ", config.global_tempdir_name); else - abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name); + abc_script += stringf("read_library %s/stdcells.genlib; ", config.global_tempdir_name); if (!config.script_file.empty()) { const std::string &script_file = config.script_file; @@ -1112,65 +1113,8 @@ void AbcModuleState::run_abc() log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", count_gates, GetSize(signal_list), count_input, count_output); - log_push(); if (count_output > 0) { - auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost(); - - buffer = stringf("%s/stdcells.genlib", tempdir_name); - f = fopen(buffer.c_str(), "wt"); - if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); - fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); - fprintf(f, "GATE ONE 1 Y=CONST1;\n"); - fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_))); - fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_))); - if (enabled_gates.count("AND")) - fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_))); - if (enabled_gates.count("NAND")) - fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_))); - if (enabled_gates.count("OR")) - fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_))); - if (enabled_gates.count("NOR")) - fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_))); - if (enabled_gates.count("XOR")) - fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_))); - if (enabled_gates.count("XNOR")) - fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_))); - if (enabled_gates.count("ANDNOT")) - fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_))); - if (enabled_gates.count("ORNOT")) - fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_))); - if (enabled_gates.count("AOI3")) - fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_))); - if (enabled_gates.count("OAI3")) - fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_))); - if (enabled_gates.count("AOI4")) - fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_))); - if (enabled_gates.count("OAI4")) - fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_))); - if (enabled_gates.count("MUX")) - fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_))); - if (enabled_gates.count("NMUX")) - fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_))); - if (map_mux4) - fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_))); - if (map_mux8) - fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_))); - if (map_mux16) - fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_))); - fclose(f); - - if (!config.lut_costs.empty()) { - buffer = stringf("%s/lutdefs.txt", tempdir_name); - f = fopen(buffer.c_str(), "wt"); - if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); - for (int i = 0; i < GetSize(config.lut_costs); i++) - fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i)); - fclose(f); - } - buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); @@ -1231,6 +1175,65 @@ void AbcModuleState::run_abc() log("Don't call ABC as there is nothing to map.\n"); } +void emit_global_input_files(const AbcConfig &config) +{ + if (!config.lut_costs.empty()) { + std::string buffer = stringf("%s/lutdefs.txt", config.global_tempdir_name.c_str()); + FILE *f = fopen(buffer.c_str(), "wt"); + if (f == nullptr) + log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + for (int i = 0; i < GetSize(config.lut_costs); i++) + fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i)); + fclose(f); + } else { + auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost(); + + std::string buffer = stringf("%s/stdcells.genlib", config.global_tempdir_name.c_str()); + FILE *f = fopen(buffer.c_str(), "wt"); + if (f == nullptr) + log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); + fprintf(f, "GATE ONE 1 Y=CONST1;\n"); + fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_))); + fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_))); + if (enabled_gates.count("AND")) + fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_))); + if (enabled_gates.count("NAND")) + fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_))); + if (enabled_gates.count("OR")) + fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_))); + if (enabled_gates.count("NOR")) + fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_))); + if (enabled_gates.count("XOR")) + fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_))); + if (enabled_gates.count("XNOR")) + fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_))); + if (enabled_gates.count("ANDNOT")) + fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_))); + if (enabled_gates.count("ORNOT")) + fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_))); + if (enabled_gates.count("AOI3")) + fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_))); + if (enabled_gates.count("OAI3")) + fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_))); + if (enabled_gates.count("AOI4")) + fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_))); + if (enabled_gates.count("OAI4")) + fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_))); + if (enabled_gates.count("MUX")) + fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_))); + if (enabled_gates.count("NMUX")) + fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_))); + if (map_mux4) + fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_))); + if (map_mux8) + fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_))); + if (map_mux16) + fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_))); + fclose(f); + } +} + void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module) { if (!did_run_abc) { @@ -1811,6 +1814,13 @@ struct AbcPass : public Pass { config.show_tempdir = design->scratchpad_get_bool("abc.showtmp", false); markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups); + if (config.cleanup) + config.global_tempdir_name = get_base_tmpdir() + "/"; + else + config.global_tempdir_name = "_tmp_"; + config.global_tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; + config.global_tempdir_name = make_temp_dir(config.global_tempdir_name); + if (design->scratchpad_get_bool("abc.debug")) { config.cleanup = false; config.show_tempdir = true; @@ -2139,6 +2149,8 @@ struct AbcPass : public Pass { // enabled_gates.insert("NMUX"); } + emit_global_input_files(config); + for (auto mod : design->selected_modules()) { if (mod->processes.size() > 0) { @@ -2164,9 +2176,12 @@ struct AbcPass : public Pass { AbcModuleState state(config, initvals); state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str); + log_push(); + log_header(design, "Executing ABC.\n"); state.run_abc(); state.extract(assign_map, design, mod); state.finish(); + log_pop(); continue; } @@ -2335,12 +2350,20 @@ struct AbcPass : public Pass { state.srst_polarity = std::get<6>(it.first); state.srst_sig = assign_map(std::get<7>(it.first)); state.prepare_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$"); + log_push(); + log_header(design, "Executing ABC.\n"); state.run_abc(); state.extract(assign_map, design, mod); state.finish(); + log_pop(); } } + if (config.cleanup) { + log("Removing global temp directory.\n"); + remove_directory(config.global_tempdir_name); + } + log_pop(); } } AbcPass; From 38f8165c8079bf9f1e853ef1ff15237aa48d4527 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 10 Sep 2025 22:53:53 +0000 Subject: [PATCH 070/188] Remove direct RTLIL access from gate_t --- passes/techmap/abc.cc | 54 ++++++++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 03417b7f2..a0521e269 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -104,8 +104,10 @@ struct gate_t gate_type_t type; int in1, in2, in3, in4; bool is_port; - RTLIL::SigBit bit; + bool bit_is_wire; + bool bit_is_1; RTLIL::State init; + std::string bit_str; }; bool map_mux4; @@ -156,6 +158,7 @@ struct AbcModuleState { int map_autoidx = 0; std::vector signal_list; + std::vector signal_bits; dict signal_map; FfInitVals &initvals; bool had_init = false; @@ -204,10 +207,13 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g gate.in3 = -1; gate.in4 = -1; gate.is_port = bit.wire != nullptr && val.is_port; - gate.bit = bit; + gate.bit_is_wire = bit.wire != nullptr; + gate.bit_is_1 = bit == State::S1; gate.init = initvals(bit); - signal_list.push_back(gate); + gate.bit_str = std::string(log_signal(bit)); signal_map[bit] = gate.id; + signal_list.push_back(std::move(gate)); + signal_bits.push_back(bit); } gate_t &gate = signal_list[signal_map[bit]]; @@ -463,17 +469,17 @@ std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **o if (sid < GetSize(signal_list)) { - auto sig = signal_list.at(sid); - if (sig.bit.wire != nullptr) + const auto &bit = signal_bits.at(sid); + if (bit.wire != nullptr) { - std::string s = stringf("$abc$%d$%s", map_autoidx, sig.bit.wire->name.c_str()+1); - if (sig.bit.wire->width != 1) - s += stringf("[%d]", sig.bit.offset); + std::string s = stringf("$abc$%d$%s", map_autoidx, bit.wire->name.c_str()+1); + if (bit.wire->width != 1) + s += stringf("[%d]", bit.offset); if (isnew) s += "_new"; s += postfix; if (orig_wire != nullptr) - *orig_wire = sig.bit.wire; + *orig_wire = bit.wire; return s; } } @@ -501,7 +507,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict> &edg } for (auto n : nodes) - fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit), + fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, signal_list[n].bit_str.c_str(), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) @@ -562,7 +568,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) int id = *workpool.begin(); workpool.erase(id); - // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit)); + // log("Removing non-loop node %d from graph: %s\n", id, signal_list[id].bit_str); for (int id2 : edges[id]) { log_assert(in_edges_count[id2] > 0); @@ -582,8 +588,8 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) for (auto &edge_it : edges) { int id2 = edge_it.first; - RTLIL::Wire *w1 = signal_list[id1].bit.wire; - RTLIL::Wire *w2 = signal_list[id2].bit.wire; + RTLIL::Wire *w1 = signal_bits[id1].wire; + RTLIL::Wire *w2 = signal_bits[id2].wire; if (w1 == nullptr) id1 = id2; else if (w2 == nullptr) @@ -605,7 +611,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) continue; } - log_assert(signal_list[id1].bit.wire != nullptr); + log_assert(signal_bits[id1].wire != nullptr); std::stringstream sstr; sstr << "$abcloop$" << (autoidx++); @@ -615,10 +621,10 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) for (int id2 : edges[id1]) { if (first_line) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), - log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); + signal_list[id1].bit_str, signal_list[id2].bit_str); else log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", - log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit)); + signal_list[id1].bit_str, signal_list[id2].bit_str); first_line = false; } @@ -641,7 +647,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) } edges[id1].swap(edges[id3]); - connect(assign_map, module, RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit)); + connect(assign_map, module, RTLIL::SigSig(signal_bits[id3], signal_bits[id1])); dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count); } } @@ -1006,7 +1012,7 @@ void AbcModuleState::run_abc() if (!si.is_port || si.type != G(NONE)) continue; fprintf(f, " ys__n%d", si.id); - pi_map[count_input++] = log_signal(si.bit); + pi_map[count_input++] = si.bit_str; } if (count_input == 0) fprintf(f, " dummy_input\n"); @@ -1018,17 +1024,17 @@ void AbcModuleState::run_abc() if (!si.is_port || si.type == G(NONE)) continue; fprintf(f, " ys__n%d", si.id); - po_map[count_output++] = log_signal(si.bit); + po_map[count_output++] = si.bit_str; } fprintf(f, "\n"); for (auto &si : signal_list) - fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit)); + fprintf(f, "# ys__n%-5d %s\n", si.id, si.bit_str.c_str()); for (auto &si : signal_list) { - if (si.bit.wire == nullptr) { + if (!si.bit_is_wire) { fprintf(f, ".names ys__n%d\n", si.id); - if (si.bit == RTLIL::State::S1) + if (si.bit_is_1) fprintf(f, "1\n"); } } @@ -1503,12 +1509,12 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL snprintf(buffer, 100, "\\ys__n%d", si.id); RTLIL::SigSig conn; if (si.type != G(NONE)) { - conn.first = si.bit; + conn.first = signal_bits[si.id]; conn.second = module->wire(remap_name(buffer)); out_wires++; } else { conn.first = module->wire(remap_name(buffer)); - conn.second = si.bit; + conn.second = signal_bits[si.id]; in_wires++; } connect(assign_map, module, conn); From 27462da20895706b6a9b362c8daa042a06d222a8 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Sat, 26 Jul 2025 02:45:21 +0000 Subject: [PATCH 071/188] Run ABCs in parallel. Large circuits can run hundreds or thousands of ABCs in a single AbcPass. For some circuits, some of those ABC runs can run for hundreds of seconds. Running ABCs in parallel with each other and in parallel with main-thread processing (reading and writing BLIF files, copying ABC BLIF output into the design) can give large speedups. --- Makefile | 14 ++- kernel/threading.cc | 45 +++++++++ kernel/threading.h | 159 +++++++++++++++++++++++++++++ kernel/yosys.cc | 2 +- misc/create_vcxsrc.sh | 1 + passes/techmap/abc.cc | 229 ++++++++++++++++++++++++++---------------- 6 files changed, 362 insertions(+), 88 deletions(-) create mode 100644 kernel/threading.cc create mode 100644 kernel/threading.h diff --git a/Makefile b/Makefile index d565ead16..4aae25c3c 100644 --- a/Makefile +++ b/Makefile @@ -44,7 +44,12 @@ LINK_ABC := 0 # Needed for environments that can't run executables (i.e. emscripten, wasm) DISABLE_SPAWN := 0 # Needed for environments that don't have proper thread support (i.e. emscripten, wasm--for now) +ENABLE_THREADS := 1 +ifeq ($(ENABLE_THREADS),1) DISABLE_ABC_THREADS := 0 +else +DISABLE_ABC_THREADS := 1 +endif # clang sanitizers SANITIZER = @@ -300,6 +305,7 @@ DISABLE_SPAWN := 1 ifeq ($(ENABLE_ABC),1) LINK_ABC := 1 +ENABLE_THREADS := 0 DISABLE_ABC_THREADS := 1 endif @@ -457,6 +463,11 @@ CXXFLAGS := -Og -DDEBUG $(filter-out $(OPT_LEVEL),$(CXXFLAGS)) STRIP := endif +ifeq ($(ENABLE_THREADS),1) +CXXFLAGS += -DYOSYS_ENABLE_THREADS +LIBS += -lpthread +endif + ifeq ($(ENABLE_ABC),1) CXXFLAGS += -DYOSYS_ENABLE_ABC ifeq ($(LINK_ABC),1) @@ -612,6 +623,7 @@ $(eval $(call add_include_file,kernel/satgen.h)) $(eval $(call add_include_file,kernel/scopeinfo.h)) $(eval $(call add_include_file,kernel/sexpr.h)) $(eval $(call add_include_file,kernel/sigtools.h)) +$(eval $(call add_include_file,kernel/threading.h)) $(eval $(call add_include_file,kernel/timinginfo.h)) $(eval $(call add_include_file,kernel/utils.h)) $(eval $(call add_include_file,kernel/yosys.h)) @@ -638,7 +650,7 @@ OBJS += kernel/log_compat.o endif OBJS += kernel/binding.o kernel/tclapi.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o -OBJS += kernel/drivertools.o kernel/functional.o +OBJS += kernel/drivertools.o kernel/functional.o kernel/threading.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o endif diff --git a/kernel/threading.cc b/kernel/threading.cc new file mode 100644 index 000000000..49fddaa7c --- /dev/null +++ b/kernel/threading.cc @@ -0,0 +1,45 @@ +#include "kernel/yosys_common.h" +#include "kernel/threading.h" + +YOSYS_NAMESPACE_BEGIN + +void DeferredLogs::flush() +{ + for (auto &m : logs) + if (m.error) + YOSYS_NAMESPACE_PREFIX log_error("%s", m.text.c_str()); + else + YOSYS_NAMESPACE_PREFIX log("%s", m.text.c_str()); +} + +int ThreadPool::pool_size(int reserved_cores, int max_threads) +{ +#ifdef YOSYS_ENABLE_THREADS + int num_threads = std::min(std::thread::hardware_concurrency() - reserved_cores, max_threads); + return std::max(0, num_threads); +#else + return 0; +#endif +} + +ThreadPool::ThreadPool(int pool_size, std::function b) + : body(std::move(b)) +{ +#ifdef YOSYS_ENABLE_THREADS + threads.reserve(pool_size); + for (int i = 0; i < pool_size; i++) + threads.emplace_back([i, this]{ body(i); }); +#else + log_assert(pool_size == 0); +#endif +} + +ThreadPool::~ThreadPool() +{ +#ifdef YOSYS_ENABLE_THREADS + for (auto &t : threads) + t.join(); +#endif +} + +YOSYS_NAMESPACE_END diff --git a/kernel/threading.h b/kernel/threading.h new file mode 100644 index 000000000..8c08d670c --- /dev/null +++ b/kernel/threading.h @@ -0,0 +1,159 @@ +#include + +#ifdef YOSYS_ENABLE_THREADS +#include +#include +#include +#endif + +#include "kernel/yosys_common.h" +#include "kernel/log.h" + +#ifndef YOSYS_THREADING_H +#define YOSYS_THREADING_H + +YOSYS_NAMESPACE_BEGIN + +// Concurrent queue implementation. Not fast, but simple. +// Multi-producer, multi-consumer, optionally bounded. +// When YOSYS_ENABLE_THREADS is not defined, this is just a non-thread-safe non-blocking deque. +template +class ConcurrentQueue +{ +public: + ConcurrentQueue(int capacity = INT_MAX) + : capacity(capacity) {} + // Push an element into the queue. If it's at capacity, block until there is room. + void push_back(T t) + { +#ifdef YOSYS_ENABLE_THREADS + std::unique_lock lock(mutex); + not_full_condition.wait(lock, [this] { return static_cast(contents.size()) < capacity; }); + if (contents.empty()) + not_empty_condition.notify_one(); +#endif + log_assert(!closed); + contents.push_back(std::move(t)); +#ifdef YOSYS_ENABLE_THREADS + if (static_cast(contents.size()) < capacity) + not_full_condition.notify_one(); +#endif + } + // Signal that no more elements will be produced. `pop_front()` will return nullopt. + void close() + { +#ifdef YOSYS_ENABLE_THREADS + std::unique_lock lock(mutex); + not_empty_condition.notify_all(); +#endif + closed = true; + } + // Pop an element from the queue. Blocks until an element is available + // or the queue is closed and empty. + std::optional pop_front() + { + return pop_front_internal(true); + } + // Pop an element from the queue. Does not block, just returns nullopt if the + // queue is empty. + std::optional try_pop_front() + { + return pop_front_internal(false); + } +private: +#ifdef YOSYS_ENABLE_THREADS + std::optional pop_front_internal(bool wait) + { + std::unique_lock lock(mutex); + if (wait) { + not_empty_condition.wait(lock, [this] { return !contents.empty() || closed; }); + } +#else + std::optional pop_front_internal(bool) + { +#endif + if (contents.empty()) + return std::nullopt; +#ifdef YOSYS_ENABLE_THREADS + if (static_cast(contents.size()) == capacity) + not_full_condition.notify_one(); +#endif + T result = std::move(contents.front()); + contents.pop_front(); +#ifdef YOSYS_ENABLE_THREADS + if (!contents.empty()) + not_empty_condition.notify_one(); +#endif + return std::move(result); + } + +#ifdef YOSYS_ENABLE_THREADS + std::mutex mutex; + // Signals one waiter thread when the queue changes and is not full. + std::condition_variable not_full_condition; + // Signals one waiter thread when the queue changes and is not empty. + std::condition_variable not_empty_condition; +#endif + std::deque contents; + int capacity; + bool closed = false; +}; + +class DeferredLogs +{ +public: + template + void log(FmtString...> fmt, Args... args) + { + logs.push_back({fmt.format(args...), false}); + } + template + void log_error(FmtString...> fmt, Args... args) + { + logs.push_back({fmt.format(args...), true}); + } + void flush(); +private: + struct Message + { + std::string text; + bool error; + }; + std::vector logs; +}; + +class ThreadPool +{ +public: + // Computes the number of worker threads to use. + // `reserved_cores` cores are set aside for other threads (e.g. work on the main thread). + // `max_threads` --- don't return more workers than this. + // The result may be 0. + static int pool_size(int reserved_cores, int max_threads); + + // Create a pool of threads running the given closure (parameterized by thread number). + // `pool_size` must be the result of a `pool_size()` call. + ThreadPool(int pool_size, std::function b); + ThreadPool(ThreadPool &&other) = delete; + // Waits for all threads to terminate. Make sure those closures return! + ~ThreadPool(); + + // Return the number of threads in the pool. + int num_threads() const + { +#ifdef YOSYS_ENABLE_THREADS + return threads.size(); +#else + return 0; +#endif + } +private: + std::function body; +#ifdef YOSYS_ENABLE_THREADS + std::vector threads; +#endif +}; + +YOSYS_NAMESPACE_END + +#endif // YOSYS_THREADING_H diff --git a/kernel/yosys.cc b/kernel/yosys.cc index dc640fae9..95beca75c 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -177,7 +177,7 @@ int run_command(const std::string &command, std::function "$vcxsrc"/YosysVS/YosysVS.vcxproj.new sed -i 's,,\n stdcpp17\n /Zc:__cplusplus %(AdditionalOptions),g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new +sed -i 's,,YOSYS_ENABLE_THREADS;,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new if [ -f "/usr/include/FlexLexer.h" ] ; then sed -i 's,,;..\\yosys\\libs\\flex,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new fi diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index a0521e269..4a65671a2 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -48,6 +48,7 @@ #include "kernel/ff.h" #include "kernel/cost.h" #include "kernel/log.h" +#include "kernel/threading.h" #include #include #include @@ -55,6 +56,7 @@ #include #include #include +#include #include #ifndef _WIN32 @@ -153,30 +155,41 @@ struct AbcSigVal { using AbcSigMap = SigValMap; -struct AbcModuleState { +// Used by off-main-threads. Contains no direct or indirect access to RTLIL. +struct RunAbcState { const AbcConfig &config; - int map_autoidx = 0; + std::string tempdir_name; std::vector signal_list; + bool did_run = false; + bool err = false; + DeferredLogs logs; + dict pi_map, po_map; + + RunAbcState(const AbcConfig &config) : config(config) {} + void run(); +}; + +struct AbcModuleState { + RunAbcState run_abc; + + int map_autoidx = 0; std::vector signal_bits; dict signal_map; FfInitVals &initvals; bool had_init = false; - bool did_run_abc = false; bool clk_polarity = false; bool en_polarity = false; bool arst_polarity = false; bool srst_polarity = false; RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig; - dict pi_map, po_map; int undef_bits_lost = 0; - std::string tempdir_name; - AbcModuleState(const AbcConfig &config, FfInitVals &initvals) - : config(config), initvals(initvals) {} + : run_abc(config), initvals(initvals) {} + AbcModuleState(AbcModuleState&&) = delete; int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1); void mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig); @@ -186,7 +199,6 @@ struct AbcModuleState { void handle_loops(AbcSigMap &assign_map, RTLIL::Module *module); void prepare_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector &cells, bool dff_mode, std::string clk_str); - void run_abc(); void extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module); void finish(); }; @@ -200,7 +212,7 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g if (signal_map.count(bit) == 0) { gate_t gate; - gate.id = signal_list.size(); + gate.id = run_abc.signal_list.size(); gate.type = G(NONE); gate.in1 = -1; gate.in2 = -1; @@ -212,11 +224,11 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g gate.init = initvals(bit); gate.bit_str = std::string(log_signal(bit)); signal_map[bit] = gate.id; - signal_list.push_back(std::move(gate)); + run_abc.signal_list.push_back(std::move(gate)); signal_bits.push_back(bit); } - gate_t &gate = signal_list[signal_map[bit]]; + gate_t &gate = run_abc.signal_list[signal_map[bit]]; if (gate_type != G(NONE)) gate.type = gate_type; @@ -236,7 +248,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig) { for (auto &bit : assign_map(sig)) if (bit.wire != nullptr && signal_map.count(bit) > 0) - signal_list[signal_map[bit]].is_port = true; + run_abc.signal_list[signal_map[bit]].is_port = true; } bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff) @@ -315,7 +327,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo if (keepff) { SigBit bit = ff.sig_q; if (assign_map(bit).wire != nullptr) { - signal_list[gate_id].is_port = true; + run_abc.signal_list[gate_id].is_port = true; } if (bit.wire != nullptr) bit.wire->attributes[ID::keep] = 1; @@ -467,7 +479,7 @@ std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **o size_t postfix_start = abc_sname.find_first_not_of("0123456789"); std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : ""; - if (sid < GetSize(signal_list)) + if (sid < GetSize(run_abc.signal_list)) { const auto &bit = signal_bits.at(sid); if (bit.wire != nullptr) @@ -507,7 +519,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict> &edg } for (auto n : nodes) - fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, signal_list[n].bit_str.c_str(), + fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, run_abc.signal_list[n].bit_str.c_str(), n, in_counts[n], workpool.count(n) ? ", shape=box" : ""); for (auto &e : edges) @@ -529,7 +541,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) // (Kahn, Arthur B. (1962), "Topological sorting of large networks") dict> edges; - std::vector in_edges_count(signal_list.size()); + std::vector in_edges_count(run_abc.signal_list.size()); pool workpool; FILE *dot_f = nullptr; @@ -538,7 +550,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) // uncomment for troubleshooting the loop detection code // dot_f = fopen("test.dot", "w"); - for (auto &g : signal_list) { + for (auto &g : run_abc.signal_list) { if (g.type == G(NONE) || g.type == G(FF) || g.type == G(FF0) || g.type == G(FF1)) { workpool.insert(g.id); } else { @@ -621,29 +633,29 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) for (int id2 : edges[id1]) { if (first_line) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), - signal_list[id1].bit_str, signal_list[id2].bit_str); + run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str); else log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", - signal_list[id1].bit_str, signal_list[id2].bit_str); + run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str); first_line = false; } int id3 = map_signal(assign_map, RTLIL::SigSpec(wire)); - signal_list[id1].is_port = true; - signal_list[id3].is_port = true; + run_abc.signal_list[id1].is_port = true; + run_abc.signal_list[id3].is_port = true; log_assert(id3 == int(in_edges_count.size())); in_edges_count.push_back(0); workpool.insert(id3); for (int id2 : edges[id1]) { - if (signal_list[id2].in1 == id1) - signal_list[id2].in1 = id3; - if (signal_list[id2].in2 == id1) - signal_list[id2].in2 = id3; - if (signal_list[id2].in3 == id1) - signal_list[id2].in3 = id3; - if (signal_list[id2].in4 == id1) - signal_list[id2].in4 = id3; + if (run_abc.signal_list[id2].in1 == id1) + run_abc.signal_list[id2].in1 = id3; + if (run_abc.signal_list[id2].in2 == id1) + run_abc.signal_list[id2].in2 = id3; + if (run_abc.signal_list[id2].in3 == id1) + run_abc.signal_list[id2].in3 = id3; + if (run_abc.signal_list[id2].in4 == id1) + run_abc.signal_list[id2].in4 = id3; } edges[id1].swap(edges[id3]); @@ -724,14 +736,14 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho struct abc_output_filter { - const AbcModuleState &state; + RunAbcState &state; bool got_cr; int escape_seq_state; std::string linebuf; std::string tempdir_name; bool show_tempdir; - abc_output_filter(const AbcModuleState& state, std::string tempdir_name, bool show_tempdir) + abc_output_filter(RunAbcState& state, std::string tempdir_name, bool show_tempdir) : state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir) { got_cr = false; @@ -759,7 +771,7 @@ struct abc_output_filter return; } if (ch == '\n') { - log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); + state.logs.log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -772,7 +784,7 @@ struct abc_output_filter { int pi, po; if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) { - log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n", + state.logs.log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n", pi, state.pi_map.count(pi) ? state.pi_map.at(pi).c_str() : "???", po, state.po_map.count(po) ? state.po_map.at(po).c_str() : "???"); return; @@ -858,16 +870,17 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module if (dff_mode && clk_sig.empty()) log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); + const AbcConfig &config = run_abc.config; if (config.cleanup) - tempdir_name = get_base_tmpdir() + "/"; + run_abc.tempdir_name = get_base_tmpdir() + "/"; else - tempdir_name = "_tmp_"; - tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; - tempdir_name = make_temp_dir(tempdir_name); + run_abc.tempdir_name = "_tmp_"; + run_abc.tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX"; + run_abc.tempdir_name = make_temp_dir(run_abc.tempdir_name); log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", - module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str()); + module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str()); - std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name); + std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name); if (!config.liberty_files.empty() || !config.genlib_files.empty()) { std::string dont_use_args; @@ -933,15 +946,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3); if (config.abc_dress) - abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name); - abc_script += stringf("; write_blif %s/output.blif", tempdir_name); + abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name); + abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); for (size_t i = 0; i+1 < abc_script.size(); i++) if (abc_script[i] == ';' && abc_script[i+1] == ' ') abc_script[i+1] = '\n'; - std::string buffer = stringf("%s/abc.script", tempdir_name); + std::string buffer = stringf("%s/abc.script", run_abc.tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); @@ -997,12 +1010,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } -void AbcModuleState::run_abc() +void RunAbcState::run() { std::string buffer = stringf("%s/input.blif", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); - if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); + if (f == nullptr) { + logs.log("Opening %s for writing failed: %s\n", buffer, strerror(errno)); + err = true; + return; + } fprintf(f, ".model netlist\n"); @@ -1117,13 +1133,14 @@ void AbcModuleState::run_abc() fprintf(f, ".end\n"); fclose(f); - log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", + logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", count_gates, GetSize(signal_list), count_input, count_output); if (count_output > 0) { buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); - log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); + logs.log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); + errno = 0; #ifndef YOSYS_LINK_ABC abc_output_filter filt(*this, tempdir_name, config.show_tempdir); int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); @@ -1172,10 +1189,10 @@ void AbcModuleState::run_abc() temp_stdouterr_r.close(); #endif if (ret != 0) { - log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); + logs.log_error("ABC: execution of command \"%s\" failed: return code %d (errno=%d).\n", buffer, ret, errno); return; } - did_run_abc = true; + did_run = true; return; } log("Don't call ABC as there is nothing to map.\n"); @@ -1242,19 +1259,23 @@ void emit_global_input_files(const AbcConfig &config) void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module) { - if (!did_run_abc) { + log_push(); + log_header(design, "Executed ABC.\n"); + run_abc.logs.flush(); + if (!run_abc.did_run) { + finish(); return; } - std::string buffer = stringf("%s/%s", tempdir_name, "output.blif"); + std::string buffer = stringf("%s/%s", run_abc.tempdir_name, "output.blif"); std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) log_error("Can't open ABC output file `%s'.\n", buffer); - bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty(); + bool builtin_lib = run_abc.config.liberty_files.empty() && run_abc.config.genlib_files.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; - parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode); + parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, run_abc.config.sop_mode); ifs.close(); @@ -1503,7 +1524,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL for (auto &it : cell_stats) log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second); int in_wires = 0, out_wires = 0; - for (auto &si : signal_list) + for (auto &si : run_abc.signal_list) if (si.is_port) { char buffer[100]; snprintf(buffer, 100, "\\ys__n%d", si.id); @@ -1519,20 +1540,22 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL } connect(assign_map, module, conn); } - log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); + log("ABC RESULTS: internal signals: %8d\n", int(run_abc.signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); delete mapped_design; + finish(); } void AbcModuleState::finish() { - if (config.cleanup) + if (run_abc.config.cleanup) { log("Removing temp directory.\n"); - remove_directory(tempdir_name); + remove_directory(run_abc.tempdir_name); } + log_pop(); } // For every signal that connects cells from different sets, or a cell in a set to a cell not in any set, @@ -2182,12 +2205,8 @@ struct AbcPass : public Pass { AbcModuleState state(config, initvals); state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str); - log_push(); - log_header(design, "Executing ABC.\n"); - state.run_abc(); + state.run_abc.run(); state.extract(assign_map, design, mod); - state.finish(); - log_pop(); continue; } @@ -2332,36 +2351,74 @@ struct AbcPass : public Pass { } log_header(design, "Summary of detected clock domains:\n"); - for (auto &it : assigned_cells) - log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second), - std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), - std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)), - std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)), - std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first))); - { std::vector*> cell_sets; - for (auto &it : assigned_cells) + for (auto &it : assigned_cells) { + log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second), + std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), + std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)), + std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)), + std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first))); cell_sets.push_back(&it.second); + } assign_cell_connection_ports(mod, cell_sets, assign_map); } + + // Reserve one core for our main thread, and don't create more worker threads + // than ABC runs. + int max_threads = assigned_cells.size(); + if (max_threads <= 1) { + // Just do everything on the main thread. + max_threads = 0; + } +#ifdef YOSYS_LINK_ABC + // ABC does't support multithreaded calls so don't call it off the main thread. + max_threads = 0; +#endif + int num_worker_threads = ThreadPool::pool_size(1, max_threads); + ConcurrentQueue> work_queue(num_worker_threads); + ConcurrentQueue> work_finished_queue; + int work_finished_count = 0; + ThreadPool worker_threads(num_worker_threads, [&](int){ + while (std::optional> work = + work_queue.pop_front()) { + // Only the `run_abc` component is safe to touch here! + (*work)->run_abc.run(); + work_finished_queue.push_back(std::move(*work)); + } + }); for (auto &it : assigned_cells) { - AbcModuleState state(config, initvals); - state.clk_polarity = std::get<0>(it.first); - state.clk_sig = assign_map(std::get<1>(it.first)); - state.en_polarity = std::get<2>(it.first); - state.en_sig = assign_map(std::get<3>(it.first)); - state.arst_polarity = std::get<4>(it.first); - state.arst_sig = assign_map(std::get<5>(it.first)); - state.srst_polarity = std::get<6>(it.first); - state.srst_sig = assign_map(std::get<7>(it.first)); - state.prepare_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$"); - log_push(); - log_header(design, "Executing ABC.\n"); - state.run_abc(); - state.extract(assign_map, design, mod); - state.finish(); - log_pop(); + // Process ABC results that have already finished before queueing another ABC. + // This should keep our memory usage down. + while (std::optional> work = + work_finished_queue.try_pop_front()) { + (*work)->extract(assign_map, design, mod); + ++work_finished_count; + } + std::unique_ptr state = std::make_unique(config, initvals); + state->clk_polarity = std::get<0>(it.first); + state->clk_sig = assign_map(std::get<1>(it.first)); + state->en_polarity = std::get<2>(it.first); + state->en_sig = assign_map(std::get<3>(it.first)); + state->arst_polarity = std::get<4>(it.first); + state->arst_sig = assign_map(std::get<5>(it.first)); + state->srst_polarity = std::get<6>(it.first); + state->srst_sig = assign_map(std::get<7>(it.first)); + state->prepare_module(design, mod, assign_map, it.second, !state->clk_sig.empty(), "$"); + if (num_worker_threads > 0) { + work_queue.push_back(std::move(state)); + } else { + // Just run everything on the main thread. + state->run_abc.run(); + work_finished_queue.push_back(std::move(state)); + } + } + work_queue.close(); + while (work_finished_count < static_cast(assigned_cells.size())) { + std::optional> work = + work_finished_queue.pop_front(); + (*work)->extract(assign_map, design, mod); + ++work_finished_count; } } From ae0ca7578a4450347dc7a545073315f72eaec19a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 8 Aug 2025 05:26:30 +0000 Subject: [PATCH 072/188] Use a pool of ABC processes. Doing ABC runs in parallel can actually make things slower when every ABC run requires spawning an ABC subprocess --- especially when using popen(), which on glibc does not use vfork(). What seems to happen is that constant fork()ing keeps making the main process data pages copy-on-write, so the main process code that is setting up each ABC call takes a lot of minor page-faults, slowing it down. The solution is pretty straightforward although a little tricky to implement. We just reuse ABC subprocesses. Instead of passing the ABC script name on the command line, we spawn an ABC REPL and pipe a command into it to source the script. When that's done we echo an `ABC_DONE` token instead of exiting. Yosys then puts the ABC process onto a stack which we can pull from the next time we do an ABC run. For one of our large designs, this is an additional 5x speedup of the primary AbcPass. It does 5155 ABC runs, all very small; runtime of the AbcPass goes from 760s to 149s (not very scientific benchmarking but the effect size is large). --- kernel/threading.h | 27 ++++++ passes/techmap/abc.cc | 207 +++++++++++++++++++++++++++++++++++++++--- 2 files changed, 221 insertions(+), 13 deletions(-) diff --git a/kernel/threading.h b/kernel/threading.h index 8c08d670c..c34abf850 100644 --- a/kernel/threading.h +++ b/kernel/threading.h @@ -154,6 +154,33 @@ private: #endif }; +template +class ConcurrentStack +{ +public: + void push_back(T &&t) { +#ifdef YOSYS_ENABLE_THREADS + std::lock_guard lock(mutex); +#endif + contents.push_back(std::move(t)); + } + std::optional try_pop_back() { +#ifdef YOSYS_ENABLE_THREADS + std::lock_guard lock(mutex); +#endif + if (contents.empty()) + return std::nullopt; + T result = std::move(contents.back()); + contents.pop_back(); + return result; + } +private: +#ifdef YOSYS_ENABLE_THREADS + std::mutex mutex; +#endif + std::vector contents; +}; + YOSYS_NAMESPACE_END #endif // YOSYS_THREADING_H diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4a65671a2..82a5124ae 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -59,6 +59,11 @@ #include #include +#ifdef __linux__ +# include +# include +# include +#endif #ifndef _WIN32 # include # include @@ -153,6 +158,121 @@ struct AbcSigVal { } }; +#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) +struct AbcProcess +{ + pid_t pid; + int to_child_pipe; + int from_child_pipe; + + AbcProcess() : pid(0), to_child_pipe(-1), from_child_pipe(-1) {} + AbcProcess(AbcProcess &&other) { + pid = other.pid; + to_child_pipe = other.to_child_pipe; + from_child_pipe = other.from_child_pipe; + other.pid = 0; + other.to_child_pipe = other.from_child_pipe = -1; + } + AbcProcess &operator=(AbcProcess &&other) { + if (this != &other) { + pid = other.pid; + to_child_pipe = other.to_child_pipe; + from_child_pipe = other.from_child_pipe; + other.pid = 0; + other.to_child_pipe = other.from_child_pipe = -1; + } + return *this; + } + ~AbcProcess() { + if (pid == 0) + return; + if (to_child_pipe >= 0) + close(to_child_pipe); + int status; + int ret = waitpid(pid, &status, 0); + if (ret != pid) { + log_error("waitpid(%d) failed", pid); + } + if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) { + log_error("ABC failed with status %X", status); + } + if (from_child_pipe >= 0) + close(from_child_pipe); + } +}; + +std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { + // Open pipes O_CLOEXEC so we don't leak any of the fds into racing + // fork()s. + int to_child_pipe[2]; + if (pipe2(to_child_pipe, O_CLOEXEC) != 0) { + logs.log_error("pipe failed"); + return std::nullopt; + } + int from_child_pipe[2]; + if (pipe2(from_child_pipe, O_CLOEXEC) != 0) { + logs.log_error("pipe failed"); + return std::nullopt; + } + + AbcProcess result; + result.to_child_pipe = to_child_pipe[1]; + result.from_child_pipe = from_child_pipe[0]; + // Allow the child side of the pipes to be inherited. + fcntl(to_child_pipe[0], F_SETFD, 0); + fcntl(from_child_pipe[1], F_SETFD, 0); + + posix_spawn_file_actions_t file_actions; + if (posix_spawn_file_actions_init(&file_actions) != 0) { + logs.log_error("posix_spawn_file_actions_init failed"); + return std::nullopt; + } + + if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[1]) != 0) { + logs.log_error("posix_spawn_file_actions_addclose failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[0]) != 0) { + logs.log_error("posix_spawn_file_actions_addclose failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_adddup2(&file_actions, to_child_pipe[0], STDIN_FILENO) != 0) { + logs.log_error("posix_spawn_file_actions_adddup2 failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDOUT_FILENO) != 0) { + logs.log_error("posix_spawn_file_actions_adddup2 failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDERR_FILENO) != 0) { + logs.log_error("posix_spawn_file_actions_adddup2 failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) { + logs.log_error("posix_spawn_file_actions_addclose failed"); + return std::nullopt; + } + if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[1]) != 0) { + logs.log_error("posix_spawn_file_actions_addclose failed"); + return std::nullopt; + } + + char arg1[] = "-s"; + char* argv[] = { strdup(abc_exe), arg1, nullptr }; + if (0 != posix_spawn(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) { + logs.log_error("posix_spawn %s failed", abc_exe); + return std::nullopt; + } + free(argv[0]); + posix_spawn_file_actions_destroy(&file_actions); + close(to_child_pipe[0]); + close(from_child_pipe[1]); + return result; +} +#else +struct AbcProcess {}; +#endif + using AbcSigMap = SigValMap; // Used by off-main-threads. Contains no direct or indirect access to RTLIL. @@ -167,7 +287,7 @@ struct RunAbcState { dict pi_map, po_map; RunAbcState(const AbcConfig &config) : config(config) {} - void run(); + void run(ConcurrentStack &process_pool); }; struct AbcModuleState { @@ -1010,7 +1130,42 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module handle_loops(assign_map, module); } -void RunAbcState::run() +bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { + std::string line; + char buf[1024]; + while (true) { + int ret = read(fd, buf, sizeof(buf) - 1); + if (ret < 0) { + logs.log_error("Failed to read from ABC, errno=%d", errno); + return false; + } + if (ret == 0) { + logs.log_error("ABC exited prematurely"); + return false; + } + char *start = buf; + char *end = buf + ret; + while (start < end) { + char *p = static_cast(memchr(start, '\n', end - start)); + if (p == nullptr) { + break; + } + line.append(start, p + 1 - start); + // ABC seems to actually print "ABC_DONE \n", but we probably shouldn't + // rely on that extra space being output. + if (line.substr(0, 8) == "ABC_DONE") { + // Ignore any leftover output, there should only be a prompt perhaps + return true; + } + filt.next_line(line); + line.clear(); + start = p + 1; + } + line.append(start, end - start); + } +} + +void RunAbcState::run(ConcurrentStack &process_pool) { std::string buffer = stringf("%s/input.blif", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); @@ -1137,14 +1292,12 @@ void RunAbcState::run() count_gates, GetSize(signal_list), count_input, count_output); if (count_output > 0) { - buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); - logs.log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); + std::string tmp_script_name = stringf("%s/abc.script", tempdir_name); + logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, tempdir_name, config.show_tempdir)); errno = 0; -#ifndef YOSYS_LINK_ABC abc_output_filter filt(*this, tempdir_name, config.show_tempdir); - int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); -#else +#ifdef YOSYS_LINK_ABC string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name); FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); if (temp_stdouterr_w == NULL) @@ -1165,7 +1318,6 @@ void RunAbcState::run() fclose(temp_stdouterr_w); // These needs to be mutable, supposedly due to getopt char *abc_argv[5]; - string tmp_script_name = stringf("%s/abc.script", tempdir_name); abc_argv[0] = strdup(config.exe_file.c_str()); abc_argv[1] = strdup("-s"); abc_argv[2] = strdup("-f"); @@ -1183,13 +1335,40 @@ void RunAbcState::run() fclose(old_stdout); fclose(old_stderr); std::ifstream temp_stdouterr_r(temp_stdouterr_name); - abc_output_filter filt(*this, tempdir_name, config.show_tempdir); for (std::string line; std::getline(temp_stdouterr_r, line); ) filt.next_line(line + "\n"); temp_stdouterr_r.close(); +#elif defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) + AbcProcess process; + if (std::optional process_opt = process_pool.try_pop_back()) { + process = std::move(process_opt.value()); + } else if (std::optional process_opt = spawn_abc(config.exe_file.c_str(), logs)) { + process = std::move(process_opt.value()); + } else { + return; + } + std::string cmd = stringf( + // This makes ABC switch stdout to line buffering, which we need + // to see our ABC_DONE message. + "set abcout /dev/stdout\n" + "empty\n" + "source %s\n" + "echo \"ABC_DONE\"\n", tmp_script_name); + int ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); + if (ret != static_cast(cmd.size())) { + logs.log_error("write failed"); + return; + } + ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1; + if (ret == 0) { + process_pool.push_back(std::move(process)); + } +#else + std::string cmd = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str()); + int ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); #endif if (ret != 0) { - logs.log_error("ABC: execution of command \"%s\" failed: return code %d (errno=%d).\n", buffer, ret, errno); + logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno); return; } did_run = true; @@ -2205,7 +2384,8 @@ struct AbcPass : public Pass { AbcModuleState state(config, initvals); state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str); - state.run_abc.run(); + ConcurrentStack process_pool; + state.run_abc.run(process_pool); state.extract(assign_map, design, mod); continue; } @@ -2379,11 +2559,12 @@ struct AbcPass : public Pass { ConcurrentQueue> work_queue(num_worker_threads); ConcurrentQueue> work_finished_queue; int work_finished_count = 0; + ConcurrentStack process_pool; ThreadPool worker_threads(num_worker_threads, [&](int){ while (std::optional> work = work_queue.pop_front()) { // Only the `run_abc` component is safe to touch here! - (*work)->run_abc.run(); + (*work)->run_abc.run(process_pool); work_finished_queue.push_back(std::move(*work)); } }); @@ -2409,7 +2590,7 @@ struct AbcPass : public Pass { work_queue.push_back(std::move(state)); } else { // Just run everything on the main thread. - state->run_abc.run(); + state->run_abc.run(process_pool); work_finished_queue.push_back(std::move(state)); } } From 9cb3a239cc872e4a4379d00a0191a2760122542e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 15 Sep 2025 23:13:20 +0000 Subject: [PATCH 073/188] Fix `subcircuit` building without `#define _YOSYS_` We can't use the new stringf functionality with `my_sprintf()` since in some builds that falls back to C-style varargs. --- libs/subcircuit/subcircuit.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/subcircuit/subcircuit.cc b/libs/subcircuit/subcircuit.cc index 8c8d3d92d..60f27fd55 100644 --- a/libs/subcircuit/subcircuit.cc +++ b/libs/subcircuit/subcircuit.cc @@ -411,7 +411,7 @@ class SubCircuit::SolverWorker std::string toString() const { - return my_stringf("%s[%d]:%s[%d]", fromPort, fromBit, toPort, toBit); + return my_stringf("%s[%d]:%s[%d]", fromPort.c_str(), fromBit, toPort.c_str(), toBit); } }; @@ -444,7 +444,7 @@ class SubCircuit::SolverWorker std::string str; bool firstPort = true; for (const auto &it : portSizes) { - str += my_stringf("%s%s[%d]", firstPort ? "" : ",", it.first, it.second); + str += my_stringf("%s%s[%d]", firstPort ? "" : ",", it.first.c_str(), it.second); firstPort = false; } return typeId + "(" + str + ")"; From fe9eed04981a74758a4ab567baa135cbd00bc28d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 16 Sep 2025 00:22:09 +0000 Subject: [PATCH 074/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4aae25c3c..281f5a868 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+72 +YOSYS_VER := 0.57+88 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 8492c49f6cf670c5df50f7a0cbf839b3d85ecae2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 03:06:17 +0000 Subject: [PATCH 075/188] Remove `string_buf` by making `log_signal()` and `log_const()` return `std::string` We only have to fix one caller in-tree so this probably has very low impact on out-of-tree plugins. Resolves #5215 --- kernel/log.cc | 33 ++++----------------------------- kernel/log.h | 4 ++-- passes/techmap/abc.cc | 2 +- 3 files changed, 7 insertions(+), 32 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index efdface80..3a44a3ddc 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -68,8 +68,6 @@ int log_debug_suppressed = 0; vector header_count; vector log_id_cache; -vector string_buf; -int string_buf_index = -1; static struct timeval initial_tv = { 0, 0 }; static bool next_print_log = false; @@ -447,8 +445,6 @@ void log_pop() { header_count.pop_back(); log_id_cache_clear(); - string_buf.clear(); - string_buf_index = -1; log_flush(); } @@ -554,8 +550,6 @@ void log_reset_stack() while (header_count.size() > 1) header_count.pop_back(); log_id_cache_clear(); - string_buf.clear(); - string_buf_index = -1; log_flush(); } @@ -580,38 +574,19 @@ void log_dump_val_worker(RTLIL::State v) { log("%s", log_signal(v)); } -const char *log_signal(const RTLIL::SigSpec &sig, bool autoint) +std::string log_signal(const RTLIL::SigSpec &sig, bool autoint) { std::stringstream buf; RTLIL_BACKEND::dump_sigspec(buf, sig, autoint); - - if (string_buf.size() < 100) { - string_buf.push_back(buf.str()); - return string_buf.back().c_str(); - } else { - if (++string_buf_index == 100) - string_buf_index = 0; - string_buf[string_buf_index] = buf.str(); - return string_buf[string_buf_index].c_str(); - } + return buf.str(); } -const char *log_const(const RTLIL::Const &value, bool autoint) +std::string log_const(const RTLIL::Const &value, bool autoint) { if ((value.flags & RTLIL::CONST_FLAG_STRING) == 0) return log_signal(value, autoint); - std::string str = "\"" + value.decode_string() + "\""; - - if (string_buf.size() < 100) { - string_buf.push_back(str); - return string_buf.back().c_str(); - } else { - if (++string_buf_index == 100) - string_buf_index = 0; - string_buf[string_buf_index] = str; - return string_buf[string_buf_index].c_str(); - } + return "\"" + value.decode_string() + "\""; } const char *log_id(const RTLIL::IdString &str) diff --git a/kernel/log.h b/kernel/log.h index a136ec7ac..78b202159 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -253,8 +253,8 @@ extern dict log_expect_log, log_expect_warning, lo extern dict log_expect_prefix_log, log_expect_prefix_warning, log_expect_prefix_error; void log_check_expected(); -const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); -const char *log_const(const RTLIL::Const &value, bool autoint = true); +std::string log_signal(const RTLIL::SigSpec &sig, bool autoint = true); +std::string log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(const RTLIL::IdString &id); template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 82a5124ae..c5bdd6ecf 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -755,7 +755,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module) log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)), run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str); else - log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "", + log(" %*s %s -> %s\n", int(log_signal(RTLIL::SigSpec(wire)).size()), "", run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str); first_line = false; } From 03127173c66b421df9eda632f5d2bc34e515a96c Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:33:14 +0000 Subject: [PATCH 076/188] Fix const_iterator postincrement behavior --- kernel/rtlil.h | 4 ++-- tests/unit/kernel/rtlilTest.cc | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fc0087442..0ec7e0954 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -904,8 +904,8 @@ public: const_iterator& operator++() { ++idx; return *this; } const_iterator& operator--() { --idx; return *this; } - const_iterator& operator++(int) { ++idx; return *this; } - const_iterator& operator--(int) { --idx; return *this; } + const_iterator operator++(int) { const_iterator result(*this); ++idx; return result; } + const_iterator operator--(int) { const_iterator result(*this); --idx; return result; } const_iterator& operator+=(int i) { idx += i; return *this; } const_iterator operator+(int add) { diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index cb773202d..b8ac554b1 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -90,6 +90,30 @@ namespace RTLIL { } + TEST_F(KernelRtlilTest, ConstConstIteratorWorks) { + const Const c(0x2, 2); + Const::const_iterator it = c.begin(); + ASSERT_NE(it, c.end()); + EXPECT_EQ(*it, State::S0); + ++it; + ASSERT_NE(it, c.end()); + EXPECT_EQ(*it, State::S1); + ++it; + EXPECT_EQ(it, c.end()); + } + + TEST_F(KernelRtlilTest, ConstConstIteratorPreincrement) { + const Const c(0x2, 2); + Const::const_iterator it = c.begin(); + EXPECT_EQ(*++it, State::S1); + } + + TEST_F(KernelRtlilTest, ConstConstIteratorPostincrement) { + const Const c(0x2, 2); + Const::const_iterator it = c.begin(); + EXPECT_EQ(*it++, State::S0); + } + class WireRtlVsHdlIndexConversionTest : public KernelRtlilTest, public testing::WithParamInterface> From 514fb8f9015b2895e61e025e8b57509942adef72 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:34:41 +0000 Subject: [PATCH 077/188] Fix Const::const_iterator tag to be bidirectional_iterator_tag --- kernel/rtlil.cc | 6 +++--- kernel/rtlil.h | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3a8b25d1d..8d7f89650 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,11 +615,11 @@ void RTLIL::Const::append(const RTLIL::Const &other) { } RTLIL::State RTLIL::Const::const_iterator::operator*() const { - if (auto bv = parent.get_if_bits()) + if (auto bv = parent->get_if_bits()) return (*bv)[idx]; - int char_idx = parent.get_str().size() - idx / 8 - 1; - bool bit = (parent.get_str()[char_idx] & (1 << (idx % 8))); + int char_idx = parent->get_str().size() - idx / 8 - 1; + bool bit = (parent->get_str()[char_idx] & (1 << (idx % 8))); return bit ? State::S1 : State::S0; } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0ec7e0954..e1002fff7 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -888,17 +888,17 @@ public: class const_iterator { private: - const Const& parent; + const Const* parent; size_t idx; public: - using iterator_category = std::input_iterator_tag; + using iterator_category = std::bidirectional_iterator_tag; using value_type = State; using difference_type = std::ptrdiff_t; using pointer = const State*; using reference = const State&; - const_iterator(const Const& c, size_t i) : parent(c), idx(i) {} + const_iterator(const Const& c, size_t i) : parent(&c), idx(i) {} State operator*() const; @@ -909,10 +909,10 @@ public: const_iterator& operator+=(int i) { idx += i; return *this; } const_iterator operator+(int add) { - return const_iterator(parent, idx + add); + return const_iterator(*parent, idx + add); } const_iterator operator-(int sub) { - return const_iterator(parent, idx - sub); + return const_iterator(*parent, idx - sub); } int operator-(const const_iterator& other) { return idx - other.idx; From 662a3df98713244cc35f0145a98f69f98c4fdb99 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:54:41 +0000 Subject: [PATCH 078/188] Update Const API with alternatives to direct use of bits() In particular, `Const::resize()`, `Const::set()`, and `Const::iterator`. --- kernel/rtlil.h | 81 ++++++++++++++++++++++++++++++++-- tests/unit/kernel/rtlilTest.cc | 54 +++++++++++++++++++++++ 2 files changed, 131 insertions(+), 4 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e1002fff7..b7776f378 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -842,13 +842,24 @@ public: Const(const std::string &str); Const(long long val, int width = 32); Const(RTLIL::State bit, int width = 1); - Const(const std::vector &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {} + Const(std::vector bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::move(bits)) {} Const(const std::vector &bits); Const(const RTLIL::Const &other); Const(RTLIL::Const &&other); RTLIL::Const &operator =(const RTLIL::Const &other); ~Const(); + struct Builder + { + Builder() {} + Builder(int expected_width) { bits.reserve(expected_width); } + void push_back(RTLIL::State b) { bits.push_back(b); } + int size() const { return static_cast(bits.size()); } + Const build() { return Const(std::move(bits)); } + private: + std::vector bits; + }; + bool operator <(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; @@ -885,6 +896,12 @@ public: void bitvectorize() const; void append(const RTLIL::Const &other); + void set(int i, RTLIL::State state) { + bits()[i] = state; + } + void resize(int size, RTLIL::State fill) { + bits().resize(size, fill); + } class const_iterator { private: @@ -927,12 +944,69 @@ public: } }; + class iterator { + private: + Const* parent; + size_t idx; + + public: + class proxy { + private: + Const* parent; + size_t idx; + public: + proxy(Const* parent, size_t idx) : parent(parent), idx(idx) {} + operator State() const { return (*parent)[idx]; } + proxy& operator=(State s) { parent->set(idx, s); return *this; } + proxy& operator=(const proxy& other) { parent->set(idx, (*other.parent)[other.idx]); return *this; } + }; + + using iterator_category = std::bidirectional_iterator_tag; + using value_type = State; + using difference_type = std::ptrdiff_t; + using pointer = proxy*; + using reference = proxy; + + iterator(Const& c, size_t i) : parent(&c), idx(i) {} + + proxy operator*() const { return proxy(parent, idx); } + iterator& operator++() { ++idx; return *this; } + iterator& operator--() { --idx; return *this; } + iterator operator++(int) { iterator result(*this); ++idx; return result; } + iterator operator--(int) { iterator result(*this); --idx; return result; } + iterator& operator+=(int i) { idx += i; return *this; } + + iterator operator+(int add) { + return iterator(*parent, idx + add); + } + iterator operator-(int sub) { + return iterator(*parent, idx - sub); + } + int operator-(const iterator& other) { + return idx - other.idx; + } + + bool operator==(const iterator& other) const { + return idx == other.idx; + } + + bool operator!=(const iterator& other) const { + return !(*this == other); + } + }; + const_iterator begin() const { return const_iterator(*this, 0); } const_iterator end() const { return const_iterator(*this, size()); } + iterator begin() { + return iterator(*this, 0); + } + iterator end() { + return iterator(*this, size()); + } State back() const { return *(end() - 1); } @@ -964,12 +1038,11 @@ public: std::optional as_int_compress(bool is_signed) const; void extu(int width) { - bits().resize(width, RTLIL::State::S0); + resize(width, RTLIL::State::S0); } void exts(int width) { - bitvectype& bv = bits(); - bv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back()); + resize(width, empty() ? RTLIL::State::Sx : back()); } [[nodiscard]] Hasher hash_into(Hasher h) const { diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index b8ac554b1..6a5f75a95 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -114,6 +114,60 @@ namespace RTLIL { EXPECT_EQ(*it++, State::S0); } + TEST_F(KernelRtlilTest, ConstIteratorWorks) { + Const c(0x2, 2); + Const::iterator it = c.begin(); + ASSERT_NE(it, c.end()); + EXPECT_EQ(*it, State::S0); + ++it; + ASSERT_NE(it, c.end()); + EXPECT_EQ(*it, State::S1); + ++it; + ASSERT_EQ(it, c.end()); + } + + TEST_F(KernelRtlilTest, ConstIteratorPreincrement) { + Const c(0x2, 2); + Const::iterator it = c.begin(); + EXPECT_EQ(*++it, State::S1); + } + + TEST_F(KernelRtlilTest, ConstIteratorPostincrement) { + Const c(0x2, 2); + Const::iterator it = c.begin(); + EXPECT_EQ(*it++, State::S0); + } + + TEST_F(KernelRtlilTest, ConstIteratorWriteWorks) { + Const c(0x2, 2); + Const::iterator it = c.begin(); + EXPECT_EQ(*it, State::S0); + *it = State::S1; + EXPECT_EQ(*it, State::S1); + } + + TEST_F(KernelRtlilTest, ConstBuilder) { + Const::Builder b; + EXPECT_EQ(GetSize(b), 0); + b.push_back(S0); + EXPECT_EQ(GetSize(b), 1); + b.push_back(S1); + EXPECT_EQ(GetSize(b), 2); + EXPECT_EQ(b.build(), Const(0x2, 2)); + } + + TEST_F(KernelRtlilTest, ConstSet) { + Const c(0x2, 2); + c.set(0, S1); + EXPECT_EQ(c, Const(0x3, 2)); + } + + TEST_F(KernelRtlilTest, ConstResize) { + Const c(0x2, 2); + c.resize(4, S1); + EXPECT_EQ(c, Const(0xe, 4)); + } + class WireRtlVsHdlIndexConversionTest : public KernelRtlilTest, public testing::WithParamInterface> From 34df6569a69f32ae96ed7b7353f484e9b0346bb2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:55:02 +0000 Subject: [PATCH 079/188] Update backends to avoid bits() --- backends/btor/btor.cc | 16 +++++++++------- backends/cxxrtl/cxxrtl_backend.cc | 15 +++++++++------ backends/functional/test_generic.cc | 2 +- backends/simplec/simplec.cc | 2 +- backends/smt2/smt2.cc | 12 ++++++------ backends/verilog/verilog_backend.cc | 12 +++++++----- 6 files changed, 33 insertions(+), 26 deletions(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 5fd21717e..bba7249c7 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -705,12 +705,13 @@ struct BtorWorker } } - Const initval; + Const::Builder initval_bits(GetSize(sig_q)); for (int i = 0; i < GetSize(sig_q); i++) if (initbits.count(sig_q[i])) - initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); + initval_bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0); else - initval.bits().push_back(State::Sx); + initval_bits.push_back(State::Sx); + Const initval = initval_bits.build(); int nid_init_val = -1; @@ -1039,10 +1040,11 @@ struct BtorWorker { if (bit.wire == nullptr) { - Const c(bit.data); - - while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr) - c.bits().push_back(sig[i+GetSize(c)].data); + Const::Builder c_bits; + c_bits.push_back(bit.data); + while (i + GetSize(c_bits) < GetSize(sig) && sig[i + GetSize(c_bits)].wire == nullptr) + c_bits.push_back(sig[i + GetSize(c_bits)].data); + Const c = c_bits.build(); if (consts.count(c) == 0) { int sid = get_bv_sid(GetSize(c)); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 0c9f6c054..9a7e1383a 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1668,26 +1668,29 @@ struct CxxrtlWorker { f << signal_temp << " == "; dump_sigspec(compare, /*is_lhs=*/false, for_debug); } else if (compare.is_fully_const()) { - RTLIL::Const compare_mask, compare_value; + RTLIL::Const::Builder compare_mask_builder(compare.size()); + RTLIL::Const::Builder compare_value_builder(compare.size()); for (auto bit : compare.as_const()) { switch (bit) { case RTLIL::S0: case RTLIL::S1: - compare_mask.bits().push_back(RTLIL::S1); - compare_value.bits().push_back(bit); + compare_mask_builder.push_back(RTLIL::S1); + compare_value_builder.push_back(bit); break; case RTLIL::Sx: case RTLIL::Sz: case RTLIL::Sa: - compare_mask.bits().push_back(RTLIL::S0); - compare_value.bits().push_back(RTLIL::S0); + compare_mask_builder.push_back(RTLIL::S0); + compare_value_builder.push_back(RTLIL::S0); break; default: log_assert(false); } } + RTLIL::Const compare_mask = compare_mask_builder.build(); + RTLIL::Const compare_value = compare_value_builder.build(); f << "and_uu<" << compare.size() << ">(" << signal_temp << ", "; dump_const(compare_mask); f << ") == "; @@ -3042,7 +3045,7 @@ struct CxxrtlWorker { if (init == RTLIL::Const()) { init = RTLIL::Const(State::Sx, GetSize(bit.wire)); } - init.bits()[bit.offset] = port.init_value[i]; + init.set(bit.offset, port.init_value[i]); } } } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index a0474ea2b..c01649a0f 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -105,7 +105,7 @@ struct MemContentsTest { RTLIL::Const values; for(addr_t addr = low; addr <= high; addr++) { RTLIL::Const word(data_dist(rnd), data_width); - values.bits().insert(values.bits().end(), word.begin(), word.end()); + values.append(word); } insert_concatenated(low, values); } diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index ed981f961..8ebc685f0 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -657,7 +657,7 @@ struct SimplecWorker { SigSpec sig = sigmaps.at(module)(w); Const val = w->attributes.at(ID::init); - val.bits().resize(GetSize(sig), State::Sx); + val.resize(GetSize(sig), State::Sx); for (int i = 0; i < GetSize(sig); i++) if (val[i] == State::S0 || val[i] == State::S1) { diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 1d3757463..d80622029 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1079,14 +1079,14 @@ struct Smt2Worker RTLIL::SigSpec sig = sigmap(wire); Const val = wire->attributes.at(ID::init); - val.bits().resize(GetSize(sig), State::Sx); + val.resize(GetSize(sig), State::Sx); if (bvmode && GetSize(sig) > 1) { Const mask(State::S1, GetSize(sig)); bool use_mask = false; for (int i = 0; i < GetSize(sig); i++) if (val[i] != State::S0 && val[i] != State::S1) { - val.bits()[i] = State::S0; - mask.bits()[i] = State::S0; + val.set(i, State::S0); + mask.set(i, State::S0); use_mask = true; } if (use_mask) @@ -1361,10 +1361,10 @@ struct Smt2Worker for (int k = 0; k < GetSize(initword); k++) { if (initword[k] == State::S0 || initword[k] == State::S1) { gen_init_constr = true; - initmask.bits()[k] = State::S1; + initmask.set(k, State::S1); } else { - initmask.bits()[k] = State::S0; - initword.bits()[k] = State::S0; + initmask.set(k, State::S0); + initword.set(k, State::S0); } } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 71969f177..b03639b8d 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -327,19 +327,20 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o void dump_reg_init(std::ostream &f, SigSpec sig) { - Const initval; bool gotinit = false; + Const::Builder initval_bits(sig.size()); for (auto bit : active_sigmap(sig)) { if (active_initdata.count(bit)) { - initval.bits().push_back(active_initdata.at(bit)); + initval_bits.push_back(active_initdata.at(bit)); gotinit = true; } else { - initval.bits().push_back(State::Sx); + initval_bits.push_back(State::Sx); } } if (gotinit) { + Const initval = initval_bits.build(); f << " = "; dump_const(f, initval); } @@ -767,9 +768,10 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) dump_sigspec(os, port.data.extract(sub * mem.width, mem.width)); os << stringf(" = %s[", mem_id);; if (port.wide_log2) { - Const addr_lo; + Const::Builder addr_lo_builder(port.wide_log2); for (int i = 0; i < port.wide_log2; i++) - addr_lo.bits().push_back(State(sub >> i & 1)); + addr_lo_builder.push_back(State(sub >> i & 1)); + Const addr_lo = addr_lo_builder.build(); os << "{"; os << temp_id; os << ", "; From f65ca488ec41500857f041768a200652a5e90189 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:55:26 +0000 Subject: [PATCH 080/188] Update frontends to avoid bits() --- frontends/aiger/aigerparse.cc | 2 +- frontends/ast/ast.cc | 4 +++- frontends/ast/genrtlil.cc | 16 +++++++++------- frontends/ast/simplify.cc | 11 +++++++---- frontends/blif/blifparse.cc | 23 +++++++++++++---------- frontends/rtlil/rtlil_parser.y | 7 ++++--- 6 files changed, 37 insertions(+), 26 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index db4cb12ba..70d94faff 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -448,7 +448,7 @@ void AigerReader::parse_xaiger() bool success = ce.eval(o); log_assert(success); log_assert(o.wire == nullptr); - lut_mask.bits()[gray] = o.data; + lut_mask.set(gray, o.data); } RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)); log_assert(output_cell); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index b61c0bea9..459b50683 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1076,8 +1076,10 @@ RTLIL::Const AstNode::realAsConst(int width) bool is_negative = v < 0; if (is_negative) v *= -1; + RTLIL::Const::Builder b(width); for (int i = 0; i < width; i++, v /= 2) - result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); + b.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); + result = b.build(); if (is_negative) result = const_neg(result, result, false, false, result.size()); } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 41e10cf98..262dda43b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -732,16 +732,17 @@ struct AST_INTERNAL::ProcessGenerator current_case->actions.push_back(SigSig(en, true)); RTLIL::SigSpec triggers; - RTLIL::Const polarity; + RTLIL::Const::Builder polarity_builder; for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits().push_back(RTLIL::S1); + polarity_builder.push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits().push_back(RTLIL::S0); + polarity_builder.push_back(RTLIL::S0); } } + RTLIL::Const polarity = polarity_builder.build(); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print)); set_src_attr(cell, ast); @@ -829,16 +830,17 @@ struct AST_INTERNAL::ProcessGenerator current_case->actions.push_back(SigSig(en, true)); RTLIL::SigSpec triggers; - RTLIL::Const polarity; + RTLIL::Const::Builder polarity_builder; for (auto sync : proc->syncs) { if (sync->type == RTLIL::STp) { triggers.append(sync->signal); - polarity.bits().push_back(RTLIL::S1); + polarity_builder.push_back(RTLIL::S1); } else if (sync->type == RTLIL::STn) { triggers.append(sync->signal); - polarity.bits().push_back(RTLIL::S0); + polarity_builder.push_back(RTLIL::S0); } } + RTLIL::Const polarity = polarity_builder.build(); RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); set_src_attr(cell, ast); @@ -893,7 +895,7 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx); for (int i = 0; i < portid; i++) { int new_bit = port_map[std::make_pair(memid, i)]; - priority_mask.bits()[new_bit] = orig_priority_mask[i]; + priority_mask.set(new_bit, orig_priority_mask[i]); } action.priority_mask = priority_mask; sync->mem_write_actions.push_back(action); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 7328290ea..2669f83e2 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -4366,7 +4366,7 @@ replace_fcall_later:; log_assert(a.size() == b.size()); for (auto i = 0; i < a.size(); i++) if (a[i] != b[i]) - a.bits()[i] = RTLIL::State::Sx; + a.set(i, RTLIL::State::Sx); newNode = mkconst_bits(location, a.to_bits(), sign_hint); } else if (children[1]->isConst() && children[2]->isConst()) { newNode = std::make_unique(location, AST_REALVALUE); @@ -5368,8 +5368,11 @@ bool AstNode::replace_variables(std::map &varia offset -= variables.at(str).offset; if (variables.at(str).range_swapped) offset = -offset; - std::vector &var_bits = variables.at(str).val.bits(); - std::vector new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width); + const RTLIL::Const &val = variables.at(str).val; + std::vector new_bits; + new_bits.reserve(width); + for (int i = 0; i < width; i++) + new_bits.push_back(val[offset+i]); auto newNode = mkconst_bits(location, new_bits, variables.at(str).is_signed); newNode->cloneInto(*this); return true; @@ -5513,7 +5516,7 @@ std::unique_ptr AstNode::eval_const_function(AstNode *fcall, bool must_ int index = i + offset - v.offset; if (v.range_swapped) index = -index; - v.val.bits().at(index) = r.at(i); + v.val.set(index, r.at(i)); } } diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index d63044923..741dd07d6 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (buffer[0] == '.') { if (lutptr) { - for (auto &bit : lutptr->bits()) + for (auto bit : *lutptr) if (bit == RTLIL::State::Sx) bit = lut_default_state; lutptr = NULL; @@ -321,9 +321,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool const_v = Const(str); } else { int n = strlen(v); - const_v.bits().resize(n); + Const::Builder const_v_builder(n); for (int i = 0; i < n; i++) - const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0; + const_v_builder.push_back(v[n-i-1] != '0' ? State::S1 : State::S0); + const_v = const_v_builder.build(); } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { @@ -563,21 +564,23 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len); sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1; + Const::Builder table_bits_builder(input_len * 2); for (int i = 0; i < input_len; i++) switch (input[i]) { case '0': - sopcell->parameters[ID::TABLE].bits().push_back(State::S1); - sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + table_bits_builder.push_back(State::S1); + table_bits_builder.push_back(State::S0); break; case '1': - sopcell->parameters[ID::TABLE].bits().push_back(State::S0); - sopcell->parameters[ID::TABLE].bits().push_back(State::S1); + table_bits_builder.push_back(State::S0); + table_bits_builder.push_back(State::S1); break; default: - sopcell->parameters[ID::TABLE].bits().push_back(State::S0); - sopcell->parameters[ID::TABLE].bits().push_back(State::S0); + table_bits_builder.push_back(State::S0); + table_bits_builder.push_back(State::S0); break; } + sopcell->parameters[ID::TABLE].append(table_bits_builder.build()); if (sopmode == -1) { sopmode = (*output == '1'); @@ -605,7 +608,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto try_next_value; } } - lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; + lutptr->set(i, !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1); try_next_value:; } diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y index fc7615364..4f0fb3b97 100644 --- a/frontends/rtlil/rtlil_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -455,9 +455,10 @@ constant: } while ((int)bits.size() > width) bits.pop_back(); - $$ = new RTLIL::Const; - for (auto it = bits.begin(); it != bits.end(); it++) - $$->bits().push_back(*it); + RTLIL::Const::Builder builder(bits.size()); + for (RTLIL::State bit : bits) + builder.push_back(bit); + $$ = new RTLIL::Const(builder.build()); if (is_signed) { $$->flags |= RTLIL::CONST_FLAG_SIGNED; } From 1b589b065d889cf53e30e53bd58ee5acde68a595 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:52:40 +0000 Subject: [PATCH 081/188] Update passes/cmds to avoid bits() --- passes/cmds/bugpoint.cc | 6 +++++- passes/cmds/clean_zerowidth.cc | 6 +++--- passes/cmds/dft_tag.cc | 6 ++++-- passes/cmds/setundef.cc | 8 ++++---- passes/cmds/splitnets.cc | 7 ++++--- passes/cmds/xprop.cc | 12 ++++++------ 6 files changed, 26 insertions(+), 19 deletions(-) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index d48e25d68..8432c27fd 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -405,7 +405,11 @@ struct BugpointPass : public Pass { for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) { auto &mask = it2->priority_mask; if (GetSize(mask) > i) { - mask.bits().erase(mask.bits().begin() + i); + RTLIL::Const::Builder new_mask_builder(GetSize(mask) - 1); + for (int k = 0; k < GetSize(mask); k++) + if (k != i) + new_mask_builder.push_back(mask[k]); + mask = new_mask_builder.build(); } } return design_copy; diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index 48a8864c0..021726450 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -158,11 +158,11 @@ struct CleanZeroWidthPass : public Pass { continue; if (GetSize(memwr.address) == 0) memwr.address = State::S0; - Const priority_mask; + RTLIL::Const::Builder new_mask_bits(swizzle.size()); for (auto x : swizzle) { - priority_mask.bits().push_back(memwr.priority_mask[x]); + new_mask_bits.push_back(memwr.priority_mask[x]); } - memwr.priority_mask = priority_mask; + memwr.priority_mask = new_mask_bits.build(); swizzle.push_back(i); new_memwr_actions.push_back(memwr); } diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 068b5d7d9..5d9756ca0 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -884,8 +884,10 @@ struct DftTagWorker { { if (sig_a.is_fully_const()) { auto const_val = sig_a.as_const(); - for (State& bit : const_val.bits()) - bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit; + for (auto bit : const_val) { + State b = bit; + bit = b == State::S0 ? State::S1 : b == State::S1 ? State::S0 : b; + } return const_val; } return module->Not(name, sig_a); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c4a555e6a..6d3e30561 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -243,7 +243,7 @@ struct SetundefPass : public Pass { { for (auto *cell : module->selected_cells()) { for (auto ¶meter : cell->parameters) { - for (auto &bit : parameter.second.bits()) { + for (auto bit : parameter.second) { if (bit > RTLIL::State::S1) bit = worker.next_bit(); } @@ -390,12 +390,12 @@ struct SetundefPass : public Pass { for (auto wire : initwires) { Const &initval = wire->attributes[ID::init]; - initval.bits().resize(GetSize(wire), State::Sx); + initval.resize(GetSize(wire), State::Sx); for (int i = 0; i < GetSize(wire); i++) { SigBit bit = sigmap(SigBit(wire, i)); if (initval[i] == State::Sx && ffbits.count(bit)) { - initval.bits()[i] = worker.next_bit(); + initval.set(i, worker.next_bit()); ffbits.erase(bit); } } @@ -421,7 +421,7 @@ struct SetundefPass : public Pass { continue; Const &initval = wire->attributes[ID::init]; - initval.bits().resize(GetSize(wire), State::Sx); + initval.resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) { wire->attributes.erase(ID::init); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 9e606dee1..d61a99ec0 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -75,10 +75,11 @@ struct SplitnetsWorker it = wire->attributes.find(ID::init); if (it != wire->attributes.end()) { - Const old_init = it->second, new_init; + Const old_init = it->second; + RTLIL::Const::Builder new_init_bits_builder(width); for (int i = offset; i < offset+width; i++) - new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx); - new_wire->attributes.emplace(ID::init, new_init); + new_init_bits_builder.push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx); + new_wire->attributes.emplace(ID::init, new_init_bits_builder.build()); } std::vector sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 186e5eec0..8b2e7ae08 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -828,9 +828,9 @@ struct XpropWorker auto init_q_is_1 = init_q; auto init_q_is_x = init_q; - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = bit == State::S1 ? State::S1 : State::S0; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = bit == State::Sx ? State::S1 : State::S0; initvals.remove_init(sig_q); @@ -865,14 +865,14 @@ struct XpropWorker auto init_q_is_x = init_q; if (ff.is_anyinit) { - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = State::Sx; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = State::S0; } else { - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = bit == State::S1 ? State::S1 : State::S0; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = bit == State::Sx ? State::S1 : State::S0; } From e1d0c010efffe98d127cf742791f955b95de7b21 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:05 +0000 Subject: [PATCH 082/188] Update passes/fsm to avoid bits() --- passes/fsm/fsm_extract.cc | 2 +- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_opt.cc | 21 ++++++++++------- passes/fsm/fsm_recode.cc | 2 +- passes/fsm/fsmdata.h | 49 ++++++++++++++------------------------- 5 files changed, 32 insertions(+), 44 deletions(-) diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index d83cff5cdc..43a797ff4 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -171,7 +171,7 @@ undef_bit_in_next_state: if (tr.ctrl_in.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0) for (auto &dc_bit : exclusive_ctrls.at(it.first)) if (ctrl_in_bit_indices.count(dc_bit)) - tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa; + tr.ctrl_in.set(ctrl_in_bit_indices.at(dc_bit), RTLIL::State::Sa); RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits); if (state_in >= 0) diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 8a18d259a..c19edcc88 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) state_dff->type = ID($adff); state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY]; state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state]; - for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits()) + for (auto bit : state_dff->parameters[ID::ARST_VALUE]) if (bit != RTLIL::State::S1) bit = RTLIL::State::S0; state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST)); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 99771f90a..b61dec890 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -169,13 +169,16 @@ struct FsmOpt for (auto tr : fsm_data.transition_table) { - RTLIL::State &si = tr.ctrl_in.bits()[i]; - RTLIL::State &sj = tr.ctrl_in.bits()[j]; + RTLIL::State si = tr.ctrl_in[i]; + RTLIL::State sj = tr.ctrl_in[j]; - if (si > RTLIL::State::S1) + if (si > RTLIL::State::S1) { si = sj; - else if (sj > RTLIL::State::S1) + tr.ctrl_in.set(i, si); + } else if (sj > RTLIL::State::S1) { sj = si; + tr.ctrl_in.set(j, sj); + } if (si == sj) { RTLIL::SigSpec tmp(tr.ctrl_in); @@ -207,8 +210,8 @@ struct FsmOpt for (auto tr : fsm_data.transition_table) { - RTLIL::State &si = tr.ctrl_in.bits()[i]; - RTLIL::State &sj = tr.ctrl_out.bits()[j]; + RTLIL::State si = tr.ctrl_in[i]; + RTLIL::State sj = tr.ctrl_out[j]; if (si > RTLIL::State::S1 || si == sj) { RTLIL::SigSpec tmp(tr.ctrl_in); @@ -240,14 +243,14 @@ struct FsmOpt RTLIL::Const other_pattern = pattern; if (pattern[bit] == RTLIL::State::S1) - other_pattern.bits()[bit] = RTLIL::State::S0; + other_pattern.set(bit, RTLIL::State::S0); else - other_pattern.bits()[bit] = RTLIL::State::S1; + other_pattern.set(bit, RTLIL::State::S1); if (set.count(other_pattern) > 0) { log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern), tr.state_in, tr.state_out, log_signal(tr.ctrl_out)); - other_pattern.bits()[bit] = RTLIL::State::Sa; + other_pattern.set(bit, RTLIL::State::Sa); new_set.insert(other_pattern); did_something = true; continue; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 8ee03329f..e4cd53a07 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -106,7 +106,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs if (encoding == "one-hot") { new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits); - new_code.bits()[state_idx] = RTLIL::State::S1; + new_code.set(state_idx, RTLIL::State::S1); } else if (encoding == "binary") { new_code = RTLIL::Const(state_idx, fsm_data.state_bits); diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 9aa12241e..4d824e136 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -45,35 +45,27 @@ struct FsmData cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size()); cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2); cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state); - cell->parameters[ID::STATE_TABLE] = RTLIL::Const(); - - for (int i = 0; i < int(state_table.size()); i++) { - std::vector &bits_table = cell->parameters[ID::STATE_TABLE].bits(); - std::vector &bits_state = state_table[i].bits(); - bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end()); - } + RTLIL::Const cell_state_table; + for (const RTLIL::Const &c : state_table) + cell_state_table.append(c); + cell->parameters[ID::STATE_TABLE] = std::move(cell_state_table); cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size()); - cell->parameters[ID::TRANS_TABLE] = RTLIL::Const(); + RTLIL::Const cell_trans_table; for (int i = 0; i < int(transition_table.size()); i++) { - std::vector &bits_table = cell->parameters[ID::TRANS_TABLE].bits(); transition_t &tr = transition_table[i]; RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2); RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2); - std::vector &bits_state_in = const_state_in.bits(); - std::vector &bits_state_out = const_state_out.bits(); - - std::vector &bits_ctrl_in = tr.ctrl_in.bits(); - std::vector &bits_ctrl_out = tr.ctrl_out.bits(); // append lsb first - bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end()); - bits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end()); - bits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end()); - bits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end()); + cell_trans_table.append(tr.ctrl_out); + cell_trans_table.append(const_state_out); + cell_trans_table.append(tr.ctrl_in); + cell_trans_table.append(const_state_in); } + cell->parameters[ID::TRANS_TABLE] = std::move(cell_trans_table); } void copy_from_cell(RTLIL::Cell *cell) @@ -95,25 +87,18 @@ struct FsmData const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE]; for (int i = 0; i < state_num; i++) { - RTLIL::Const state_code; - int off_begin = i*state_bits, off_end = off_begin + state_bits; - state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end); + int off_begin = i*state_bits; + RTLIL::Const state_code = state_table.extract(off_begin, state_bits); this->state_table.push_back(state_code); } for (int i = 0; i < trans_num; i++) { - auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2); - auto off_state_out = off_ctrl_out + num_outputs; - auto off_ctrl_in = off_state_out + state_num_log2; - auto off_state_in = off_ctrl_in + num_inputs; - auto off_end = off_state_in + state_num_log2; - - RTLIL::Const state_in, state_out, ctrl_in, ctrl_out; - ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out); - state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in); - ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in); - state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end); + int base_offset = i*(num_inputs+num_outputs+2*state_num_log2); + RTLIL::Const ctrl_out = trans_table.extract(base_offset, num_outputs); + RTLIL::Const state_out = trans_table.extract(base_offset + num_outputs, state_num_log2); + RTLIL::Const ctrl_in = trans_table.extract(base_offset + num_outputs + state_num_log2, num_inputs); + RTLIL::Const state_in = trans_table.extract(base_offset + num_outputs + state_num_log2 + num_inputs, state_num_log2); transition_t tr; tr.state_in = state_in.as_int(); From 23f196a3b894c28927c244ac0c2160830ab1f1e5 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:14 +0000 Subject: [PATCH 083/188] Update passes/memory to avoid bits() --- passes/memory/memory_bram.cc | 10 +++++----- passes/memory/memory_share.cc | 7 ++++--- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 8ef2c4271..10301b44a 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -848,9 +848,9 @@ grow_read_ports:; for (int i = 0; i < mem.width; i++) if (shuffle_map[i] != -1) { module->connect(port.data[shuffle_map[i]], new_data[i]); - new_init_value.bits()[i] = port.init_value[shuffle_map[i]]; - new_arst_value.bits()[i] = port.arst_value[shuffle_map[i]]; - new_srst_value.bits()[i] = port.srst_value[shuffle_map[i]]; + new_init_value.set(i, port.init_value[shuffle_map[i]]); + new_arst_value.set(i, port.arst_value[shuffle_map[i]]); + new_srst_value.set(i, port.srst_value[shuffle_map[i]]); } port.data = new_data; port.init_value = new_init_value; @@ -887,9 +887,9 @@ grow_read_ports:; for (int i = 0; i < init_size; i++) for (int j = 0; j < bram.dbits; j++) if (init_offset+i < GetSize(initdata) && init_offset+i >= 0) - initparam.bits()[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j]; + initparam.set(i*bram.dbits+j, initdata[init_offset+i][init_shift+j]); else - initparam.bits()[i*bram.dbits+j] = State::Sx; + initparam.set(i*bram.dbits+j, State::Sx); c->setParam(ID::INIT, initparam); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 6a424952a..fe884772a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -60,16 +60,17 @@ struct MemoryShareWorker bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) { res = Const(State::Sx, mem.width << wide_log2); for (int i = 0; i < GetSize(src1); i++) - res.bits()[i + sub1 * mem.width] = src1[i]; + res.set(i + sub1 * mem.width, src1[i]); for (int i = 0; i < GetSize(src2); i++) { if (src2[i] == State::Sx) continue; - auto &dst = res.bits()[i + sub2 * mem.width]; + int idx = i + sub2 * mem.width; + RTLIL::State dst = res[idx]; if (dst == src2[i]) continue; if (dst != State::Sx) return false; - dst = src2[i]; + res.set(idx, src2[i]); } return true; } From 5600eb2e5b2640c7966230c7e6cc0e7be454d1b3 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:23 +0000 Subject: [PATCH 084/188] Update passes/opt to avoid bits() --- passes/opt/opt_clean.cc | 6 +++--- passes/opt/opt_dff.cc | 22 +++++++++++++--------- passes/opt/opt_expr.cc | 4 ++-- passes/opt/opt_ffinv.cc | 15 ++++++++------- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_lut_ins.cc | 2 +- passes/opt/opt_mem.cc | 30 +++++++++++++++--------------- passes/opt/pmux2shiftx.cc | 16 +++++++++------- passes/opt/share.cc | 26 +++++++++++++++++--------- passes/opt/wreduce.cc | 4 ++-- 10 files changed, 71 insertions(+), 56 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4dd5ba616..cef2c0dc3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos for (int i = 0; i < wire->width; i++) { auto it = init_bits.find(RTLIL::SigBit(wire, i)); if (it != init_bits.end()) { - val.bits()[i] = it->second; + val.set(i, it->second); found = true; } } @@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (wire->attributes.count(ID::init)) initval = wire->attributes.at(ID::init); if (GetSize(initval) != GetSize(wire)) - initval.bits().resize(GetSize(wire), State::Sx); + initval.resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) wire->attributes.erase(ID::init); @@ -457,7 +457,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (s1[i] != s2[i]) { if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) { s2[i] = initval[i]; - initval.bits()[i] = State::Sx; + initval.set(i, State::Sx); } new_conn.first.append(s1[i]); new_conn.second.append(s2[i]); diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 2fb0f947f..a364539e4 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -405,27 +405,29 @@ struct OptDffWorker } else if (ff.pol_clr == ff.pol_set) { // Try a more complex conversion to plain async reset. State val_neutral = ff.pol_set ? State::S0 : State::S1; - Const val_arst; SigBit sig_arst; if (ff.sig_clr[0] == val_neutral) sig_arst = ff.sig_set[0]; else sig_arst = ff.sig_clr[0]; bool failed = false; + Const::Builder val_arst_builder(ff.width); for (int i = 0; i < ff.width; i++) { if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral) - val_arst.bits().push_back(State::S0); + val_arst_builder.push_back(State::S0); else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral) - val_arst.bits().push_back(State::S1); - else + val_arst_builder.push_back(State::S1); + else { failed = true; + break; + } } if (!failed) { log("Converting CLR/SET to ARST on %s (%s) from module %s.\n", log_id(cell), log_id(cell->type), log_id(module)); ff.has_sr = false; ff.has_arst = true; - ff.val_arst = val_arst; + ff.val_arst = val_arst_builder.build(); ff.sig_arst = sig_arst; ff.pol_arst = ff.pol_clr; changed = true; @@ -637,7 +639,7 @@ struct OptDffWorker // Try to merge sync resets. std::map> groups; std::vector remaining_indices; - Const val_srst; + Const::Builder val_srst_builder(ff.width); for (int i = 0 ; i < ff.width; i++) { ctrls_t resets; @@ -679,16 +681,18 @@ struct OptDffWorker groups[resets].push_back(i); } else remaining_indices.push_back(i); - val_srst.bits().push_back(reset_val); + val_srst_builder.push_back(reset_val); } + Const val_srst = val_srst_builder.build(); for (auto &it : groups) { FfData new_ff = ff.slice(it.second); - new_ff.val_srst = Const(); + Const::Builder new_val_srst_builder(new_ff.width); for (int i = 0; i < new_ff.width; i++) { int j = it.second[i]; - new_ff.val_srst.bits().push_back(val_srst[j]); + new_val_srst_builder.push_back(val_srst[j]); } + new_ff.val_srst = new_val_srst_builder.build(); ctrl_t srst = combine_resets(it.first, ff.is_fine); new_ff.has_srst = true; diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index e5957df08..86d96ea7a 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -83,7 +83,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) auto cursor = initbits.find(bit); if (cursor != initbits.end()) { revisit_initwires.insert(cursor->second.first); - val.bits()[i] = cursor->second.second; + val.set(i, cursor->second.second); } } @@ -101,7 +101,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct) Const initval = wire->attributes.at(ID::init); for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) { if (SigBit(initval[i]) == sig[i]) - initval.bits()[i] = State::Sx; + initval.set(i, State::Sx); } if (initval.is_fully_undef()) { log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 52e180a20..882221e56 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -96,10 +96,10 @@ struct OptFfInvWorker } } Const mask = lut->getParam(ID::LUT); - Const new_mask; - for (int j = 0; j < (1 << GetSize(sig_a)); j++) { - new_mask.bits().push_back(mask[j ^ flip_mask]); - } + Const::Builder new_mask_builder(1 << GetSize(sig_a)); + for (int j = 0; j < (1 << GetSize(sig_a)); j++) + new_mask_builder.push_back(mask[j ^ flip_mask]); + Const new_mask = new_mask_builder.build(); if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) { module->connect(lut->getPort(ID::Y), ff.sig_q); module->remove(lut); @@ -178,13 +178,14 @@ struct OptFfInvWorker if (d_lut->type == ID($lut)) { Const mask = d_lut->getParam(ID::LUT); - Const new_mask; + Const::Builder new_mask_builder(GetSize(mask)); for (int i = 0; i < GetSize(mask); i++) { if (mask[i] == State::S0) - new_mask.bits().push_back(State::S1); + new_mask_builder.push_back(State::S1); else - new_mask.bits().push_back(State::S0); + new_mask_builder.push_back(State::S0); } + Const new_mask = new_mask_builder.build(); d_lut->setParam(ID::LUT, new_mask); if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) { module->connect(ff.sig_d, d_lut->getPort(ID::A)); diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 97147fc48..248c3dfe9 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -493,7 +493,7 @@ struct OptLutWorker eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1; } eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs); - lutM_new_table.bits()[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs); + lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs)); } log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str()); diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 492676ece..9e471c3de 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -213,7 +213,7 @@ struct OptLutInsPass : public Pass { } lidx |= val << j; } - new_lut.bits()[i] = lut[lidx]; + new_lut.set(i, lut[lidx]); } // For lattice, and gowin do not replace with a const driver — the nextpnr // packer requires a complete set of LUTs for wide LUT muxes. diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index f8354c960..9c5a6d83e 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -175,36 +175,36 @@ struct OptMemPass : public Pass { } for (auto &port: mem.rd_ports) { SigSpec new_data; - Const new_init; - Const new_arst; - Const new_srst; + Const::Builder new_init_bits; + Const::Builder new_arst_bits; + Const::Builder new_srst_bits; for (int sub = 0; sub < (1 << port.wide_log2); sub++) { for (auto i: swizzle) { int bidx = sub * mem.width + i; new_data.append(port.data[bidx]); - new_init.bits().push_back(port.init_value[bidx]); - new_arst.bits().push_back(port.arst_value[bidx]); - new_srst.bits().push_back(port.srst_value[bidx]); + new_init_bits.push_back(port.init_value[bidx]); + new_arst_bits.push_back(port.arst_value[bidx]); + new_srst_bits.push_back(port.srst_value[bidx]); } } port.data = new_data; - port.init_value = new_init; - port.arst_value = new_arst; - port.srst_value = new_srst; + port.init_value = new_init_bits.build(); + port.arst_value = new_arst_bits.build(); + port.srst_value = new_srst_bits.build(); } for (auto &init: mem.inits) { - Const new_data; - Const new_en; + Const::Builder new_data_bits; for (int s = 0; s < GetSize(init.data); s += mem.width) { for (auto i: swizzle) { - new_data.bits().push_back(init.data[s + i]); + new_data_bits.push_back(init.data[s + i]); } } + init.data = new_data_bits.build(); + Const::Builder new_en_bits; for (auto i: swizzle) { - new_en.bits().push_back(init.en[i]); + new_en_bits.push_back(init.en[i]); } - init.data = new_data; - init.en = new_en; + init.en = new_en_bits.build(); } mem.width = GetSize(swizzle); changed = true; diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index e512a5be1..4a0864df0 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -321,11 +321,12 @@ struct Pmux2ShiftxPass : public Pass { bits.sort(); pair entry; - + RTLIL::Const::Builder entry_bits_builder(GetSize(bits)); for (auto it : bits) { entry.first.append(it.first); - entry.second.bits().push_back(it.second); + entry_bits_builder.push_back(it.second); } + entry.second = entry_bits_builder.build(); eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; goto next_cell; @@ -342,11 +343,12 @@ struct Pmux2ShiftxPass : public Pass { bits.sort(); pair entry; - + RTLIL::Const::Builder entry_bits_builder(GetSize(bits)); for (auto it : bits) { entry.first.append(it.first); - entry.second.bits().push_back(it.second); + entry_bits_builder.push_back(it.second); } + entry.second = entry_bits_builder.build(); eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry; goto next_cell; @@ -591,7 +593,7 @@ struct Pmux2ShiftxPass : public Pass { used_src_columns[best_src_col] = true; perm_new_from_old[dst_col] = best_src_col; - perm_xormask.bits()[dst_col] = best_inv ? State::S1 : State::S0; + perm_xormask.set(dst_col, best_inv ? State::S1 : State::S0); } } @@ -614,7 +616,7 @@ struct Pmux2ShiftxPass : public Pass { Const new_c(State::S0, GetSize(old_c)); for (int i = 0; i < GetSize(old_c); i++) - new_c.bits()[i] = old_c[perm_new_from_old[i]]; + new_c.set(i, old_c[perm_new_from_old[i]]); Const new_c_before_xor = new_c; new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c)); @@ -687,7 +689,7 @@ struct Pmux2ShiftxPass : public Pass { if (!full_case) { Const enable_mask(State::S0, max_choice+1); for (auto &it : perm_choices) - enable_mask.bits()[it.first.as_int()] = State::S1; + enable_mask.set(it.first.as_int(), State::S1); en = module->addWire(NEW_ID); module->addShift(NEW_ID, enable_mask, cmp, en, false, src); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 1d7ba7d98..307cd299b 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -790,12 +790,13 @@ struct ShareWorker } p.first = RTLIL::SigSpec(); - p.second.bits().clear(); + RTLIL::Const::Builder new_bits(p_bits.size()); for (auto &it : p_bits) { p.first.append(it.first); - p.second.bits().push_back(it.second); + new_bits.push_back(it.second); } + p.second = new_bits.build(); return true; } @@ -818,9 +819,9 @@ struct ShareWorker auto otherval = val; if (otherval[i] == State::S0) - otherval.bits()[i] = State::S1; + otherval.set(i, State::S1); else if (otherval[i] == State::S1) - otherval.bits()[i] = State::S0; + otherval.set(i, State::S0); else continue; @@ -829,8 +830,11 @@ struct ShareWorker auto newsig = sig; newsig.remove(i); - auto newval = val; - newval.bits().erase(newval.bits().begin() + i); + RTLIL::Const::Builder new_bits(val.size() - 1); + for (int j = 0; j < val.size(); ++j) + if (j != i) + new_bits.push_back(val[j]); + RTLIL::Const newval = new_bits.build(); db[newsig].insert(newval); db[sig].erase(otherval); @@ -926,7 +930,8 @@ struct ShareWorker if (used_in_a) for (auto p : c_patterns) { for (int i = 0; i < GetSize(sig_s); i++) - p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0); + p.first.append(sig_s[i]); + p.second.append(RTLIL::Const(RTLIL::State::S0, GetSize(sig_s))); if (sort_check_activation_pattern(p)) if (!insert_capped(activation_patterns_cache[cell], p)) { recursion_state.erase(cell); @@ -936,7 +941,8 @@ struct ShareWorker for (int idx : used_in_b_parts) for (auto p : c_patterns) { - p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1); + p.first.append(sig_s[idx]); + p.second.append(RTLIL::Const(RTLIL::State::S1)); if (sort_check_activation_pattern(p)) if (!insert_capped(activation_patterns_cache[cell], p)) { recursion_state.erase(cell); @@ -989,12 +995,14 @@ struct ShareWorker { std::vector p_first = p.first; ssc_pair_t new_p; + RTLIL::Const::Builder new_p_second_bits; for (int i = 0; i < GetSize(p_first); i++) if (filter_bits.count(p_first[i]) == 0) { new_p.first.append(p_first[i]); - new_p.second.bits().push_back(p.second.at(i)); + new_p_second_bits.push_back(p.second.at(i)); } + new_p.second = new_p_second_bits.build(); out.insert(new_p); } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index fb30f0195..359c76d42 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -220,10 +220,10 @@ struct WreduceWorker // Narrow ARST_VALUE parameter to new size. if (cell->parameters.count(ID::ARST_VALUE)) { - rst_value.bits().resize(GetSize(sig_q)); + rst_value.resize(GetSize(sig_q), State::S0); cell->setParam(ID::ARST_VALUE, rst_value); } else if (cell->parameters.count(ID::SRST_VALUE)) { - rst_value.bits().resize(GetSize(sig_q)); + rst_value.resize(GetSize(sig_q), State::S0); cell->setParam(ID::SRST_VALUE, rst_value); } From 2d5ce8c363ff342f25dfe582318c193b2886f0f0 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:34 +0000 Subject: [PATCH 085/188] Update passes/proc to avoid bits() --- passes/proc/proc_init.cc | 12 +++++------- passes/proc/proc_memwr.cc | 2 +- passes/proc/proc_rom.cc | 12 ++++++------ 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 99cacf5fd..3d27eaa9a 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -52,17 +52,15 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) Const value = valuesig.as_const(); Const &wireinit = lhs_c.wire->attributes[ID::init]; - - while (GetSize(wireinit) < lhs_c.wire->width) - wireinit.bits().push_back(State::Sx); - + if (GetSize(wireinit) < lhs_c.wire->width) + wireinit.resize(lhs_c.wire->width, State::Sx); for (int i = 0; i < lhs_c.width; i++) { - auto &initbit = wireinit.bits()[i + lhs_c.offset]; + int index = i + lhs_c.offset; + State initbit = wireinit[index]; if (initbit != State::Sx && initbit != value[i]) log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c)); - initbit = value[i]; + wireinit.set(index, value[i]); } - log(" Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit)); } offset += lhs_c.width; diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index 88aea39bb..a5ae0d6d5 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -39,7 +39,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n Const priority_mask(State::S0, port_id); for (int i = 0; i < GetSize(prev_port_ids); i++) if (memwr.priority_mask[i] == State::S1) - priority_mask.bits()[prev_port_ids[i]] = State::S1; + priority_mask.set(prev_port_ids[i], State::S1); prev_port_ids.push_back(port_id); RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2)); diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index d3b781e60..a7b485194 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -97,7 +97,7 @@ struct RomWorker log_debug("rejecting switch: lhs not uniform\n"); return; } - val.bits()[it2->second] = it.second[i].data; + val.set(it2->second, it.second[i].data); } } for (auto bit: val) { @@ -114,7 +114,7 @@ struct RomWorker } Const c = addr.as_const(); while (GetSize(c) && c.back() == State::S0) - c.bits().pop_back(); + c.resize(c.size() - 1, State::S0); if (GetSize(c) > swsigbits) continue; if (GetSize(c) > 30) { @@ -155,22 +155,22 @@ struct RomWorker Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits); mem.attributes = sw->attributes; - Const init_data; + Const::Builder builder(mem.size * GetSize(lhs)); for (int i = 0; i < mem.size; i++) { auto it = vals.find(i); if (it == vals.end()) { log_assert(got_default); for (auto bit: default_val) - init_data.bits().push_back(bit); + builder.push_back(bit); } else { for (auto bit: it->second) - init_data.bits().push_back(bit); + builder.push_back(bit); } } MemInit init; init.addr = 0; - init.data = init_data; + init.data = builder.build(); init.en = Const(State::S1, GetSize(lhs)); mem.inits.push_back(std::move(init)); From d1642bf510e02bdcff4acca738a6e459c3662f59 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:42 +0000 Subject: [PATCH 086/188] Update passes/sat to avoid bits() --- passes/sat/eval.cc | 4 ++-- passes/sat/formalff.cc | 2 +- passes/sat/sat.cc | 29 ++++++++++++++++++----------- passes/sat/sim.cc | 32 ++++++++++++++------------------ 4 files changed, 35 insertions(+), 32 deletions(-) diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index bde5e1ecb..f71e8124b 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -256,7 +256,7 @@ struct VlogHammerReporter for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); - recorded_set_vals.bits().push_back(bits.back()); + recorded_set_vars.append(RTLIL::Const(bits.back())); bits.pop_back(); } if (module == modules.front()) { @@ -346,7 +346,7 @@ struct VlogHammerReporter log_error("Pattern %s is to short!\n", pattern); patterns.push_back(sig.as_const()); if (invert_pattern) { - for (auto &bit : patterns.back().bits()) + for (auto bit : patterns.back()) if (bit == RTLIL::State::S0) bit = RTLIL::State::S1; else if (bit == RTLIL::State::S1) diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index 286bf2976..c0b0cfc15 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -851,7 +851,7 @@ struct FormalFfPass : public Pass { auto before = ff.val_init; for (int i = 0; i < ff.width; i++) if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i])) - ff.val_init.bits()[i] = State::S0; + ff.val_init.set(i, State::S0); if (ff.val_init != before) { log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n", diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 967cb0472..5216390da 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -620,14 +620,18 @@ struct SatHelper int last_timestep = -2; for (auto &info : modelInfo) { - RTLIL::Const value; bool found_undef = false; + RTLIL::Const::Builder value_builder(info.width); for (int i = 0; i < info.width; i++) { - value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); - if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits().back() = RTLIL::State::Sx, found_undef = true; + RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0; + if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) { + bit = RTLIL::State::Sx; + found_undef = true; + } + value_builder.push_back(bit); } + RTLIL::Const value = value_builder.build(); if (info.timestep != last_timestep) { const char *hline = "---------------------------------------------------------------------------------------------------" @@ -732,13 +736,14 @@ struct SatHelper int last_timestep = -2; for (auto &info : modelInfo) { - RTLIL::Const value; - + RTLIL::Const::Builder value_builder(info.width); for (int i = 0; i < info.width; i++) { - value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0; if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits().back() = RTLIL::State::Sx; + bit = RTLIL::State::Sx; + value_builder.push_back(bit); } + RTLIL::Const value = value_builder.build(); if (info.timestep != last_timestep) { if(last_timestep == 0) @@ -779,12 +784,14 @@ struct SatHelper for (auto &info : modelInfo) { - Const value; + RTLIL::Const::Builder value_builder(info.width); for (int i = 0; i < info.width; i++) { - value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0); + RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0; if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) - value.bits().back() = RTLIL::State::Sx; + bit = RTLIL::State::Sx; + value_builder.push_back(bit); } + Const value = value_builder.build(); wavedata[info.description].first = info.width; wavedata[info.description].second[info.timestep] = value; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 0510bc7df..aadea328f 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -127,16 +127,11 @@ struct SimShared bool initstate = true; }; -void zinit(State &v) -{ - if (v != State::S1) - v = State::S0; -} - void zinit(Const &v) { - for (auto &bit : v.bits()) - zinit(bit); + for (auto bit : v) + if (bit != State::S1) + bit = State::S0; } struct SimInstance @@ -419,16 +414,17 @@ struct SimInstance Const get_state(SigSpec sig) { - Const value; + Const::Builder builder(GetSize(sig)); for (auto bit : sigmap(sig)) if (bit.wire == nullptr) - value.bits().push_back(bit.data); + builder.push_back(bit.data); else if (state_nets.count(bit)) - value.bits().push_back(state_nets.at(bit)); + builder.push_back(state_nets.at(bit)); else - value.bits().push_back(State::Sz); + builder.push_back(State::Sz); + Const value = builder.build(); if (shared->debug) log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); return value; @@ -488,7 +484,7 @@ struct SimInstance for (int i = 0; i < GetSize(data); i++) if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa) if (state.data[i+offset] != data[i]) - dirty = true, state.data.bits()[i+offset] = data[i]; + dirty = true, state.data.set(i+offset, data[i]); if (dirty) dirty_memories.insert(memid); @@ -500,7 +496,7 @@ struct SimInstance if (offset >= state.mem->size * state.mem->width) log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid)); if (state.data[offset] != data) { - state.data.bits()[offset] = data; + state.data.set(offset, data); dirty_memories.insert(memid); } } @@ -717,10 +713,10 @@ struct SimInstance for(int i=0;i= 0 && index < mem.size) for (int i = 0; i < (mem.width << port.wide_log2); i++) if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) { - mdb.data.bits().at(index*mem.width+i) = data[i]; + mdb.data.set(index*mem.width+i, data[i]); dirty_memories.insert(mem.memid); did_something = true; } @@ -971,7 +967,7 @@ struct SimInstance if (w->attributes.count(ID::init) == 0) w->attributes[ID::init] = Const(State::Sx, GetSize(w)); - w->attributes[ID::init].bits()[sig_q[i].offset] = initval[i]; + w->attributes[ID::init].set(sig_q[i].offset, initval[i]); } } From 8cc86b264355a35c210660d1bb29a0ab0dba23bc Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:53:51 +0000 Subject: [PATCH 087/188] Update passes/techmap to avoid bits() --- passes/techmap/abc9_ops.cc | 11 +++++++---- passes/techmap/dffinit.cc | 6 +++--- passes/techmap/dfflegalize.cc | 8 ++++---- passes/techmap/flowmap.cc | 2 +- passes/techmap/techmap.cc | 9 +++++---- passes/techmap/zinit.cc | 2 +- 6 files changed, 21 insertions(+), 17 deletions(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 91149ac55..069b94204 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1216,7 +1216,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) auto Qi = initmap(Q); auto it = Qi.wire->attributes.find(ID::init); if (it != Qi.wire->attributes.end()) - it->second.bits()[Qi.offset] = State::Sx; + it->second.set(Qi.offset, State::Sx); } else if (cell->type.in(ID($_AND_), ID($_NOT_))) module->remove(cell); @@ -1526,8 +1526,11 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) log_assert(index < GetSize(A)); int i = 0; while (i < GetSize(mask)) { - for (int j = 0; j < (1 << index); j++) - std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]); + for (int j = 0; j < (1 << index); j++) { + State bit = mask[i+j]; + mask.set(i+j, mask[i+j+(1 << index)]); + mask.set(i+j+(1 << index), bit); + } i += 1 << (index+1); } A[index] = y_bit; @@ -1542,7 +1545,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // and get cleaned away clone_lut: driver_mask = driver_lut->getParam(ID::LUT); - for (auto &b : driver_mask.bits()) { + for (auto b : driver_mask) { if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index ee83105fd..013675c8a 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -118,13 +118,13 @@ struct DffinitPass : public Pass { for (int i = 0; i < GetSize(sig); i++) { if (initval[i] == State::Sx) continue; - while (GetSize(value) <= i) - value.bits().push_back(State::S0); + if (GetSize(value) <= i) + value.resize(i + 1, State::S0); if (noreinit && value[i] != State::Sx && value[i] != initval[i]) log_error("Trying to assign a different init value for %s.%s.%s which technically " "have a conflicted init value.\n", log_id(module), log_id(cell), log_id(it.second)); - value.bits()[i] = initval[i]; + value.set(i, initval[i]); } if (highlow_mode && GetSize(value) != 0) { diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index facea2e90..5a622c611 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass { if (ff.has_arst) { if (ff.val_arst[i] == State::Sx) { if (!(supported & (mask << 8))) - ff.val_arst.bits()[i] = State::S0; + ff.val_arst.set(i, State::S0); if (!(supported & (mask << 4))) - ff.val_arst.bits()[i] = State::S1; + ff.val_arst.set(i, State::S1); } } if (ff.has_srst) { if (ff.val_srst[i] == State::Sx) { if (!(supported & (mask << 8))) - ff.val_srst.bits()[i] = State::S0; + ff.val_srst.set(i, State::S0); if (!(supported & (mask << 4))) - ff.val_srst.bits()[i] = State::S1; + ff.val_srst.set(i, State::S1); } } } diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 7fbe54849..f5f225a9b 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1401,7 +1401,7 @@ struct FlowmapWorker log_signal(node), log_signal(undef), env.c_str()); } - lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0; + lut_table.set(i, value.as_bool() ? State::S1 : State::S0); ce.pop(); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 2a22258b7..30b8e17ab 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -680,15 +680,16 @@ struct TechmapWorker for (auto &conn : cell->connections()) if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { - RTLIL::Const value; - for (auto &bit : sigmap(conn.second)) { + SigSpec sm = sigmap(conn.second); + RTLIL::Const::Builder builder(GetSize(sm) * bits); + for (auto &bit : sm) { int val = unique_bit_id.at(bit); for (int i = 0; i < bits; i++) { - value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0); + builder.push_back((val & 1) != 0 ? State::S1 : State::S0); val = val >> 1; } } - parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value); + parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), builder.build()); } } diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index bf049eab7..38936e64d 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -76,7 +76,7 @@ struct ZinitPass : public Pass { if (ff.val_init[i] == State::S1) bits.insert(i); else if (ff.val_init[i] != State::S0 && all_mode) - ff.val_init.bits()[i] = State::S0; + ff.val_init.set(i, State::S0); } ff.flip_bits(bits); ff.emit(); From 159ca3ba569d5e850c8610f9a458ae39d0570e6d Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:54:00 +0000 Subject: [PATCH 088/188] Update passes/tests to avoid bits() --- passes/tests/test_cell.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 286ef757d..75a63b2e0 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -641,15 +641,16 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: if (!gold_wire->port_input) continue; - RTLIL::Const in_value; + RTLIL::Const::Builder in_value_builder(GetSize(gold_wire)); for (int i = 0; i < GetSize(gold_wire); i++) - in_value.bits().push_back(xorshift32(2) ? State::S1 : State::S0); + in_value_builder.push_back(xorshift32(2) ? State::S1 : State::S0); + RTLIL::Const in_value = in_value_builder.build(); if (xorshift32(4) == 0) { int inv_chance = 1 + xorshift32(8); for (int i = 0; i < GetSize(gold_wire); i++) if (xorshift32(inv_chance) == 0) - in_value.bits()[i] = RTLIL::Sx; + in_value.set(i, RTLIL::Sx); } if (verbose) From 7f247fb1256ceca143575127169678eee1d1e1af Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:54:13 +0000 Subject: [PATCH 089/188] Update passes/hierarchy to avoid bits() --- passes/hierarchy/submod.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index d77d65359..486d21920 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -79,7 +79,7 @@ struct SubmodWorker flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used); if (set_int_driven) for (int i = c.offset; i < c.offset+c.width; i++) { - wire_flags.at(c.wire).is_int_driven.bits()[i] = State::S1; + wire_flags.at(c.wire).is_int_driven.set(i, State::S1); flag_found_something = true; } } @@ -185,8 +185,8 @@ struct SubmodWorker auto it = sig[i].wire->attributes.find(ID::init); if (it != sig[i].wire->attributes.end()) { auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first; - jt->second.bits()[i] = it->second[sig[i].offset]; - it->second.bits()[sig[i].offset] = State::Sx; + jt->second.set(i, it->second[sig[i].offset]); + it->second.set(sig[i].offset, State::Sx); } } } From 6dc9a8bacfdb9f5c63a420b1aa12afd0f3387301 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:55:47 +0000 Subject: [PATCH 090/188] Update kernel to avoid bits() --- kernel/bitpattern.h | 2 +- kernel/calc.cc | 92 +++++++++++++++++++------------------------ kernel/celltypes.h | 8 ++-- kernel/consteval.h | 4 +- kernel/drivertools.cc | 9 ++--- kernel/ff.cc | 31 +++++++++++---- kernel/ffinit.h | 10 ++--- kernel/ffmerge.cc | 24 +++++------ kernel/macc.h | 2 +- kernel/mem.cc | 73 ++++++++++++++++++++++------------ kernel/mem.h | 6 ++- kernel/rtlil.cc | 2 +- kernel/tclapi.cc | 7 ++-- kernel/yw.cc | 3 +- 14 files changed, 151 insertions(+), 122 deletions(-) diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 0e12e6dce..e2071436c 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -100,7 +100,7 @@ struct BitPatternPool bits_t sig2bits(RTLIL::SigSpec sig) { bits_t bits; - bits.bitdata = sig.as_const().bits(); + bits.bitdata = sig.as_const().to_bits(); for (auto &b : bits.bitdata) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; diff --git a/kernel/calc.cc b/kernel/calc.cc index f08c97396..9b0885db9 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -33,10 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) if (arg.size() > 0 && is_signed) padding = arg.back(); - while (GetSize(arg) < width) - arg.bits().push_back(padding); - - arg.bits().resize(width); + arg.resize(width, padding); } static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) @@ -79,12 +76,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b { mag--; for (auto i = 0; i < result_len; i++) - result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; + result.set(i, mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1); } else { for (auto i = 0; i < result_len; i++) - result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; + result.set(i, mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0); } } @@ -140,11 +137,11 @@ RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, boo RTLIL::Const result(RTLIL::State::Sx, result_len); for (auto i = 0; i < result_len; i++) { if (i >= GetSize(arg1_ext)) - result.bits()[i] = RTLIL::State::S0; - else if (arg1_ext.bits()[i] == RTLIL::State::S0) - result.bits()[i] = RTLIL::State::S1; - else if (arg1_ext.bits()[i] == RTLIL::State::S1) - result.bits()[i] = RTLIL::State::S0; + result.set(i, RTLIL::State::S0); + else if (arg1_ext[i] == RTLIL::State::S0) + result.set(i, RTLIL::State::S1); + else if (arg1_ext[i] == RTLIL::State::S1) + result.set(i, RTLIL::State::S0); } return result; @@ -161,9 +158,9 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL: RTLIL::Const result(RTLIL::State::Sx, result_len); for (auto i = 0; i < result_len; i++) { - RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0; - RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0; - result.bits()[i] = logic_func(a, b); + RTLIL::State a = i < GetSize(arg1) ? arg1[i] : RTLIL::State::S0; + RTLIL::State b = i < GetSize(arg2) ? arg2[i] : RTLIL::State::S0; + result.set(i, logic_func(a, b)); } return result; @@ -197,8 +194,8 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log temp = logic_func(temp, arg1[i]); RTLIL::Const result(temp); - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -222,9 +219,9 @@ RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Con RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len); if (!buffer.empty()) { if (buffer.front() == RTLIL::State::S0) - buffer.bits().front() = RTLIL::State::S1; + buffer.set(0, RTLIL::State::S1); else if (buffer.front() == RTLIL::State::S1) - buffer.bits().front() = RTLIL::State::S0; + buffer.set(0, RTLIL::State::S0); } return buffer; } @@ -239,9 +236,8 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const int undef_bit_pos_a = -1; BigInteger a = const2big(arg1, signed1, undef_bit_pos_a); RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -254,9 +250,8 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_and(bit_a, bit_b)); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -269,9 +264,8 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::Const result(logic_or(bit_a, bit_b)); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -295,11 +289,11 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co for (int i = 0; i < result_len; i++) { BigInteger pos = BigInteger(i) + offset; if (pos < 0) - result.bits()[i] = vacant_bits; + result.set(i, vacant_bits); else if (pos >= BigInteger(GetSize(arg1))) - result.bits()[i] = sign_ext ? arg1.back() : vacant_bits; + result.set(i, sign_ext ? arg1.back() : vacant_bits); else - result.bits()[i] = arg1[pos.toInt()]; + result.set(i, arg1[pos.toInt()]); } return result; @@ -346,9 +340,8 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, int undef_bit_pos = -1; bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -357,9 +350,8 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, int undef_bit_pos = -1; bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -383,7 +375,7 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, matched_status = RTLIL::State::Sx; } - result.bits().front() = matched_status; + result.set(0, matched_status); return result; } @@ -391,9 +383,9 @@ RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, { RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len); if (result.front() == RTLIL::State::S0) - result.bits().front() = RTLIL::State::S1; + result.set(0, RTLIL::State::S1); else if (result.front() == RTLIL::State::S1) - result.bits().front() = RTLIL::State::S0; + result.set(0, RTLIL::State::S0); return result; } @@ -412,7 +404,7 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2 return result; } - result.bits().front() = RTLIL::State::S1; + result.set(0, RTLIL::State::S1); return result; } @@ -420,9 +412,9 @@ RTLIL::Const RTLIL::const_nex(const RTLIL::Const &arg1, const RTLIL::Const &arg2 { RTLIL::Const result = RTLIL::const_eqx(arg1, arg2, signed1, signed2, result_len); if (result.front() == RTLIL::State::S0) - result.bits().front() = RTLIL::State::S1; + result.set(0, RTLIL::State::S1); else if (result.front() == RTLIL::State::S1) - result.bits().front() = RTLIL::State::S0; + result.set(0, RTLIL::State::S0); return result; } @@ -431,9 +423,8 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, int undef_bit_pos = -1; bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -442,9 +433,8 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, int undef_bit_pos = -1; bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); - - while (GetSize(result) < result_len) - result.bits().push_back(RTLIL::State::S0); + if (GetSize(result) < result_len) + result.resize(result_len, RTLIL::State::S0); return result; } @@ -628,7 +618,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2 RTLIL::Const ret = arg1; for (auto i = 0; i < ret.size(); i++) if (ret[i] != arg2[i]) - ret.bits()[i] = State::Sx; + ret.set(i, State::Sx); return ret; } @@ -703,7 +693,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar log_assert(arg2.size() == arg1.size()); RTLIL::Const result(RTLIL::State::S0, arg1.size()); for (auto i = 0; i < arg1.size(); i++) - result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0; + result.set(i, arg1[i] == arg2[i] ? State::S1 : State::S0); return result; } @@ -715,7 +705,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar RTLIL::Const result(RTLIL::State::Sx, arg1.size()); for (auto i = 0; i < arg1.size(); i++) { if (arg3[i] != State::Sx || arg1[i] == arg2[i]) - result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i]; + result.set(i, arg3[i] == State::S1 ? arg2[i] : arg1[i]); } return result; diff --git a/kernel/celltypes.h b/kernel/celltypes.h index f08a695e9..469017029 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -328,7 +328,7 @@ struct CellTypes static RTLIL::Const eval_not(RTLIL::Const v) { - for (auto &bit : v.bits()) + for (auto bit : v) if (bit == State::S0) bit = State::S1; else if (bit == State::S1) bit = State::S0; return v; @@ -421,16 +421,14 @@ struct CellTypes static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr) { if (cell->type == ID($slice)) { - RTLIL::Const ret; int width = cell->parameters.at(ID::Y_WIDTH).as_int(); int offset = cell->parameters.at(ID::OFFSET).as_int(); - ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width); - return ret; + return arg1.extract(offset, width); } if (cell->type == ID($concat)) { RTLIL::Const ret = arg1; - ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end()); + ret.append(arg2); return ret; } diff --git a/kernel/consteval.h b/kernel/consteval.h index adcf86f8a..b13c7ea5c 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -115,7 +115,7 @@ struct ConstEval for (int i = 0; i < GetSize(coval); i++) { carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry); - coval.bits()[i] = carry ? State::S1 : State::S0; + coval.set(i, carry ? State::S1 : State::S0); } set(sig_co, coval); @@ -249,7 +249,7 @@ struct ConstEval for (int i = 0; i < GetSize(val_y); i++) if (val_y[i] == RTLIL::Sx) - val_x.bits()[i] = RTLIL::Sx; + val_x.set(i, RTLIL::Sx); set(sig_y, val_y); set(sig_x, val_x); diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 6290f4470..90bfb0ee7 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -260,7 +260,7 @@ bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit) switch (single.type()) { case DriveType::CONSTANT: { - single.constant().bits().push_back(constant); + single.constant().append(RTLIL::Const(constant)); } break; case DriveType::WIRE: { single.wire().width += 1; @@ -295,8 +295,7 @@ bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk) switch (single.type()) { case DriveType::CONSTANT: { - auto &bits = single.constant().bits(); - bits.insert(bits.end(), constant.bits().begin(), constant.bits().end()); + single.constant().append(constant); } break; case DriveType::WIRE: { single.wire().width += width; @@ -349,7 +348,7 @@ bool DriveChunk::try_append(DriveBit const &bit) none_ += 1; return true; case DriveType::CONSTANT: - constant_.bits().push_back(bit.constant()); + constant_.append(RTLIL::Const(bit.constant())); return true; case DriveType::WIRE: return wire_.try_append(bit.wire()); @@ -375,7 +374,7 @@ bool DriveChunk::try_append(DriveChunk const &chunk) none_ += chunk.none_; return true; case DriveType::CONSTANT: - constant_.bits().insert(constant_.bits().end(), chunk.constant_.begin(), chunk.constant_.end()); + constant_.append(chunk.constant_); return true; case DriveType::WIRE: return wire_.try_append(chunk.wire()); diff --git a/kernel/ff.cc b/kernel/ff.cc index 8b38b84cb..a72e6a65c 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -287,6 +287,16 @@ FfData FfData::slice(const std::vector &bits) { res.pol_clr = pol_clr; res.pol_set = pol_set; res.attributes = attributes; + std::optional arst_bits; + if (has_arst) + arst_bits.emplace(bits.size()); + std::optional srst_bits; + if (has_srst) + srst_bits.emplace(bits.size()); + std::optional init_bits; + if (initvals) + init_bits.emplace(bits.size()); + for (int i : bits) { res.sig_q.append(sig_q[i]); if (has_clk || has_gclk) @@ -298,12 +308,19 @@ FfData FfData::slice(const std::vector &bits) { res.sig_set.append(sig_set[i]); } if (has_arst) - res.val_arst.bits().push_back(val_arst[i]); + arst_bits->push_back(val_arst[i]); if (has_srst) - res.val_srst.bits().push_back(val_srst[i]); + srst_bits->push_back(val_srst[i]); if (initvals) - res.val_init.bits().push_back(val_init[i]); + init_bits->push_back(val_init[i]); } + + if (has_arst) + res.val_arst = arst_bits->build(); + if (has_srst) + res.val_srst = srst_bits->build(); + if (initvals) + res.val_init = init_bits->build(); res.width = GetSize(res.sig_q); return res; } @@ -688,10 +705,10 @@ void FfData::flip_rst_bits(const pool &bits) { for (auto bit: bits) { if (has_arst) - val_arst.bits()[bit] = invert(val_arst[bit]); + val_arst.set(bit, invert(val_arst[bit])); if (has_srst) - val_srst.bits()[bit] = invert(val_srst[bit]); - val_init.bits()[bit] = invert(val_init[bit]); + val_srst.set(bit, invert(val_srst[bit])); + val_init.set(bit, invert(val_init[bit])); } } @@ -760,7 +777,7 @@ void FfData::flip_bits(const pool &bits) { Const mask = Const(State::S0, width); for (auto bit: bits) - mask.bits()[bit] = State::S1; + mask.set(bit, State::S1); if (has_clk || has_gclk) sig_d = module->Xor(NEW_ID, sig_d, mask); diff --git a/kernel/ffinit.h b/kernel/ffinit.h index 66c13b68f..920fba307 100644 --- a/kernel/ffinit.h +++ b/kernel/ffinit.h @@ -74,10 +74,10 @@ struct FfInitVals RTLIL::Const operator()(const RTLIL::SigSpec &sig) const { - RTLIL::Const res; + RTLIL::Const::Builder res_bits(GetSize(sig)); for (auto bit : sig) - res.bits().push_back((*this)(bit)); - return res; + res_bits.push_back((*this)(bit)); + return res_bits.build(); } void set_init(RTLIL::SigBit bit, RTLIL::State val) @@ -93,12 +93,12 @@ struct FfInitVals initbits[mbit] = std::make_pair(val,abit); auto it2 = abit.wire->attributes.find(ID::init); if (it2 != abit.wire->attributes.end()) { - it2->second.bits()[abit.offset] = val; + it2->second.set(abit.offset, val); if (it2->second.is_fully_undef()) abit.wire->attributes.erase(it2); } else if (val != State::Sx) { Const cval(State::Sx, GetSize(abit.wire)); - cval.bits()[abit.offset] = val; + cval.set(abit.offset, val); abit.wire->attributes[ID::init] = cval; } } diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 3b361c1c2..632cba05c 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -42,9 +42,9 @@ bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, poolparameters[ID::WIDTH] = Const(width); cell->parameters[ID::OFFSET] = Const(start_offset); cell->parameters[ID::SIZE] = Const(size); - Const rd_wide_continuation, rd_clk_enable, rd_clk_polarity, rd_transparency_mask, rd_collision_x_mask; - Const wr_wide_continuation, wr_clk_enable, wr_clk_polarity, wr_priority_mask; - Const rd_ce_over_srst, rd_arst_value, rd_srst_value, rd_init_value; SigSpec rd_clk, rd_en, rd_addr, rd_data; SigSpec wr_clk, wr_en, wr_addr, wr_data; SigSpec rd_arst, rd_srst; @@ -147,6 +144,15 @@ void Mem::emit() { for (int i = 0; i < GetSize(wr_ports); i++) for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++) wr_port_xlat.push_back(i); + Const::Builder rd_wide_continuation_builder; + Const::Builder rd_clk_enable_builder; + Const::Builder rd_clk_polarity_builder; + Const::Builder rd_transparency_mask_builder; + Const::Builder rd_collision_x_mask_builder; + Const::Builder rd_ce_over_srst_builder; + Const::Builder rd_arst_value_builder; + Const::Builder rd_srst_value_builder; + Const::Builder rd_init_value_builder; for (auto &port : rd_ports) { for (auto attr: port.attributes) if (!cell->has_attribute(attr.first)) @@ -157,10 +163,10 @@ void Mem::emit() { } for (int sub = 0; sub < (1 << port.wide_log2); sub++) { - rd_wide_continuation.bits().push_back(State(sub != 0)); - rd_clk_enable.bits().push_back(State(port.clk_enable)); - rd_clk_polarity.bits().push_back(State(port.clk_polarity)); - rd_ce_over_srst.bits().push_back(State(port.ce_over_srst)); + rd_wide_continuation_builder.push_back(State(sub != 0)); + rd_clk_enable_builder.push_back(State(port.clk_enable)); + rd_clk_polarity_builder.push_back(State(port.clk_polarity)); + rd_ce_over_srst_builder.push_back(State(port.ce_over_srst)); rd_clk.append(port.clk); rd_arst.append(port.arst); rd_srst.append(port.srst); @@ -170,18 +176,27 @@ void Mem::emit() { rd_addr.append(addr); log_assert(GetSize(addr) == abits); for (auto idx : wr_port_xlat) { - rd_transparency_mask.bits().push_back(State(bool(port.transparency_mask[idx]))); - rd_collision_x_mask.bits().push_back(State(bool(port.collision_x_mask[idx]))); + rd_transparency_mask_builder.push_back(State(bool(port.transparency_mask[idx]))); + rd_collision_x_mask_builder.push_back(State(bool(port.collision_x_mask[idx]))); } } rd_data.append(port.data); for (auto bit : port.arst_value) - rd_arst_value.bits().push_back(bit); + rd_arst_value_builder.push_back(bit); for (auto bit : port.srst_value) - rd_srst_value.bits().push_back(bit); + rd_srst_value_builder.push_back(bit); for (auto bit : port.init_value) - rd_init_value.bits().push_back(bit); + rd_init_value_builder.push_back(bit); } + Const rd_wide_continuation = rd_wide_continuation_builder.build(); + Const rd_clk_enable = rd_clk_enable_builder.build(); + Const rd_clk_polarity = rd_clk_polarity_builder.build(); + Const rd_transparency_mask = rd_transparency_mask_builder.build(); + Const rd_collision_x_mask = rd_collision_x_mask_builder.build(); + Const rd_ce_over_srst = rd_ce_over_srst_builder.build(); + Const rd_arst_value = rd_arst_value_builder.build(); + Const rd_srst_value = rd_srst_value_builder.build(); + Const rd_init_value = rd_init_value_builder.build(); if (rd_ports.empty()) { rd_wide_continuation = State::S0; rd_clk_enable = State::S0; @@ -212,6 +227,10 @@ void Mem::emit() { cell->setPort(ID::RD_SRST, rd_srst); cell->setPort(ID::RD_ADDR, rd_addr); cell->setPort(ID::RD_DATA, rd_data); + Const::Builder wr_wide_continuation_builder; + Const::Builder wr_clk_enable_builder; + Const::Builder wr_clk_polarity_builder; + Const::Builder wr_priority_mask_builder; for (auto &port : wr_ports) { for (auto attr: port.attributes) if (!cell->has_attribute(attr.first)) @@ -222,12 +241,12 @@ void Mem::emit() { } for (int sub = 0; sub < (1 << port.wide_log2); sub++) { - wr_wide_continuation.bits().push_back(State(sub != 0)); - wr_clk_enable.bits().push_back(State(port.clk_enable)); - wr_clk_polarity.bits().push_back(State(port.clk_polarity)); + wr_wide_continuation_builder.push_back(State(sub != 0)); + wr_clk_enable_builder.push_back(State(port.clk_enable)); + wr_clk_polarity_builder.push_back(State(port.clk_polarity)); wr_clk.append(port.clk); for (auto idx : wr_port_xlat) - wr_priority_mask.bits().push_back(State(bool(port.priority_mask[idx]))); + wr_priority_mask_builder.push_back(State(bool(port.priority_mask[idx]))); SigSpec addr = port.sub_addr(sub); addr.extend_u0(abits, false); wr_addr.append(addr); @@ -236,6 +255,10 @@ void Mem::emit() { wr_en.append(port.en); wr_data.append(port.data); } + Const wr_wide_continuation = wr_wide_continuation_builder.build(); + Const wr_clk_enable = wr_clk_enable_builder.build(); + Const wr_clk_polarity = wr_clk_polarity_builder.build(); + Const wr_priority_mask = wr_priority_mask_builder.build(); if (wr_ports.empty()) { wr_wide_continuation = State::S0; wr_clk_enable = State::S0; @@ -414,7 +437,7 @@ void Mem::coalesce_inits() { if (!init.en.is_fully_ones()) { for (int i = 0; i < GetSize(init.data); i++) if (init.en[i % width] != State::S1) - init.data.bits()[i] = State::Sx; + init.data.set(i, State::Sx); init.en = Const(State::S1, width); } continue; @@ -427,7 +450,7 @@ void Mem::coalesce_inits() { log_assert(offset + GetSize(init.data) <= GetSize(cdata)); for (int i = 0; i < GetSize(init.data); i++) if (init.en[i % width] == State::S1) - cdata.bits()[i+offset] = init.data[i]; + cdata.set(i+offset, init.data[i]); init.removed = true; } MemInit new_init; @@ -446,7 +469,7 @@ Const Mem::get_init_data() const { int offset = (init.addr.as_int() - start_offset) * width; for (int i = 0; i < GetSize(init.data); i++) if (0 <= i+offset && i+offset < GetSize(init_data) && init.en[i % width] == State::S1) - init_data.bits()[i+offset] = init.data[i]; + init_data.set(i+offset, init.data[i]); } return init_data; } @@ -1700,7 +1723,7 @@ MemContents::MemContents(Mem *mem) : RTLIL::Const previous = (*this)[addr + i]; for(int j = 0; j < _data_width; j++) if(init.en[j] != State::S1) - data.bits()[_data_width * i + j] = previous[j]; + data.set(_data_width * i + j, previous[j]); } insert_concatenated(init.addr.as_int(), data); } @@ -1846,7 +1869,7 @@ std::map::iterator MemContents::_reserve_rang // we have two different ranges touching at either end, we need to merge them auto upper_end = _range_end(upper_it); // make range bigger (maybe reserve here instead of resize?) - lower_it->second.bits().resize(_range_offset(lower_it, upper_end), State::Sx); + lower_it->second.resize(_range_offset(lower_it, upper_end), State::Sx); // copy only the data beyond our range std::copy(_range_data(upper_it, end_addr), _range_data(upper_it, upper_end), _range_data(lower_it, end_addr)); // keep lower_it, but delete upper_it @@ -1854,16 +1877,16 @@ std::map::iterator MemContents::_reserve_rang return lower_it; } else if (lower_touch) { // we have a range to the left, just make it bigger and delete any other that may exist. - lower_it->second.bits().resize(_range_offset(lower_it, end_addr), State::Sx); + lower_it->second.resize(_range_offset(lower_it, end_addr), State::Sx); // keep lower_it and upper_it _values.erase(std::next(lower_it), upper_it); return lower_it; } else if (upper_touch) { // we have a range to the right, we need to expand it // since we need to erase and reinsert to a new address, steal the data - RTLIL::Const data = std::move(upper_it->second); // note that begin_addr is not in upper_it, otherwise the whole range covered check would have tripped - data.bits().insert(data.bits().begin(), (_range_begin(upper_it) - begin_addr) * _data_width, State::Sx); + RTLIL::Const data(State::Sx, (_range_begin(upper_it) - begin_addr) * _data_width); + data.append(std::move(upper_it->second)); // delete lower_it and upper_it, then reinsert _values.erase(lower_it, std::next(upper_it)); return _values.emplace(begin_addr, std::move(data)).first; @@ -1886,7 +1909,7 @@ void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) { std::fill(to_begin + values.size(), to_begin + words * _data_width, State::S0); } -std::vector::iterator MemContents::_range_write(std::vector::iterator it, RTLIL::Const const &word) { +RTLIL::Const::iterator MemContents::_range_write(RTLIL::Const::iterator it, RTLIL::Const const &word) { auto from_end = word.size() <= _data_width ? word.end() : word.begin() + _data_width; auto to_end = std::copy(word.begin(), from_end, it); auto it_next = std::next(it, _data_width); diff --git a/kernel/mem.h b/kernel/mem.h index a06f44bd8..b35ea52c7 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -255,11 +255,13 @@ private: // return the offset the addr would have in the range at `it` size_t _range_offset(std::map::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; } // assuming _range_contains(it, addr), return an iterator pointing to the data at addr - std::vector::iterator _range_data(std::map::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); } + RTLIL::Const::iterator _range_data(std::map::iterator it, addr_t addr) { + return RTLIL::Const::iterator(it->second, _range_offset(it, addr)); + } // internal version of reserve_range that returns an iterator to the range std::map::iterator _reserve_range(addr_t begin_addr, addr_t end_addr); // write a single word at addr, return iterator to next word - std::vector::iterator _range_write(std::vector::iterator it, RTLIL::Const const &data); + RTLIL::Const::iterator _range_write(RTLIL::Const::iterator it, RTLIL::Const const &data); public: class range { int _data_width; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8d7f89650..62f7ae4f7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -486,7 +486,7 @@ int RTLIL::Const::get_min_size(bool is_signed) const void RTLIL::Const::compress(bool is_signed) { auto idx = get_min_size(is_signed); - bits().erase(bits().begin() + idx, bits().end()); + resize(idx, RTLIL::State::S0); } std::optional RTLIL::Const::as_int_compress(bool is_signed) const diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 4bdb680ac..729d06ca0 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -214,18 +214,19 @@ bool mp_int_to_const(mp_int *a, Const &b, bool is_signed) buf.resize(mp_unsigned_bin_size(a)); mp_to_unsigned_bin(a, buf.data()); - b.bits().reserve(mp_count_bits(a) + is_signed); + Const::Builder b_bits(mp_count_bits(a) + is_signed); for (int i = 0; i < mp_count_bits(a);) { for (int j = 0; j < 8 && i < mp_count_bits(a); j++, i++) { bool bv = ((buf.back() & (1 << j)) != 0) ^ negative; - b.bits().push_back(bv ? RTLIL::S1 : RTLIL::S0); + b_bits.push_back(bv ? RTLIL::S1 : RTLIL::S0); } buf.pop_back(); } if (is_signed) { - b.bits().push_back(negative ? RTLIL::S1 : RTLIL::S0); + b_bits.push_back(negative ? RTLIL::S1 : RTLIL::S0); } + b = b_bits.build(); return true; } diff --git a/kernel/yw.cc b/kernel/yw.cc index daad53380..560f7dd38 100644 --- a/kernel/yw.cc +++ b/kernel/yw.cc @@ -185,7 +185,6 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const const std::string &bits = steps[t].bits; RTLIL::Const result(State::Sa, width); - result.bits().reserve(width); int read_begin = GetSize(bits) - 1 - bits_offset; int read_end = max(-1, read_begin - width); @@ -200,7 +199,7 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const default: log_abort(); } - result.bits()[j] = bit; + result.set(j, bit); } return result; From 09b493cfcd6ec79320e9a1f660b93ebd6a80085e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:55:56 +0000 Subject: [PATCH 091/188] Update techlibs to avoid bits() --- techlibs/gatemate/gatemate_foldinv.cc | 4 ++-- techlibs/greenpak4/greenpak4_dffinv.cc | 8 ++++---- techlibs/microchip/microchip_dffopt.cc | 2 +- techlibs/microchip/microchip_dsp.cc | 4 ++-- techlibs/quicklogic/ql_dsp_simd.cc | 6 ++---- techlibs/xilinx/xilinx_dffopt.cc | 6 +++--- techlibs/xilinx/xilinx_dsp.cc | 8 ++++---- techlibs/xilinx/xilinx_srl.cc | 10 ++++------ 8 files changed, 22 insertions(+), 26 deletions(-) diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index cce5d2c4f..1af6a8987 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -82,7 +82,7 @@ struct FoldInvWorker { Const result(State::S0, GetSize(lut)); for (int i = 0; i < GetSize(lut); i++) { int j = i ^ (1 << bit); - result.bits()[j] = lut[i]; + result.set(j, lut[i]); } return result; } @@ -91,7 +91,7 @@ struct FoldInvWorker { { Const result(State::S0, GetSize(lut)); for (int i = 0; i < GetSize(lut); i++) - result.bits()[i] = (lut[i] == State::S1) ? State::S0 : State::S1; + result.set(i, (lut[i] == State::S1) ? State::S0 : State::S1); return result; } diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index 37f6d8d9b..4f60a5c37 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -36,9 +36,9 @@ void invert_gp_dff(Cell *cell, bool invert_input) Const initval = cell->getParam(ID::INIT); if (GetSize(initval) >= 1) { if (initval[0] == State::S0) - initval.bits()[0] = State::S1; + initval.set(0, State::S1); else if (initval[0] == State::S1) - initval.bits()[0] = State::S0; + initval.set(0, State::S0); cell->setParam(ID::INIT, initval); } @@ -47,9 +47,9 @@ void invert_gp_dff(Cell *cell, bool invert_input) Const srmode = cell->getParam(ID(SRMODE)); if (GetSize(srmode) >= 1) { if (srmode[0] == State::S0) - srmode.bits()[0] = State::S1; + srmode.set(0, State::S1); else if (srmode[0] == State::S1) - srmode.bits()[0] = State::S0; + srmode.set(0, State::S0); cell->setParam(ID(SRMODE), srmode); } } diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index 8a13c4325..98e2f17a7 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -93,7 +93,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1); new_bit = data.first[lut_idx] == State::S1; } - result.first.bits()[i] = new_bit ? State::S1 : State::S0; + result.first.set(i, new_bit ? State::S1 : State::S0); } return true; } diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc index 3dfcb8905..df7093bc5 100644 --- a/techlibs/microchip/microchip_dsp.cc +++ b/techlibs/microchip/microchip_dsp.cc @@ -128,7 +128,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) continue; for (int i = c.offset; i < c.offset + c.width; i++) { log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); - it->second.bits()[i] = State::Sx; + it->second.set(i, State::Sx); } } }; @@ -244,7 +244,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) continue; for (int i = c.offset; i < c.offset + c.width; i++) { log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); - it->second.bits()[i] = State::Sx; + it->second.set(i, State::Sx); } } }; diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index fdd2de406..cd509ce7f 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -200,10 +200,8 @@ struct QlDspSimdPass : public Pass { auto val_a = dsp_a->getParam(it); auto val_b = dsp_b->getParam(it); - mode_bits.bits().insert(mode_bits.bits().end(), - val_a.begin(), val_a.end()); - mode_bits.bits().insert(mode_bits.bits().end(), - val_b.begin(), val_b.end()); + mode_bits.append(val_a); + mode_bits.append(val_b); } // Enable the fractured mode by connecting the control diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index bca3deef9..8a6d3e015 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -92,7 +92,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1); new_bit = data.first[lut_idx] == State::S1; } - result.first.bits()[i] = new_bit ? State::S1 : State::S0; + result.first.set(i, new_bit ? State::S1 : State::S0); } return true; } @@ -211,8 +211,8 @@ lut_sigin_done: Cell *cell_d = it_D->second.second; if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) { // Flip all bits in the LUT. - for (int i = 0; i < GetSize(lut_d.first); i++) - lut_d.first.bits()[i] = (lut_d.first[i] == State::S1) ? State::S0 : State::S1; + for (auto bit : lut_d.first) + bit = (bit == State::S1) ? State::S0 : State::S1; } LutData lut_d_post_ce; diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index f95930a90..22e6bce5b 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -343,7 +343,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) // Since B is an exact power of 2, subtract 1 // by inverting all bits up until hitting // that one hi bit - for (auto &b : B.bits()) + for (auto b : B) if (b == State::S0) b = State::S1; else if (b == State::S1) { b = State::S0; @@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) continue; for (int i = c.offset; i < c.offset+c.width; i++) { log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); - it->second.bits()[i] = State::Sx; + it->second.set(i, State::Sx); } } }; @@ -579,7 +579,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) continue; for (int i = c.offset; i < c.offset+c.width; i++) { log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); - it->second.bits()[i] = State::Sx; + it->second.set(i, State::Sx); } } }; @@ -702,7 +702,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) continue; for (int i = c.offset; i < c.offset+c.width; i++) { log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx); - it->second.bits()[i] = State::Sx; + it->second.set(i, State::Sx); } } }; diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc index 32a0064a6..2c23f8f42 100644 --- a/techlibs/xilinx/xilinx_srl.cc +++ b/techlibs/xilinx/xilinx_srl.cc @@ -40,9 +40,8 @@ void run_fixed(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { - auto &i = it->second.bits()[Q.offset]; - initval.append(i); - i = State::Sx; + initval.append(it->second[Q.offset]); + it->second.set(Q.offset, State::Sx); } else initval.append(State::Sx); @@ -121,9 +120,8 @@ void run_variable(xilinx_srl_pm &pm) log_assert(Q.wire); auto it = Q.wire->attributes.find(ID::init); if (it != Q.wire->attributes.end()) { - auto &i = it->second.bits()[Q.offset]; - initval.append(i); - i = State::Sx; + initval.append(it->second[Q.offset]); + it->second.set(Q.offset, State::Sx); } else initval.append(State::Sx); From 9493292690544ad6f0dc76ddcd04d8e677e2211a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 01:56:27 +0000 Subject: [PATCH 092/188] Update tests to avoid bits() --- tests/unit/kernel/rtlilTest.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 6a5f75a95..a9b7c3ada 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -80,10 +80,10 @@ namespace RTLIL { EXPECT_EQ(i, 16); EXPECT_TRUE(cs1.is_str()); - // It can be mutated with the bits() view - // and decays into unpacked - for (auto& bit : cs1.bits()) { - bit = State::Sx; + // It can be mutated via bit iteration and decays into unpacked + // when an non-defined bit is set. + for (auto b : cs1) { + b = State::Sx; } EXPECT_TRUE(cs1.is_bits()); } From 1e244cd78acc6695154f925369ac1109e5e249ed Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 05:21:21 +0000 Subject: [PATCH 093/188] Deprecate Const::bits() --- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 62f7ae4f7..22467fa8e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -378,7 +378,7 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const return !(*this == other); } -std::vector& RTLIL::Const::bits() +std::vector& RTLIL::Const::bits_internal() { bitvectorize(); return get_bits(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b7776f378..02c8190dc 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -837,6 +837,8 @@ private: bitvectype& get_bits() const; std::string& get_str() const; + std::vector& bits_internal(); + public: Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector()) {} Const(const std::string &str); @@ -864,7 +866,8 @@ public: bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; - std::vector& bits(); + [[deprecated]] + std::vector& bits() { return bits_internal(); } bool as_bool() const; // Convert the constant value to a C++ int. @@ -897,10 +900,10 @@ public: void append(const RTLIL::Const &other); void set(int i, RTLIL::State state) { - bits()[i] = state; + bits_internal()[i] = state; } void resize(int size, RTLIL::State fill) { - bits().resize(size, fill); + bits_internal().resize(size, fill); } class const_iterator { From 61caa5e042ecb59770b2e3bcafdda60bc094cbb2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 06:00:50 +0000 Subject: [PATCH 094/188] Deprecate Const::bitvectorize() --- kernel/rtlil.cc | 26 +++++++++++++------------- kernel/rtlil.h | 7 +++++-- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 22467fa8e..0afe2a3c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -380,7 +380,7 @@ bool RTLIL::Const::operator !=(const RTLIL::Const &other) const std::vector& RTLIL::Const::bits_internal() { - bitvectorize(); + bitvectorize_internal(); return get_bits(); } @@ -394,7 +394,7 @@ std::vector RTLIL::Const::to_bits() const bool RTLIL::Const::as_bool() const { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); for (size_t i = 0; i < bv.size(); i++) if (bv[i] == State::S1) @@ -404,7 +404,7 @@ bool RTLIL::Const::as_bool() const int RTLIL::Const::as_int(bool is_signed) const { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); int32_t ret = 0; for (size_t i = 0; i < bv.size() && i < 32; i++) @@ -496,7 +496,7 @@ std::optional RTLIL::Const::as_int_compress(bool is_signed) const std::string RTLIL::Const::as_string(const char* any) const { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); std::string ret; ret.reserve(bv.size()); @@ -534,7 +534,7 @@ std::string RTLIL::Const::decode_string() const if (auto str = get_if_str()) return *str; - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); const int n = GetSize(bv); const int n_over_8 = n / 8; @@ -583,7 +583,7 @@ bool RTLIL::Const::empty() const { } } -void RTLIL::Const::bitvectorize() const { +void RTLIL::Const::bitvectorize_internal() const { if (tag == backing_tag::bits) return; @@ -609,7 +609,7 @@ void RTLIL::Const::bitvectorize() const { } void RTLIL::Const::append(const RTLIL::Const &other) { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); bv.insert(bv.end(), other.begin(), other.end()); } @@ -625,7 +625,7 @@ RTLIL::State RTLIL::Const::const_iterator::operator*() const { bool RTLIL::Const::is_fully_zero() const { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); cover("kernel.rtlil.const.is_fully_zero"); @@ -638,7 +638,7 @@ bool RTLIL::Const::is_fully_zero() const bool RTLIL::Const::is_fully_ones() const { - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); cover("kernel.rtlil.const.is_fully_ones"); @@ -653,7 +653,7 @@ bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); for (const auto &bit : bv) @@ -667,7 +667,7 @@ bool RTLIL::Const::is_fully_undef() const { cover("kernel.rtlil.const.is_fully_undef"); - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); for (const auto &bit : bv) @@ -681,7 +681,7 @@ bool RTLIL::Const::is_fully_undef_x_only() const { cover("kernel.rtlil.const.is_fully_undef_x_only"); - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); for (const auto &bit : bv) @@ -695,7 +695,7 @@ bool RTLIL::Const::is_onehot(int *pos) const { cover("kernel.rtlil.const.is_onehot"); - bitvectorize(); + bitvectorize_internal(); bitvectype& bv = get_bits(); bool found = false; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 02c8190dc..0691ac2a6 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -838,6 +838,7 @@ private: bitvectype& get_bits() const; std::string& get_str() const; std::vector& bits_internal(); + void bitvectorize_internal() const; public: Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector()) {} @@ -866,8 +867,11 @@ public: bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; - [[deprecated]] + [[deprecated("Don't use direct access to the internal std::vector, that's an implementation detail.")]] std::vector& bits() { return bits_internal(); } + [[deprecated("Don't call bitvectorize() directly, it's an implementation detail.")]] + void bitvectorize() const { bitvectorize_internal(); } + bool as_bool() const; // Convert the constant value to a C++ int. @@ -896,7 +900,6 @@ public: std::string decode_string() const; int size() const; bool empty() const; - void bitvectorize() const; void append(const RTLIL::Const &other); void set(int i, RTLIL::State state) { From b06085ab6c3db59254c0bd2d8dbbf02775b296e1 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 03:08:31 +0000 Subject: [PATCH 095/188] Make Const::Const(long long) constructor use packed bits internally if possible --- kernel/rtlil.cc | 25 +++++++++++++++++++++++++ kernel/rtlil.h | 3 ++- tests/unit/kernel/rtlilTest.cc | 25 +++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 0afe2a3c0..b07468e12 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -257,9 +257,34 @@ RTLIL::Const::Const(const std::string &str) tag = backing_tag::string; } +RTLIL::Const::Const(long long val) // default width 32 +{ + flags = RTLIL::CONST_FLAG_NONE; + char bytes[] = { + (char)(val >> 24), (char)(val >> 16), (char)(val >> 8), (char)val + }; + new ((void*)&str_) std::string(bytes, 4); + tag = backing_tag::string; +} + RTLIL::Const::Const(long long val, int width) { flags = RTLIL::CONST_FLAG_NONE; + if ((width & 7) == 0) { + new ((void*)&str_) std::string(); + tag = backing_tag::string; + std::string& str = get_str(); + int bytes = width >> 3; + signed char sign_byte = val < 0 ? -1 : 0; + str.resize(bytes, sign_byte); + bytes = std::min(bytes, sizeof(val)); + for (int i = 0; i < bytes; i++) { + str[str.size() - 1 - i] = val; + val = val >> 8; + } + return; + } + new ((void*)&bits_) bitvectype(); tag = backing_tag::bits; bitvectype& bv = get_bits(); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 0691ac2a6..6bb6f1fe1 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -843,7 +843,8 @@ private: public: Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector()) {} Const(const std::string &str); - Const(long long val, int width = 32); + Const(long long val); // default width is 32 + Const(long long val, int width); Const(RTLIL::State bit, int width = 1); Const(std::vector bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::move(bits)) {} Const(const std::vector &bits); diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index a9b7c3ada..0b7fbfd37 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -88,6 +88,31 @@ namespace RTLIL { EXPECT_TRUE(cs1.is_bits()); } + { + Const c(0x12345678); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.as_int(), 0x12345678); + } + + { + Const c(0xab, 8); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.as_int(), 0xab); + } + + { + Const c(0x12345678, 80); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.as_int(), 0x12345678); + EXPECT_EQ(c[79], S0); + } + + { + Const c(-1, 80); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.as_int(), -1); + EXPECT_EQ(c[79], S1); + } } TEST_F(KernelRtlilTest, ConstConstIteratorWorks) { From b597ad777e6ab306f82e3cfa521454f29a8c19c5 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 03:09:19 +0000 Subject: [PATCH 096/188] Make Const::as_bool and Const::as_int work with packed bits without decaying to vector --- kernel/rtlil.cc | 34 +++++++++++++++++++++++++--------- tests/unit/kernel/rtlilTest.cc | 11 +++++++++++ 2 files changed, 36 insertions(+), 9 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b07468e12..1228e738f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -419,7 +419,13 @@ std::vector RTLIL::Const::to_bits() const bool RTLIL::Const::as_bool() const { - bitvectorize_internal(); + if (is_str()) { + for (char ch : get_str()) + if (ch != 0) + return true; + return false; + } + bitvectype& bv = get_bits(); for (size_t i = 0; i < bv.size(); i++) if (bv[i] == State::S1) @@ -429,15 +435,25 @@ bool RTLIL::Const::as_bool() const int RTLIL::Const::as_int(bool is_signed) const { - bitvectorize_internal(); - bitvectype& bv = get_bits(); int32_t ret = 0; - for (size_t i = 0; i < bv.size() && i < 32; i++) + if (const std::string *s = get_if_str()) { + int size = GetSize(*s); + // Ignore any bytes after the first 4 since bits beyond 32 are truncated. + for (int i = std::min(4, size); i > 0; i--) + ret |= static_cast((*s)[size - i]) << ((i - 1) * 8); + // If is_signed and the string is shorter than 4 bytes then apply sign extension. + if (is_signed && size > 0 && size < 4 && ((*s)[0] & 0x80)) + ret |= -1 << size*8; + return ret; + } + + const bitvectype& bv = get_bits(); + int significant_bits = std::min(GetSize(bv), 32); + for (int i = 0; i < significant_bits; i++) if (bv[i] == State::S1) ret |= 1 << i; - if (is_signed && bv.back() == State::S1) - for (size_t i = bv.size(); i < 32; i++) - ret |= 1 << i; + if (is_signed && significant_bits > 0 && significant_bits < 32 && bv.back() == State::S1 ) + ret |= -1 << significant_bits; return ret; } @@ -457,7 +473,7 @@ bool RTLIL::Const::convertible_to_int(bool is_signed) const if (size == 32) { if (is_signed) return true; - return get_bits().at(31) != State::S1; + return back() != State::S1; } return false; @@ -478,7 +494,7 @@ int RTLIL::Const::as_int_saturating(bool is_signed) const const auto min_size = get_min_size(is_signed); log_assert(min_size > 0); - const auto neg = get_bits().at(min_size - 1); + const auto neg = (*this)[min_size - 1]; return neg ? std::numeric_limits::min() : std::numeric_limits::max(); } return as_int(is_signed); diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 0b7fbfd37..99ddf44cc 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -92,12 +92,14 @@ namespace RTLIL { Const c(0x12345678); EXPECT_TRUE(c.is_str()); EXPECT_EQ(c.as_int(), 0x12345678); + EXPECT_TRUE(c.is_str()); } { Const c(0xab, 8); EXPECT_TRUE(c.is_str()); EXPECT_EQ(c.as_int(), 0xab); + EXPECT_TRUE(c.is_str()); } { @@ -105,6 +107,7 @@ namespace RTLIL { EXPECT_TRUE(c.is_str()); EXPECT_EQ(c.as_int(), 0x12345678); EXPECT_EQ(c[79], S0); + EXPECT_TRUE(c.is_str()); } { @@ -112,6 +115,14 @@ namespace RTLIL { EXPECT_TRUE(c.is_str()); EXPECT_EQ(c.as_int(), -1); EXPECT_EQ(c[79], S1); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(1 << 24); + EXPECT_TRUE(c.is_str()); + EXPECT_TRUE(c.as_bool()); + EXPECT_TRUE(c.is_str()); } } From 9ad83cc67b0e1a1f1bbf181a64f2a37450410dab Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 03:29:44 +0000 Subject: [PATCH 097/188] Fast path for Const::operator== --- kernel/rtlil.cc | 5 +++++ tests/unit/kernel/rtlilTest.cc | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1228e738f..f0653e91a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -388,6 +388,11 @@ bool RTLIL::Const::operator<(const RTLIL::Const &other) const bool RTLIL::Const::operator ==(const RTLIL::Const &other) const { + if (is_str() && other.is_str()) + return get_str() == other.get_str(); + if (is_bits() && other.is_bits()) + return get_bits() == other.get_bits(); + if (size() != other.size()) return false; diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 99ddf44cc..b2b2e7076 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -204,6 +204,24 @@ namespace RTLIL { EXPECT_EQ(c, Const(0xe, 4)); } + TEST_F(KernelRtlilTest, ConstEqualStr) { + EXPECT_EQ(Const("abc"), Const("abc")); + EXPECT_NE(Const("abc"), Const("def")); + } + + TEST_F(KernelRtlilTest, ConstEqualBits) { + std::vector v1 = {S0, S1}; + std::vector v2 = {S1, S0}; + EXPECT_EQ(Const(v1), Const(v1)); + EXPECT_NE(Const(v1), Const(v2)); + } + + TEST_F(KernelRtlilTest, ConstEqualStrBits) { + std::vector v1 = {S0, S0, S0, S0, S0, S1, S0, S0}; + EXPECT_EQ(Const(v1), Const(" ")); + EXPECT_NE(Const(v1), Const("a")); + } + class WireRtlVsHdlIndexConversionTest : public KernelRtlilTest, public testing::WithParamInterface> From 1a367b907cd5ddb8a0d28457ad9e6f2e3cfb3105 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 03:34:17 +0000 Subject: [PATCH 098/188] Use fast path for 32-bit Const integer constructor in more places --- frontends/json/jsonparse.cc | 2 +- frontends/rtlil/rtlil_parser.y | 2 +- frontends/verific/verific.cc | 8 ++++---- kernel/rtlil.h | 3 ++- techlibs/ice40/ice40_dsp.cc | 2 +- techlibs/quicklogic/ql_bram_merge.cc | 2 +- 6 files changed, 10 insertions(+), 9 deletions(-) diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index f2faa669b..743ac5d9e 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -258,7 +258,7 @@ Const json_parse_attr_param_value(JsonNode *node) } } else if (node->type == 'N') { - value = Const(node->data_number, 32); + value = Const(node->data_number); if (node->data_number < 0) value.flags |= RTLIL::CONST_FLAG_SIGNED; } else diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y index 4f0fb3b97..2b8d7b7ab 100644 --- a/frontends/rtlil/rtlil_parser.y +++ b/frontends/rtlil/rtlil_parser.y @@ -465,7 +465,7 @@ constant: free($1); } | TOK_INT { - $$ = new RTLIL::Const($1, 32); + $$ = new RTLIL::Const($1); } | TOK_STRING { $$ = new RTLIL::Const($1); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9e3436c14..8bb34582e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -267,13 +267,13 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string static const RTLIL::Const extract_vhdl_integer(std::string &val) { char *end; - return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32); + return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10)); } static const RTLIL::Const extract_vhdl_char(std::string &val) { if (val.size()==3 && val[0]=='\"' && val.back()=='\"') - return RTLIL::Const((int)val[1], 32); + return RTLIL::Const((int)val[1]); log_error("Error parsing VHDL character.\n"); } @@ -311,7 +311,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig } else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) && ((decimal = std::strtol(value, &end, 10)), !end[0])) { is_signed = output_signed; - c = RTLIL::Const((int)decimal, 32); + c = RTLIL::Const((int)decimal); } else if (val == "false") { c = RTLIL::Const::from_string("0"); } else if (val == "true") { @@ -344,7 +344,7 @@ static const RTLIL::Const extract_verilog_const(const char *value, bool allow_s } else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) && ((decimal = std::strtol(value, &end, 10)), !end[0])) { is_signed = output_signed; - c = RTLIL::Const((int)decimal, 32); + c = RTLIL::Const((int)decimal); } else if (allow_string) { c = RTLIL::Const(val); } else { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6bb6f1fe1..fca32508d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1112,7 +1112,8 @@ struct RTLIL::SigChunk SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {} SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {} SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {} - SigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {} + SigChunk(int val) /*default width 32*/ : SigChunk(RTLIL::Const(val)) {} + SigChunk(int val, int width) : SigChunk(RTLIL::Const(val, width)) {} SigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {} SigChunk(const RTLIL::SigBit &bit); diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc index 3f00028c3..995cdb97e 100644 --- a/techlibs/ice40/ice40_dsp.cc +++ b/techlibs/ice40/ice40_dsp.cc @@ -82,7 +82,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) SigSpec CD = st.sigCD; if (CD.empty()) - CD = RTLIL::Const(0, 32); + CD = RTLIL::Const(0); else log_assert(GetSize(CD) == 32); diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index bed1ba572..7b99d74e5 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -45,7 +45,7 @@ struct QlBramMergeWorker { { if(cell->type != split_cell_type) continue; if(!cell->hasParam(ID(OPTION_SPLIT))) continue; - if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1)) continue; mergeable_groups[get_key(cell)].insert(cell); } } From 67a274ed1f499cec716f4f9a2f163786a85c62ae Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 03:48:16 +0000 Subject: [PATCH 099/188] Optimize Const::hash_into to hash packed bits efficiently --- kernel/rtlil.cc | 34 ++++++++++++++++++++++++++++++++++ kernel/rtlil.h | 7 +------ tests/unit/kernel/rtlilTest.cc | 12 ++++++++++++ 3 files changed, 47 insertions(+), 6 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f0653e91a..f2ac1dee8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -760,6 +760,40 @@ bool RTLIL::Const::is_onehot(int *pos) const return found; } +Hasher RTLIL::Const::hash_into(Hasher h) const +{ + if (auto str = get_if_str()) + return hashlib::hash_ops::hash_into(*str, h); + + // If the bits are all 0/1, hash packed bits using the string hash. + // Otherwise hash the leading packed bits with the rest of the bits individually. + bitvectype &bv = get_bits(); + int size = GetSize(bv); + std::string packed; + int packed_size = (size + 7) >> 3; + packed.resize(packed_size, 0); + for (int bi = 0; bi < packed_size; ++bi) { + char ch = 0; + int end = std::min((bi + 1)*8, size); + for (int i = bi*8; i < end; ++i) { + RTLIL::State b = bv[i]; + if (b > RTLIL::State::S1) { + // Hash the packed bits we've seen so far, plus the remaining bits. + h = hashlib::hash_ops::hash_into(packed, h); + h = hashlib::hash_ops::hash_into(ch, h); + for (; i < size; ++i) { + h = hashlib::hash_ops::hash_into(bv[i], h); + } + h.eat(size); + return h; + } + ch |= static_cast(b) << (i & 7); + } + packed[packed_size - 1 - bi] = ch; + } + return hashlib::hash_ops::hash_into(packed, h); +} + RTLIL::Const RTLIL::Const::extract(int offset, int len, RTLIL::State padding) const { bitvectype ret_bv; ret_bv.reserve(len); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fca32508d..f4c84dbfa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1052,12 +1052,7 @@ public: resize(width, empty() ? RTLIL::State::Sx : back()); } - [[nodiscard]] Hasher hash_into(Hasher h) const { - h.eat(size()); - for (auto b : *this) - h.eat(b); - return h; - } + [[nodiscard]] Hasher hash_into(Hasher h) const; }; struct RTLIL::AttrObject diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index b2b2e7076..4d8736ea3 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -222,6 +222,18 @@ namespace RTLIL { EXPECT_NE(Const(v1), Const("a")); } + static Hasher::hash_t hash(const Const &c) { + Hasher h; + h = c.hash_into(h); + return h.yield(); + } + + TEST_F(KernelRtlilTest, ConstEqualHashStrBits) { + std::vector v1 = {S0, S0, S0, S0, S0, S1, S0, S0}; + EXPECT_EQ(hash(Const(v1)), hash(Const(" "))); + EXPECT_NE(hash(Const(v1)), hash(Const("a"))); + } + class WireRtlVsHdlIndexConversionTest : public KernelRtlilTest, public testing::WithParamInterface> From f61e3377a93623934f5368f57ad3286050d155c4 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:13:23 +0000 Subject: [PATCH 100/188] Hash strings 8 bytes at a time --- kernel/hashlib.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 92188a220..c95ce1e7b 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -168,8 +168,17 @@ struct hash_ops { } else if constexpr (std::is_pointer_v) { return hash_ops::hash_into((uintptr_t) a, h); } else if constexpr (std::is_same_v) { - for (auto c : a) - h.hash32(c); + int size = a.size(); + int i = 0; + while (i + 8 < size) { + uint64_t v; + memcpy(&v, a.data() + i, 8); + h.hash64(v); + i += 8; + } + uint64_t v = 0; + memcpy(&v, a.data() + i, size - i); + h.hash64(v); return h; } else { return a.hash_into(h); From cb1186aac52a5797e2f5f4ccde3f47b34f4bc7d6 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:40:22 +0000 Subject: [PATCH 101/188] Make Const::as_string work without reducing packed bits to vector --- kernel/rtlil.cc | 19 +++++++++---------- tests/unit/kernel/rtlilTest.cc | 7 +++++++ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f2ac1dee8..7a65a6db6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -542,18 +542,17 @@ std::optional RTLIL::Const::as_int_compress(bool is_signed) const std::string RTLIL::Const::as_string(const char* any) const { - bitvectorize_internal(); - bitvectype& bv = get_bits(); + int sz = size(); std::string ret; - ret.reserve(bv.size()); - for (size_t i = bv.size(); i > 0; i--) - switch (bv[i-1]) { - case S0: ret += "0"; break; - case S1: ret += "1"; break; - case Sx: ret += "x"; break; - case Sz: ret += "z"; break; + ret.reserve(sz); + for (int i = sz - 1; i >= 0; --i) + switch ((*this)[i]) { + case S0: ret.push_back('0'); break; + case S1: ret.push_back('1'); break; + case Sx: ret.push_back('x'); break; + case Sz: ret.push_back('z'); break; case Sa: ret += any; break; - case Sm: ret += "m"; break; + case Sm: ret.push_back('m'); break; } return ret; } diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 4d8736ea3..366d022de 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -124,6 +124,13 @@ namespace RTLIL { EXPECT_TRUE(c.as_bool()); EXPECT_TRUE(c.is_str()); } + + { + Const c(0x2, 8); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.as_string(), "00000010"); + EXPECT_TRUE(c.is_str()); + } } TEST_F(KernelRtlilTest, ConstConstIteratorWorks) { From caaf9a4400e7feb7764120c05a31e57a4c571ff7 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:42:52 +0000 Subject: [PATCH 102/188] Const::decode_string() doesn't need to call bitvectorize --- kernel/rtlil.cc | 1 - tests/unit/kernel/rtlilTest.cc | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7a65a6db6..7530644ec 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -579,7 +579,6 @@ std::string RTLIL::Const::decode_string() const if (auto str = get_if_str()) return *str; - bitvectorize_internal(); bitvectype& bv = get_bits(); const int n = GetSize(bv); const int n_over_8 = n / 8; diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 366d022de..5f8c0dd06 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -131,6 +131,32 @@ namespace RTLIL { EXPECT_EQ(c.as_string(), "00000010"); EXPECT_TRUE(c.is_str()); } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.decode_string(), " "); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_EQ(c.decode_string(), " "); + EXPECT_TRUE(c.is_str()); + } + + { + std::vector v = {S0, S0, S0, S0, S0, S1, S0, S0}; + Const c(v); + EXPECT_EQ(c.decode_string(), " "); + } + + { + std::vector v = {S0, S0, S0, S0, S0, S1, S0, Sx}; + Const c(v); + EXPECT_EQ(c.decode_string(), " "); + } } TEST_F(KernelRtlilTest, ConstConstIteratorWorks) { From 29810f1e7ccb8e934e372d0ec91a987c4c051249 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 04:50:35 +0000 Subject: [PATCH 103/188] Make Const::is_*() functions work on packed bits without decaying to vector --- kernel/rtlil.cc | 44 ++++++++++------ tests/unit/kernel/rtlilTest.cc | 91 ++++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+), 15 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7530644ec..7ced8fba6 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -669,10 +669,17 @@ RTLIL::State RTLIL::Const::const_iterator::operator*() const { bool RTLIL::Const::is_fully_zero() const { - bitvectorize_internal(); - bitvectype& bv = get_bits(); cover("kernel.rtlil.const.is_fully_zero"); + if (auto str = get_if_str()) { + for (char ch : *str) + if (ch != 0) + return false; + return true; + } + + bitvectype& bv = get_bits(); + for (const auto &bit : bv) if (bit != RTLIL::State::S0) return false; @@ -682,10 +689,16 @@ bool RTLIL::Const::is_fully_zero() const bool RTLIL::Const::is_fully_ones() const { - bitvectorize_internal(); - bitvectype& bv = get_bits(); cover("kernel.rtlil.const.is_fully_ones"); + if (auto str = get_if_str()) { + for (char ch : *str) + if (ch != (char)0xff) + return false; + return true; + } + + bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::S1) return false; @@ -697,9 +710,10 @@ bool RTLIL::Const::is_fully_def() const { cover("kernel.rtlil.const.is_fully_def"); - bitvectorize_internal(); - bitvectype& bv = get_bits(); + if (is_str()) + return true; + bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; @@ -711,9 +725,10 @@ bool RTLIL::Const::is_fully_undef() const { cover("kernel.rtlil.const.is_fully_undef"); - bitvectorize_internal(); - bitvectype& bv = get_bits(); + if (auto str = get_if_str()) + return str->empty(); + bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz) return false; @@ -725,9 +740,10 @@ bool RTLIL::Const::is_fully_undef_x_only() const { cover("kernel.rtlil.const.is_fully_undef_x_only"); - bitvectorize_internal(); - bitvectype& bv = get_bits(); + if (auto str = get_if_str()) + return str->empty(); + bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::Sx) return false; @@ -739,12 +755,10 @@ bool RTLIL::Const::is_onehot(int *pos) const { cover("kernel.rtlil.const.is_onehot"); - bitvectorize_internal(); - bitvectype& bv = get_bits(); - bool found = false; - for (int i = 0; i < GetSize(*this); i++) { - auto &bit = bv[i]; + int size = GetSize(*this); + for (int i = 0; i < size; i++) { + State bit = (*this)[i]; if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; if (bit == RTLIL::State::S1) { diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 5f8c0dd06..97cc936de 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -157,6 +157,50 @@ namespace RTLIL { Const c(v); EXPECT_EQ(c.decode_string(), " "); } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_FALSE(c.is_fully_zero()); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_FALSE(c.is_fully_ones()); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_TRUE(c.is_fully_def()); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_FALSE(c.is_fully_undef()); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + EXPECT_FALSE(c.is_fully_undef_x_only()); + EXPECT_TRUE(c.is_str()); + } + + { + Const c(" "); + EXPECT_TRUE(c.is_str()); + int pos; + EXPECT_TRUE(c.is_onehot(&pos)); + EXPECT_EQ(pos, 5); + EXPECT_TRUE(c.is_str()); + } } TEST_F(KernelRtlilTest, ConstConstIteratorWorks) { @@ -267,6 +311,53 @@ namespace RTLIL { EXPECT_NE(hash(Const(v1)), hash(Const("a"))); } + TEST_F(KernelRtlilTest, ConstIsFullyZero) { + EXPECT_TRUE(Const(0, 8).is_fully_zero()); + EXPECT_FALSE(Const(8, 8).is_fully_zero()); + EXPECT_TRUE(Const().is_fully_zero()); + } + + TEST_F(KernelRtlilTest, ConstIsFullyOnes) { + EXPECT_TRUE(Const(0xf, 4).is_fully_ones()); + EXPECT_FALSE(Const(3, 4).is_fully_ones()); + EXPECT_TRUE(Const().is_fully_ones()); + } + + TEST_F(KernelRtlilTest, ConstIsFullyDef) { + EXPECT_TRUE(Const(0xf, 4).is_fully_def()); + std::vector v1 = {S0, Sx}; + EXPECT_FALSE(Const(v1).is_fully_def()); + EXPECT_TRUE(Const().is_fully_def()); + } + + TEST_F(KernelRtlilTest, ConstIsFullyUndef) { + std::vector v1 = {S0, Sx}; + EXPECT_FALSE(Const(v1).is_fully_undef()); + EXPECT_TRUE(Const(Sz, 2).is_fully_undef()); + EXPECT_TRUE(Const().is_fully_undef()); + } + + TEST_F(KernelRtlilTest, ConstIsFullyUndefXOnly) { + std::vector v1 = {Sx, Sz}; + EXPECT_FALSE(Const(v1).is_fully_undef_x_only()); + EXPECT_TRUE(Const(Sx, 2).is_fully_undef_x_only()); + EXPECT_TRUE(Const().is_fully_undef_x_only()); + } + + TEST_F(KernelRtlilTest, ConstIsOnehot) { + int pos; + EXPECT_TRUE(Const(0x80, 8).is_onehot(&pos)); + EXPECT_EQ(pos, 7); + EXPECT_FALSE(Const(0x82, 8).is_onehot(&pos)); + EXPECT_FALSE(Const(0, 8).is_onehot(&pos)); + EXPECT_TRUE(Const(1, 1).is_onehot(&pos)); + EXPECT_EQ(pos, 0); + EXPECT_FALSE(Const(Sx, 1).is_onehot(&pos)); + std::vector v1 = {Sx, S1}; + EXPECT_FALSE(Const(v1).is_onehot(&pos)); + EXPECT_FALSE(Const().is_onehot(&pos)); + } + class WireRtlVsHdlIndexConversionTest : public KernelRtlilTest, public testing::WithParamInterface> From fee2b8992c526fde3a502db2cbd9fb3b614536c8 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 29 Aug 2025 05:56:19 +0000 Subject: [PATCH 104/188] Stop using `mutable` in `Const`. Now that we only call `bitvectorize()` in non-const methods, we can move the casting-away-const to only happen in `bitvectorize()`, which is deprecated so only some plugins (maybe) are using it. This means `const` `Const` methods don't change the underlying data, which means they'll be safe to use from multiple threads if/when we want to do that. --- kernel/rtlil.cc | 36 +++++++++++++++++++++++------------- kernel/rtlil.h | 22 +++++++++++++--------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7ced8fba6..035701cb9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -240,12 +240,22 @@ const pool &RTLIL::builtin_ff_cell_types() { #define check(condition) log_assert(condition && "malformed Const union") -Const::bitvectype& Const::get_bits() const { +const Const::bitvectype& Const::get_bits() const { check(is_bits()); return *get_if_bits(); } -std::string& Const::get_str() const { +const std::string& Const::get_str() const { + check(is_str()); + return *get_if_str(); +} + +Const::bitvectype& Const::get_bits() { + check(is_bits()); + return *get_if_bits(); +} + +std::string& Const::get_str() { check(is_str()); return *get_if_str(); } @@ -431,7 +441,7 @@ bool RTLIL::Const::as_bool() const return false; } - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (size_t i = 0; i < bv.size(); i++) if (bv[i] == State::S1) return true; @@ -448,7 +458,7 @@ int RTLIL::Const::as_int(bool is_signed) const ret |= static_cast((*s)[size - i]) << ((i - 1) * 8); // If is_signed and the string is shorter than 4 bytes then apply sign extension. if (is_signed && size > 0 && size < 4 && ((*s)[0] & 0x80)) - ret |= -1 << size*8; + ret |= UINT32_MAX << size*8; return ret; } @@ -458,7 +468,7 @@ int RTLIL::Const::as_int(bool is_signed) const if (bv[i] == State::S1) ret |= 1 << i; if (is_signed && significant_bits > 0 && significant_bits < 32 && bv.back() == State::S1 ) - ret |= -1 << significant_bits; + ret |= UINT32_MAX << significant_bits; return ret; } @@ -579,7 +589,7 @@ std::string RTLIL::Const::decode_string() const if (auto str = get_if_str()) return *str; - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); const int n = GetSize(bv); const int n_over_8 = n / 8; std::string s; @@ -627,7 +637,7 @@ bool RTLIL::Const::empty() const { } } -void RTLIL::Const::bitvectorize_internal() const { +void RTLIL::Const::bitvectorize_internal() { if (tag == backing_tag::bits) return; @@ -678,7 +688,7 @@ bool RTLIL::Const::is_fully_zero() const return true; } - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::S0) @@ -698,7 +708,7 @@ bool RTLIL::Const::is_fully_ones() const return true; } - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::S1) return false; @@ -713,7 +723,7 @@ bool RTLIL::Const::is_fully_def() const if (is_str()) return true; - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1) return false; @@ -728,7 +738,7 @@ bool RTLIL::Const::is_fully_undef() const if (auto str = get_if_str()) return str->empty(); - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz) return false; @@ -743,7 +753,7 @@ bool RTLIL::Const::is_fully_undef_x_only() const if (auto str = get_if_str()) return str->empty(); - bitvectype& bv = get_bits(); + const bitvectype& bv = get_bits(); for (const auto &bit : bv) if (bit != RTLIL::State::Sx) return false; @@ -779,7 +789,7 @@ Hasher RTLIL::Const::hash_into(Hasher h) const // If the bits are all 0/1, hash packed bits using the string hash. // Otherwise hash the leading packed bits with the rest of the bits individually. - bitvectype &bv = get_bits(); + const bitvectype &bv = get_bits(); int size = GetSize(bv); std::string packed; int packed_size = (size + 7) >> 3; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4c84dbfa..6b4bc0c7d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -822,23 +822,27 @@ private: using bitvectype = std::vector; enum class backing_tag: bool { bits, string }; // Do not access the union or tag even in Const methods unless necessary - mutable backing_tag tag; + backing_tag tag; union { - mutable bitvectype bits_; - mutable std::string str_; + bitvectype bits_; + std::string str_; }; // Use these private utilities instead bool is_bits() const { return tag == backing_tag::bits; } bool is_str() const { return tag == backing_tag::string; } - bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; } - std::string* get_if_str() const { return is_str() ? &str_ : NULL; } + bitvectype* get_if_bits() { return is_bits() ? &bits_ : NULL; } + std::string* get_if_str() { return is_str() ? &str_ : NULL; } + const bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; } + const std::string* get_if_str() const { return is_str() ? &str_ : NULL; } - bitvectype& get_bits() const; - std::string& get_str() const; + bitvectype& get_bits(); + std::string& get_str(); + const bitvectype& get_bits() const; + const std::string& get_str() const; std::vector& bits_internal(); - void bitvectorize_internal() const; + void bitvectorize_internal(); public: Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector()) {} @@ -871,7 +875,7 @@ public: [[deprecated("Don't use direct access to the internal std::vector, that's an implementation detail.")]] std::vector& bits() { return bits_internal(); } [[deprecated("Don't call bitvectorize() directly, it's an implementation detail.")]] - void bitvectorize() const { bitvectorize_internal(); } + void bitvectorize() const { const_cast(this)->bitvectorize_internal(); } bool as_bool() const; From 11b829ba70f61a5c59abae8e4b6feec34000b74f Mon Sep 17 00:00:00 2001 From: rhanqtl Date: Thu, 4 Sep 2025 23:19:11 +0800 Subject: [PATCH 105/188] fix(parse): #5234 adjust width of rhs according to lhs --- kernel/rtlil.cc | 6 +++++- tests/sat/fminit_noexpand.ys | 10 ++++++++++ tests/sat/fminit_seq_width.ys | 17 +++++++++++++++++ 3 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 tests/sat/fminit_noexpand.ys create mode 100644 tests/sat/fminit_seq_width.ys diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 035701cb9..586262f97 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -5974,7 +5974,11 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R } } - return parse(sig, module, str); + if (!parse(sig, module, str)) + return false; + if (sig.width_ > lhs.width_) + sig.remove(lhs.width_, sig.width_ - lhs.width_); + return true; } RTLIL::CaseRule::~CaseRule() diff --git a/tests/sat/fminit_noexpand.ys b/tests/sat/fminit_noexpand.ys new file mode 100644 index 000000000..a271c3c59 --- /dev/null +++ b/tests/sat/fminit_noexpand.ys @@ -0,0 +1,10 @@ +read_verilog -sv < Date: Thu, 28 Aug 2025 18:10:00 +0200 Subject: [PATCH 106/188] write_rtlil: don't sort --- backends/rtlil/rtlil_backend.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index cb17432b1..d7de67bfc 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -456,8 +456,6 @@ struct RTLILBackend : public Backend { } extra_args(f, filename, args, argidx); - design->sort(); - log("Output filename: %s\n", filename); *f << stringf("# Generated by %s\n", yosys_maybe_version()); From d6d1f16c4340279f14a8d752d2af1ce3ec5b1707 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:30 +0200 Subject: [PATCH 107/188] hashlib: add insertion order const iterator --- kernel/hashlib.h | 18 ++++++++++++++---- kernel/utils.h | 11 +++++++++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index c95ce1e7b..ed329bba6 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -569,13 +569,16 @@ public: int index; const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { } public: - typedef std::forward_iterator_tag iterator_category; + typedef std::bidirectional_iterator_tag iterator_category; typedef std::pair value_type; typedef ptrdiff_t difference_type; - typedef std::pair* pointer; - typedef std::pair& reference; + typedef const std::pair* pointer; + typedef const std::pair& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } + const_iterator operator++(int) { const_iterator tmp = *this; index--; return tmp; } + const_iterator operator--() { index++; return *this; } + const_iterator operator--(int) { const_iterator tmp = *this; index++; return tmp; } const_iterator operator+=(int amt) { index -= amt; return *this; } bool operator<(const const_iterator &other) const { return index > other.index; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -609,6 +612,13 @@ public: const std::pair *operator->() const { return &ptr->entries[index].udata; } operator const_iterator() const { return const_iterator(ptr, index); } }; + using reverse_iterator = std::reverse_iterator; + reverse_iterator rbegin() const { + return std::make_reverse_iterator(end()); + } + reverse_iterator rend() const { + return std::make_reverse_iterator(begin()); + } constexpr dict() { @@ -858,7 +868,7 @@ public: const_iterator begin() const { return const_iterator(this, int(entries.size())-1); } const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); } - const_iterator end() const { return const_iterator(nullptr, -1); } + const_iterator end() const { return const_iterator(this, -1); } }; template diff --git a/kernel/utils.h b/kernel/utils.h index 6c9fe36a5..5c739aceb 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -21,6 +21,7 @@ // do not depend on any other components of yosys (except stuff like log_*). #include "kernel/yosys.h" +#include #ifndef UTILS_H #define UTILS_H @@ -276,6 +277,16 @@ inline int ceil_log2(int x) #endif } +template +auto reversed(const T& container) { + struct reverse_view { + const T& cont; + auto begin() const { return cont.rbegin(); } + auto end() const { return cont.rend(); } + }; + return reverse_view{container}; +} + YOSYS_NAMESPACE_END #endif From e11ea42af0e1e3dc1efbfb4f053b268e48b91175 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:21:42 +0200 Subject: [PATCH 108/188] raise_error: whitespace --- passes/tests/raise_error.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc index 7233e78fa..b21ec7d1d 100644 --- a/passes/tests/raise_error.cc +++ b/passes/tests/raise_error.cc @@ -47,7 +47,7 @@ struct RaiseErrorPass : public Pass { extra_args(args, argidx, design, true); RTLIL::NamedObject *err_obj = nullptr; - + for (auto mod : design->all_selected_modules()) { if (mod->has_attribute(ID::raise_error)) { err_obj = mod->clone(); From 68ad52c6ae9b75ccab3681e2bc90ef97269b9cdc Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:03 +0200 Subject: [PATCH 109/188] bugpoint: don't sort --- passes/cmds/bugpoint.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 8432c27fd..897dd8459 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -122,8 +122,6 @@ struct BugpointPass : public Pass { int run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg, string suffix, bool catch_err) { - design->sort(); - string bugpoint_file = "bugpoint-case"; if (suffix.size()) bugpoint_file += stringf(".%.8s", suffix); From 1328a33e829923b544a57d70215b8717c6dbab8a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:35 +0200 Subject: [PATCH 110/188] write_rtlil: dump in insertion order --- backends/rtlil/rtlil_backend.cc | 148 ++++++++++++++------------------ backends/rtlil/rtlil_backend.h | 1 + 2 files changed, 64 insertions(+), 85 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index d7de67bfc..8402d3e3d 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -24,12 +24,23 @@ #include "rtlil_backend.h" #include "kernel/yosys.h" +#include "kernel/utils.h" #include +#include USING_YOSYS_NAMESPACE using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN +void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj) +{ + for (const auto& [name, value] : reversed(obj->attributes)) { + f << stringf("%s" "attribute %s ", indent, name); + dump_const(f, value); + f << stringf("\n"); + } +} + void RTLIL_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint) { if (width < 0) @@ -110,8 +121,8 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo dump_sigchunk(f, sig.as_chunk(), autoint); } else { f << stringf("{ "); - for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) { - dump_sigchunk(f, *it, false); + for (const auto& chunk : reversed(sig.chunks())) { + dump_sigchunk(f, chunk, false); f << stringf(" "); } f << stringf("}"); @@ -120,14 +131,10 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { - for (auto &it : wire->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, wire); if (wire->driverCell_) { f << stringf("%s" "# driver %s %s\n", indent, - wire->driverCell()->name.c_str(), wire->driverPort().c_str()); + wire->driverCell()->name, wire->driverPort()); } f << stringf("%s" "wire ", indent); if (wire->width != 1) @@ -149,11 +156,7 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory) { - for (auto &it : memory->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, memory); f << stringf("%s" "memory ", indent); if (memory->width != 1) f << stringf("width %d ", memory->width); @@ -166,23 +169,19 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell) { - for (auto &it : cell->attributes) { - f << stringf("%s" "attribute %s ", indent, it.first); - dump_const(f, it.second); - f << stringf("\n"); - } + dump_attributes(f, indent, cell); f << stringf("%s" "cell %s %s\n", indent, cell->type, cell->name); - for (auto &it : cell->parameters) { + for (const auto& [name, param] : reversed(cell->parameters)) { f << stringf("%s parameter%s%s %s ", indent, - (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", - (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", - it.first.c_str()); - dump_const(f, it.second); + (param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", + (param.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", + name); + dump_const(f, param); f << stringf("\n"); } - for (auto &it : cell->connections()) { - f << stringf("%s connect %s ", indent, it.first); - dump_sigspec(f, it.second); + for (const auto& [port, sig] : reversed(cell->connections_)) { + f << stringf("%s connect %s ", indent, port); + dump_sigspec(f, sig); f << stringf("\n"); } f << stringf("%s" "end\n", indent); @@ -190,47 +189,38 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs) { - for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) - { + for (const auto& [lhs, rhs] : cs->actions) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, it->first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it->second); + dump_sigspec(f, rhs); f << stringf("\n"); } - for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it) - dump_proc_switch(f, indent, *it); + for (const auto& sw : cs->switches) + dump_proc_switch(f, indent, sw); } void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw) { - for (auto it = sw->attributes.begin(); it != sw->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, sw); f << stringf("%s" "switch ", indent); dump_sigspec(f, sw->signal); f << stringf("\n"); - for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) + for (const auto case_ : sw->cases) { - for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) { - f << stringf("%s attribute %s ", indent, ait->first); - dump_const(f, ait->second); - f << stringf("\n"); - } + dump_attributes(f, indent, case_); f << stringf("%s case ", indent); - for (size_t i = 0; i < (*it)->compare.size(); i++) { + for (size_t i = 0; i < case_->compare.size(); i++) { if (i > 0) f << stringf(" , "); - dump_sigspec(f, (*it)->compare[i]); + dump_sigspec(f, case_->compare[i]); } f << stringf("\n"); - dump_proc_case_body(f, indent + " ", *it); + dump_proc_case_body(f, indent + " ", case_); } f << stringf("%s" "end\n", indent); @@ -253,20 +243,16 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT case RTLIL::STi: f << stringf("init\n"); break; } - for (auto &it: sy->actions) { + for (const auto& [lhs, rhs] : sy->actions) { f << stringf("%s update ", indent); - dump_sigspec(f, it.first); + dump_sigspec(f, lhs); f << stringf(" "); - dump_sigspec(f, it.second); + dump_sigspec(f, rhs); f << stringf("\n"); } for (auto &it: sy->mem_write_actions) { - for (auto it2 = it.attributes.begin(); it2 != it.attributes.end(); ++it2) { - f << stringf("%s attribute %s ", indent, it2->first); - dump_const(f, it2->second); - f << stringf("\n"); - } + dump_attributes(f, indent, &it); f << stringf("%s memwr %s ", indent, it.memid); dump_sigspec(f, it.address); f << stringf(" "); @@ -281,15 +267,11 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc) { - for (auto it = proc->attributes.begin(); it != proc->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, proc); f << stringf("%s" "process %s\n", indent, proc->name); dump_proc_case_body(f, indent + " ", &proc->root_case); - for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it) - dump_proc_sync(f, indent + " ", *it); + for (auto* sync : proc->syncs) + dump_proc_sync(f, indent + " ", sync); f << stringf("%s" "end\n", indent); } @@ -309,11 +291,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_header) { - for (auto it = module->attributes.begin(); it != module->attributes.end(); ++it) { - f << stringf("%s" "attribute %s ", indent, it->first); - dump_const(f, it->second); - f << stringf("\n"); - } + dump_attributes(f, indent, module); f << stringf("%s" "module %s\n", indent, module->name); @@ -335,40 +313,40 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (print_body) { - for (auto it : module->wires()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, wire] : reversed(module->wires_)) + if (!only_selected || design->selected(module, wire)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", it); + dump_wire(f, indent + " ", wire); } - for (auto it : module->memories) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, mem] : reversed(module->memories)) + if (!only_selected || design->selected(module, mem)) { if (only_selected) f << stringf("\n"); - dump_memory(f, indent + " ", it.second); + dump_memory(f, indent + " ", mem); } - for (auto it : module->cells()) - if (!only_selected || design->selected(module, it)) { + for (const auto& [_, cell] : reversed(module->cells_)) + if (!only_selected || design->selected(module, cell)) { if (only_selected) f << stringf("\n"); - dump_cell(f, indent + " ", it); + dump_cell(f, indent + " ", cell); } - for (auto it : module->processes) - if (!only_selected || design->selected(module, it.second)) { + for (const auto& [_, process] : reversed(module->processes)) + if (!only_selected || design->selected(module, process)) { if (only_selected) f << stringf("\n"); - dump_proc(f, indent + " ", it.second); + dump_proc(f, indent + " ", process); } bool first_conn_line = true; - for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { + for (const auto& [lhs, rhs] : module->connections()) { bool show_conn = !only_selected || design->selected_whole_module(module->name); if (!show_conn) { - RTLIL::SigSpec sigs = it->first; - sigs.append(it->second); + RTLIL::SigSpec sigs = lhs; + sigs.append(rhs); for (auto &c : sigs.chunks()) { if (c.wire == NULL || !design->selected(module, c.wire)) continue; @@ -378,7 +356,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (show_conn) { if (only_selected && first_conn_line) f << stringf("\n"); - dump_conn(f, indent + " ", it->first, it->second); + dump_conn(f, indent + " ", lhs, rhs); first_conn_line = false; } } @@ -394,7 +372,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!flag_m) { int count_selected_mods = 0; - for (auto module : design->modules()) { + for (auto* module : design->modules()) { if (design->selected_whole_module(module->name)) flag_m = true; if (design->selected(module)) @@ -410,7 +388,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl f << stringf("autoidx %d\n", autoidx); } - for (auto module : design->modules()) { + for (const auto& [_, module] : reversed(design->modules_)) { if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); @@ -526,7 +504,7 @@ struct DumpPass : public Pass { if (!empty) { rewrite_filename(filename); std::ofstream *ff = new std::ofstream; - ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc); + ff->open(filename, append ? std::ofstream::app : std::ofstream::trunc); if (ff->fail()) { delete ff; log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 35829729c..dd7347def 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -31,6 +31,7 @@ YOSYS_NAMESPACE_BEGIN namespace RTLIL_BACKEND { + void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj); void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); From 118c1890b10f8849f720ad27c817e735f9175f3c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 18:22:59 +0200 Subject: [PATCH 111/188] raise_error: don't rely on module ordering in test --- tests/bugpoint/raise_error.ys | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/bugpoint/raise_error.ys b/tests/bugpoint/raise_error.ys index 8fb10eb96..79127deff 100644 --- a/tests/bugpoint/raise_error.ys +++ b/tests/bugpoint/raise_error.ys @@ -22,34 +22,37 @@ logger -check-expected # raise_error with int exits with status design -load read +setattr -mod -unset raise_error def other +dump bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error -always still uses 'raise_error' attribute if possible design -load read +setattr -mod -unset raise_error def other bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7 select -assert-mod-count 1 =* select -assert-mod-count 1 top # raise_error with string prints message and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other # raise_error with no value exits with 1 design -load read -rename def zzy +setattr -mod -unset raise_error top delete other bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1 select -assert-mod-count 1 =* -select -assert-mod-count 1 zzy +select -assert-mod-count 1 def # raise_error -stderr prints to stderr and exits with 1 design -load read -rename top abc +setattr -mod -unset raise_error top def bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1 select -assert-mod-count 1 =* select -assert-mod-count 1 other From bcc69d5f6ed5c0292c6c7c279cfbf3785358b246 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:19:57 +0200 Subject: [PATCH 112/188] write_rtlil: add -sort to match old behavior --- backends/rtlil/rtlil_backend.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 8402d3e3d..d607be837 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -416,10 +416,14 @@ struct RTLILBackend : public Backend { log(" -selected\n"); log(" only write selected parts of the design.\n"); log("\n"); + log(" -sort\n"); + log(" sort design in-place (used to be default).\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool selected = false; + bool do_sort = false; log_header(design, "Executing RTLIL backend.\n"); @@ -430,12 +434,19 @@ struct RTLILBackend : public Backend { selected = true; continue; } + if (arg == "-sort") { + do_sort = true; + continue; + } break; } extra_args(f, filename, args, argidx); log("Output filename: %s\n", filename); + if (do_sort) + design->sort(); + *f << stringf("# Generated by %s\n", yosys_maybe_version()); RTLIL_BACKEND::dump_design(*f, design, selected, true, false); } From 4215f3c13418e2e3f649e1d6175861a97bdd4701 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:50:15 +0200 Subject: [PATCH 113/188] rtlil: add textual roundtrip test --- Makefile | 1 + tests/rtlil/.gitignore | 2 + tests/rtlil/everything.v | 40 + tests/rtlil/roundtrip-text.ref.il | 283 ++++++ tests/rtlil/roundtrip-text.sh | 30 + tests/rtlil/roundtrip-text.synth.ref.il | 1194 +++++++++++++++++++++++ tests/rtlil/run-test.sh | 4 + 7 files changed, 1554 insertions(+) create mode 100644 tests/rtlil/.gitignore create mode 100644 tests/rtlil/everything.v create mode 100644 tests/rtlil/roundtrip-text.ref.il create mode 100644 tests/rtlil/roundtrip-text.sh create mode 100644 tests/rtlil/roundtrip-text.synth.ref.il create mode 100755 tests/rtlil/run-test.sh diff --git a/Makefile b/Makefile index 281f5a868..51c0015fd 100644 --- a/Makefile +++ b/Makefile @@ -889,6 +889,7 @@ MK_TEST_DIRS += tests/sim MK_TEST_DIRS += tests/svtypes MK_TEST_DIRS += tests/techmap MK_TEST_DIRS += tests/various +MK_TEST_DIRS += tests/rtlil ifeq ($(ENABLE_VERIFIC),1) ifneq ($(YOSYS_NOVERIFIC),1) MK_TEST_DIRS += tests/verific diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore new file mode 100644 index 000000000..e1661c060 --- /dev/null +++ b/tests/rtlil/.gitignore @@ -0,0 +1,2 @@ +*.tmp.il +*.tmp.il.bak \ No newline at end of file diff --git a/tests/rtlil/everything.v b/tests/rtlil/everything.v new file mode 100644 index 000000000..666d630c2 --- /dev/null +++ b/tests/rtlil/everything.v @@ -0,0 +1,40 @@ +module alu( + input clk, + input [7:0] A, + input [7:0] B, + input [3:0] operation, + output reg [7:0] result, + output reg CF, + output reg ZF, + output reg SF +); + + localparam ALU_OP_ADD = 4'b0000; + localparam ALU_OP_SUB = 4'b0001; + + reg [8:0] tmp; + + always @(posedge clk) + begin + case (operation) + ALU_OP_ADD : + tmp = A + B; + ALU_OP_SUB : + tmp = A - B; + endcase + + CF <= tmp[8]; + ZF <= tmp[7:0] == 0; + SF <= tmp[7]; + + result <= tmp[7:0]; + end +endmodule + +module foo( + input [7:0] a, input [7:0] b, output [7:0] y +); + wire [7:0] bb; + assign b = bb; + assign y = a + bb; +endmodule diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il new file mode 100644 index 000000000..d67cb3626 --- /dev/null +++ b/tests/rtlil/roundtrip-text.ref.il @@ -0,0 +1,283 @@ +autoidx 15 +attribute \src "everything.v:1.1-32.10" +attribute \cells_not_processed 1 +module \alu + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:27.9-27.22" + cell $eq $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A $1\tmp[8:0] [7:0] + connect \B 0 + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:17.2-31.5" + process $proc$everything.v:17$1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp[8:0] $1\tmp[8:0] + assign $0\CF[0:0] $1\tmp[8:0] [8] + assign $0\ZF[0:0] $eq$everything.v:27$4_Y + assign $0\SF[0:0] $1\tmp[8:0] [7] + assign $0\result[7:0] $1\tmp[8:0] [7:0] + attribute \src "everything.v:19.3-24.10" + switch \operation + attribute \src "everything.v:19.19-19.19" + case 4'0000 + assign { } { } + assign $1\tmp[8:0] $add$everything.v:21$2_Y + attribute \src "everything.v:21.17-21.17" + case 4'0001 + assign { } { } + assign $1\tmp[8:0] $sub$everything.v:23$3_Y + case + assign $1\tmp[8:0] \tmp + end + sync posedge \clk + update \result $0\result[7:0] + update \CF $0\CF[0:0] + update \ZF $0\ZF[0:0] + update \SF $0\SF[0:0] + update \tmp $0\tmp[8:0] + end +end +attribute \src "everything.v:34.1-40.10" +attribute \cells_not_processed 1 +module \foo + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:39.16-39.22" + wire width 8 $add$everything.v:39$5_Y + attribute \src "everything.v:39.16-39.22" + cell $add $add$everything.v:39$5 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \a + connect \B \bb + connect \Y $add$everything.v:39$5_Y + end + connect \b \bb + connect \y $add$everything.v:39$5_Y +end +attribute \cells_not_processed 1 +attribute \src "everything.v:1.1-32.10" +module \zzz + attribute \src "everything.v:27.9-27.22" + wire $eq$everything.v:27$4_Y + attribute \src "everything.v:23.11-23.16" + wire width 9 $sub$everything.v:23$3_Y + attribute \src "everything.v:21.11-21.16" + wire width 9 $add$everything.v:21$2_Y + attribute \src "everything.v:17.2-31.5" + wire width 9 $1\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire width 9 $0\tmp[8:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + wire $procmux$8_CMP + wire width 9 $procmux$7_Y + wire $procmux$9_CMP + attribute \src "everything.v:27.9-27.22" + cell $logic_not $eq$everything.v:27$4 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 8 + connect \A $1\tmp[8:0] [7:0] + connect \Y $eq$everything.v:27$4_Y + end + attribute \src "everything.v:23.11-23.16" + cell $sub $sub$everything.v:23$3 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $sub$everything.v:23$3_Y + end + attribute \src "everything.v:21.11-21.16" + cell $add $add$everything.v:21$2 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 9 + connect \A \A + connect \B \B + connect \Y $add$everything.v:21$2_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $eq $procmux$8_CMP0 + parameter \A_SIGNED 0 + parameter \B_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 4'0001 + connect \Y $procmux$8_CMP + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $pmux $procmux$7 + parameter \WIDTH 9 + parameter \S_WIDTH 2 + connect \A \tmp + connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y } + connect \S { $procmux$9_CMP $procmux$8_CMP } + connect \Y $procmux$7_Y + end + attribute \src "everything.v:19.3-24.10" + attribute \full_case 1 + cell $logic_not $procmux$9_CMP0 + parameter \A_SIGNED 0 + parameter \Y_WIDTH 1 + parameter \A_WIDTH 4 + connect \A \operation + connect \Y $procmux$9_CMP + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$10 + parameter \WIDTH 8 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7:0] + connect \Q \result + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$11 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [8] + connect \Q \CF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$12 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $eq$everything.v:27$4_Y + connect \Q \ZF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$13 + parameter \WIDTH 1 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y [7] + connect \Q \SF + connect \CLK \clk + end + attribute \src "everything.v:17.2-31.5" + cell $dff $procdff$14 + parameter \WIDTH 9 + parameter \CLK_POLARITY 1'1 + connect \D $procmux$7_Y + connect \Q \tmp + connect \CLK \clk + end + connect $0\result[7:0] $1\tmp[8:0] [7:0] + connect $0\SF[0:0] $1\tmp[8:0] [7] + connect $0\ZF[0:0] $eq$everything.v:27$4_Y + connect $0\CF[0:0] $1\tmp[8:0] [8] + connect $0\tmp[8:0] $1\tmp[8:0] + connect $1\tmp[8:0] $procmux$7_Y +end diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh new file mode 100644 index 000000000..7dd0327ca --- /dev/null +++ b/tests/rtlil/roundtrip-text.sh @@ -0,0 +1,30 @@ +set -euo pipefail +YS=../../yosys + +# write_rtlil and dump are equivalent +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il +sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +# Trim first line ("Generated by Yosys ...") +tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il + +# Loading and writing it out again doesn't change the RTLIL +$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il +tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il + +# Hashing differences don't change the RTLIL +$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il +tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il +diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il + +echo "Without ABC, we don't get any irreproducibility and can pin that" +echo "Has this test case started failing for you? Consider updating the reference" +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" +sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il +tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il +diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il new file mode 100644 index 000000000..04b27b1c1 --- /dev/null +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -0,0 +1,1194 @@ +autoidx 511 +attribute \src "everything.v:34.1-40.10" +module \foo + attribute \src "everything.v:35.48-35.49" + wire width 8 output 3 \y + attribute \src "everything.v:37.16-37.18" + wire width 8 \bb + attribute \src "everything.v:35.32-35.33" + wire width 8 input 2 \b + attribute \src "everything.v:35.17-35.18" + wire width 8 input 1 \a + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.X + attribute \unused_bits "7" + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 + connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 + connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] + connect \B \b [7] + connect \A \a [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] + connect \B \b [6] + connect \A \a [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] + connect \B \b [5] + connect \A \a [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] + connect \B \b [4] + connect \A \a [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] + connect \B \b [3] + connect \A \a [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] + connect \B \b [2] + connect \A \a [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 + connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] + connect \B \b [1] + connect \A \a [1] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 + connect \Y \y [0] + connect \B \b [0] + connect \A \a [0] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 + connect \Y \y [7] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 + connect \Y \y [6] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 + connect \Y \y [5] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 + connect \Y \y [4] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 + connect \Y \y [3] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 + connect \Y \y [2] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] + end + attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 + connect \Y \y [1] + connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] + end + connect $auto$alumacc.cc:495:replace_alu$21.X [0] \y [0] + connect $auto$alumacc.cc:495:replace_alu$21.lcu.G [0] $auto$alumacc.cc:495:replace_alu$21.CO [0] + connect \bb \b +end +attribute \src "everything.v:1.1-32.10" +module \alu + attribute \src "everything.v:15.12-15.15" + wire width 9 \tmp + attribute \src "everything.v:6.19-6.25" + wire width 8 output 5 \result + attribute \src "everything.v:5.14-5.23" + wire width 4 input 4 \operation + attribute \src "everything.v:2.8-2.11" + wire input 1 \clk + attribute \src "everything.v:8.13-8.15" + wire output 7 \ZF + attribute \src "everything.v:9.13-9.15" + wire output 8 \SF + attribute \src "everything.v:7.13-7.15" + wire output 6 \CF + attribute \src "everything.v:4.14-4.15" + wire width 8 input 3 \B + attribute \src "everything.v:3.14-3.15" + wire width 8 input 2 \A + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y + attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + wire $procmux$9_CMP + wire $procmux$8_CMP + wire $auto$simplemap.cc:254:simplemap_eqne$247 + wire $auto$simplemap.cc:166:logic_reduce$268 + wire width 2 $auto$simplemap.cc:166:logic_reduce$265 + wire $auto$simplemap.cc:166:logic_reduce$235 + wire width 2 $auto$simplemap.cc:166:logic_reduce$232 + wire width 4 $auto$simplemap.cc:166:logic_reduce$227 + wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 + wire $auto$rtlil.cc:3196:NotGate$497 + wire $auto$opt_dff.cc:247:make_patterns_logic$505 + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.X + attribute \unused_bits "8" + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \force_downto 1 + wire width 9 $auto$alumacc.cc:495:replace_alu$18.B + attribute \src "everything.v:17.2-31.5" + wire width 8 $0\result[7:0] + attribute \src "everything.v:17.2-31.5" + wire $0\ZF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\SF[0:0] + attribute \src "everything.v:17.2-31.5" + wire $0\CF[0:0] + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 + connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 + connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A \A [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A \A [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A \A [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A \A [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A \A [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A \A [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A \A [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 + connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] + connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \A [0] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] + connect \A \B [7] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] + connect \A \B [6] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] + connect \A \B [5] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] + connect \A \B [4] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] + connect \A \B [3] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] + connect \A \B [2] + end + attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] + connect \A \B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] + connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] + end + attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 + connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] + connect \A \B [0] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$299 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [8] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A 1'0 + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$298 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [7] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] + connect \A \B [7] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$297 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [6] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] + connect \A \B [6] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$296 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [5] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] + connect \A \B [5] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$295 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [4] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] + connect \A \B [4] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$294 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [3] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] + connect \A \B [3] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$293 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [2] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] + connect \A \B [2] + end + attribute \src 0'x + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$292 + connect \Y $auto$alumacc.cc:495:replace_alu$18.B [1] + connect \S $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] + connect \A \B [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$264 + connect \Y $0\CF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [8] + connect \A 1'x + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$263 + connect \Y $0\SF[0:0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [7] + connect \A \tmp [7] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$262 + connect \Y $0\result[7:0] [6] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [6] + connect \A \tmp [6] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$261 + connect \Y $0\result[7:0] [5] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [5] + connect \A \tmp [5] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$260 + connect \Y $0\result[7:0] [4] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [4] + connect \A \tmp [4] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$259 + connect \Y $0\result[7:0] [3] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [3] + connect \A \tmp [3] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$258 + connect \Y $0\result[7:0] [2] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [2] + connect \A \tmp [2] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$257 + connect \Y $0\result[7:0] [1] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [1] + connect \A \tmp [1] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$256 + connect \Y $0\result[7:0] [0] + connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A \tmp [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$270 + connect \Y $procmux$9_CMP + connect \A $auto$simplemap.cc:166:logic_reduce$268 + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$255 + connect \Y $procmux$8_CMP + connect \A $auto$simplemap.cc:254:simplemap_eqne$247 + end + attribute \src "everything.v:27.9-27.22" + cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$237 + connect \Y $0\ZF[0:0] + connect \A $auto$simplemap.cc:166:logic_reduce$235 + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$269 + connect \Y $auto$simplemap.cc:166:logic_reduce$268 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$265 [0] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$267 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \B \operation [3] + connect \A \operation [2] + end + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$266 + connect \Y $auto$simplemap.cc:166:logic_reduce$265 [0] + connect \B \operation [1] + connect \A \operation [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$236 + connect \Y $auto$simplemap.cc:166:logic_reduce$235 + connect \B $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$232 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$234 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [1] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$233 + connect \Y $auto$simplemap.cc:166:logic_reduce$232 [0] + connect \B $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \A $auto$simplemap.cc:166:logic_reduce$227 [0] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$231 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [3] + connect \B $0\SF[0:0] + connect \A $0\result[7:0] [6] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$230 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [2] + connect \B $0\result[7:0] [5] + connect \A $0\result[7:0] [4] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$229 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [1] + connect \B $0\result[7:0] [3] + connect \A $0\result[7:0] [2] + end + attribute \src "everything.v:27.9-27.22" + cell $_OR_ $auto$simplemap.cc:175:logic_reduce$228 + connect \Y $auto$simplemap.cc:166:logic_reduce$227 [0] + connect \B $0\result[7:0] [1] + connect \A $0\result[7:0] [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$253 + connect \Y $auto$simplemap.cc:254:simplemap_eqne$247 + connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect \A $auto$simplemap.cc:125:simplemap_reduce$249 [0] + end + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$250 + connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [0] + connect \B \operation [1] + connect \A $auto$rtlil.cc:3196:NotGate$497 + end + attribute \src 0'x + cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$226 + connect \Y $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \B $procmux$9_CMP + connect \A $procmux$8_CMP + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$502 + connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] + connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$500 + connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [0] + connect \A $auto$alumacc.cc:495:replace_alu$18.X [0] + end + cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$496 + connect \Y $auto$rtlil.cc:3196:NotGate$497 + connect \A \operation [0] + end + attribute \src "everything.v:17.2-31.5" + cell $_DFFE_PP_ $auto$ff.cc:266:slice$504 + connect \Q \CF + connect \E $auto$opt_dff.cc:247:make_patterns_logic$505 + connect \D $0\CF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$289 + connect \Q \tmp [7] + connect \D $0\SF[0:0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$288 + connect \Q \tmp [6] + connect \D $0\result[7:0] [6] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$287 + connect \Q \tmp [5] + connect \D $0\result[7:0] [5] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$286 + connect \Q \tmp [4] + connect \D $0\result[7:0] [4] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$285 + connect \Q \tmp [3] + connect \D $0\result[7:0] [3] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$284 + connect \Q \tmp [2] + connect \D $0\result[7:0] [2] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$283 + connect \Q \tmp [1] + connect \D $0\result[7:0] [1] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$282 + connect \Q \tmp [0] + connect \D $0\result[7:0] [0] + connect \C \clk + end + attribute \src "everything.v:17.2-31.5" + cell $_DFF_P_ $auto$ff.cc:266:slice$280 + connect \Q \ZF + connect \D $0\ZF[0:0] + connect \C \clk + end + connect $0\result[7:0] [7] $0\SF[0:0] + connect $auto$alumacc.cc:495:replace_alu$18.B [0] \B [0] + connect $auto$alumacc.cc:495:replace_alu$18.X [8] $auto$alumacc.cc:495:replace_alu$18.BB [8] + connect $auto$alumacc.cc:495:replace_alu$18.lcu.G [8] 1'0 + connect $auto$simplemap.cc:166:logic_reduce$265 [1] $auto$simplemap.cc:125:simplemap_reduce$249 [1] + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [8] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [0] } { 1'1 $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [7] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [0] } { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] $auto$alumacc.cc:495:replace_alu$18.BB [0] } + connect $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [0] \B [0] + connect \SF \tmp [7] + connect \result \tmp [7:0] + connect \tmp [8] \CF +end diff --git a/tests/rtlil/run-test.sh b/tests/rtlil/run-test.sh new file mode 100755 index 000000000..70b282a9a --- /dev/null +++ b/tests/rtlil/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../gen-tests-makefile.sh +generate_mk --bash From fdbdd193c1245a4fc3ecbf70bac26d18a11e3b75 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 19:56:28 +0200 Subject: [PATCH 114/188] rtlil: add roundtrip test for design -stash and design -save, fix #5321 --- kernel/rtlil.cc | 1 + tests/rtlil/roundtrip-design.sh | 8 ++++++++ tests/rtlil/roundtrip-text.ref.il | 6 +++--- 3 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 tests/rtlil/roundtrip-design.sh diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 035701cb9..050fc6bd1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -5993,6 +5993,7 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule; new_caserule->compare = compare; new_caserule->actions = actions; + new_caserule->attributes = attributes; for (auto &it : switches) new_caserule->switches.push_back(it->clone()); return new_caserule; diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh new file mode 100644 index 000000000..beacddd8f --- /dev/null +++ b/tests/rtlil/roundtrip-design.sh @@ -0,0 +1,8 @@ +set -euo pipefail +YS=../../yosys + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" +diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il + +$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" +diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il index d67cb3626..cc45f53dd 100644 --- a/tests/rtlil/roundtrip-text.ref.il +++ b/tests/rtlil/roundtrip-text.ref.il @@ -203,7 +203,7 @@ module \zzz connect \B \B connect \Y $add$everything.v:21$2_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $eq $procmux$8_CMP0 parameter \A_SIGNED 0 @@ -215,7 +215,7 @@ module \zzz connect \B 4'0001 connect \Y $procmux$8_CMP end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" attribute \full_case 1 cell $pmux $procmux$7 parameter \WIDTH 9 @@ -225,7 +225,7 @@ module \zzz connect \S { $procmux$9_CMP $procmux$8_CMP } connect \Y $procmux$7_Y end - attribute \src "everything.v:19.3-24.10" + attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" attribute \full_case 1 cell $logic_not $procmux$9_CMP0 parameter \A_SIGNED 0 From 70e681ba7ddcb3e1ee8fb6eb748252a8c63f6148 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:36:31 +0200 Subject: [PATCH 115/188] rtlil: move test temporary files to temp directory --- tests/rtlil/.gitignore | 3 +-- tests/rtlil/roundtrip-design.sh | 10 +++++---- tests/rtlil/roundtrip-text.sh | 38 +++++++++++++++++---------------- 3 files changed, 27 insertions(+), 24 deletions(-) diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore index e1661c060..abe251a76 100644 --- a/tests/rtlil/.gitignore +++ b/tests/rtlil/.gitignore @@ -1,2 +1 @@ -*.tmp.il -*.tmp.il.bak \ No newline at end of file +/temp \ No newline at end of file diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh index beacddd8f..018e363c7 100644 --- a/tests/rtlil/roundtrip-design.sh +++ b/tests/rtlil/roundtrip-design.sh @@ -1,8 +1,10 @@ set -euo pipefail YS=../../yosys -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il" -diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il +mkdir -p temp -$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il" -diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" +diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il + +$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" +diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 7dd0327ca..45db7ee72 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -1,30 +1,32 @@ set -euo pipefail YS=../../yosys +mkdir -p temp + # write_rtlil and dump are equivalent -$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.write.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.dump.tmp.il -sed '/^$/d' -i.bak roundtrip-text.write.tmp.il +$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" +sed '/^$/d' -i.bak temp/roundtrip-text.dump.il +sed '/^$/d' -i.bak temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") -tail -n +2 roundtrip-text.write.tmp.il > roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.write-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.ref.il +tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il +diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL -$YS -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload.tmp.il -tail -n +2 roundtrip-text.reload.tmp.il > roundtrip-text.reload-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-nogen.tmp.il +$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL -$YS --hash-seed=2345678 -p "read_rtlil roundtrip-text.dump.tmp.il; write_rtlil roundtrip-text.reload-hash.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.reload-hash.tmp.il -tail -n +2 roundtrip-text.reload-hash.tmp.il > roundtrip-text.reload-hash-nogen.tmp.il -diff roundtrip-text.dump.tmp.il roundtrip-text.reload-hash-nogen.tmp.il +$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" +sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il +diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil roundtrip-text.synth.tmp.il" -sed '/^$/d' -i.bak roundtrip-text.synth.tmp.il -tail -n +2 roundtrip-text.synth.tmp.il > roundtrip-text.synth-nogen.tmp.il -diff roundtrip-text.synth-nogen.tmp.il roundtrip-text.synth.ref.il +$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il +diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il From 175e024033e06f1696a52488e33811b194c9c1b3 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 2 Sep 2025 20:43:52 +0200 Subject: [PATCH 116/188] functional: in test, rely less on wreduce doing a perfect job --- tests/functional/test_functional.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 7a09966d8..d4ebc3484 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") From 73747f6928591a93c723beec1060bd8f1a85cf56 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:57:17 +0200 Subject: [PATCH 117/188] read_verilog: add -relativeshare for synthesis reproducibility testing --- frontends/verilog/verilog_frontend.cc | 17 +++++++++++++++ passes/techmap/techmap.cc | 9 ++++++++ techlibs/common/synth.cc | 30 ++++++++++++++++++++------- techlibs/fabulous/synth_fabulous.cc | 2 +- tests/functional/test_functional.py | 4 ++-- 5 files changed, 51 insertions(+), 11 deletions(-) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 231891271..0b5e93a19 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -229,6 +229,10 @@ struct VerilogFrontend : public Frontend { log(" add 'dir' to the directories which are used when searching include\n"); log(" files\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The command 'verilog_defaults' can be used to register default options for\n"); log("subsequent calls to 'read_verilog'.\n"); log("\n"); @@ -273,6 +277,7 @@ struct VerilogFrontend : public Frontend { bool flag_nowb = false; bool flag_nosynthesis = false; bool flag_yydebug = false; + bool flag_relative_share = false; define_map_t defines_map; std::list include_dirs; @@ -450,6 +455,11 @@ struct VerilogFrontend : public Frontend { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } + if (arg == "-relativeshare") { + flag_relative_share = true; + log_experimental("read_verilog -relativeshare"); + continue; + } if (arg == "-D" && argidx+1 < args.size()) { std::string name = args[++argidx], value; size_t equal = name.find('='); @@ -490,6 +500,13 @@ struct VerilogFrontend : public Frontend { log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); + log("verilog frontend filename %s\n", filename.c_str()); + if (flag_relative_share) { + auto share_path = proc_share_dirname(); + if (filename.substr(0, share_path.length()) == share_path) + filename = std::string("+/") + filename.substr(share_path.length()); + log("new filename %s\n", filename.c_str()); + } AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv; std::string code_after_preproc; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 30b8e17ab..281a8795a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1032,6 +1032,10 @@ struct TechmapPass : public Pass { log(" -dont_map \n"); log(" leave the given cell type unmapped by ignoring any mapping rules for it\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); log("the module name will be used to match the cell. Multiple space-separated cell\n"); @@ -1185,6 +1189,11 @@ struct TechmapPass : public Pass { verilog_frontend += " -I " + args[++argidx]; continue; } + if (args[argidx] == "-relativeshare") { + verilog_frontend += " -relativeshare"; + log_experimental("techmap -relativeshare"); + continue; + } if (args[argidx] == "-assert") { worker.assert_mode = true; continue; diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 9c85fbbc7..0dbb7cbec 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -98,13 +98,17 @@ struct SynthPass : public ScriptPass { log(" mapping library in the `techmap` step. this option can be\n"); log(" repeated.\n"); log("\n"); + log(" -relativeshare\n"); + log(" use paths relative to share directory for source locations\n"); + log(" where possible (experimental).\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share; int lut; std::vector techmap_maps; @@ -124,6 +128,7 @@ struct SynthPass : public ScriptPass { flowmap = false; booth = false; hieropt = false; + relative_share = false; abc = "abc"; techmap_maps.clear(); } @@ -211,6 +216,11 @@ struct SynthPass : public ScriptPass { hieropt = true; continue; } + if (args[argidx] == "-relativeshare") { + relative_share = true; + log_experimental("synth -relativeshare"); + continue; + } break; } extra_args(args, argidx, design); @@ -239,6 +249,10 @@ struct SynthPass : public ScriptPass { else hieropt_flag = hieropt ? " -hier" : ""; + std::string techmap_cmd = "techmap"; + if (relative_share) + techmap_cmd += " -relativeshare"; + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); @@ -268,9 +282,9 @@ struct SynthPass : public ScriptPass { run("peepopt"); run("opt_clean"); if (help_mode) - run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); + run(techmap_cmd + " -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) - run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", techmap_cmd, lut)); if (booth || help_mode) run("booth", " (if -booth)"); if (!noalumacc) @@ -287,22 +301,22 @@ struct SynthPass : public ScriptPass { run("memory_map"); run("opt -full"); if (help_mode) { - run("techmap", " (unless -extra-map)"); - run("techmap -map +/techmap.v -map ", " (if -extra-map)"); + run(techmap_cmd, " (unless -extra-map)"); + run(techmap_cmd + " -map +/techmap.v -map ", " (if -extra-map)"); } else { std::string techmap_opts; if (!techmap_maps.empty()) techmap_opts += " -map +/techmap.v"; for (auto fn : techmap_maps) techmap_opts += stringf(" -map %s", fn); - run("techmap" + techmap_opts); + run(techmap_cmd + techmap_opts); } if (help_mode) { - run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); + run(techmap_cmd + " -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); run("flowmap -maxlut K", " (if -flowmap and -lut)"); } else if (noabc && lut) { - run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); + run(stringf("%s -map +/gate2lut.v -D LUT_WIDTH=%d", techmap_cmd, lut)); run("clean; opt_lut"); } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0e6553fa1..60f2a6816 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); log(" times).\n"); log("\n"); - log(" -extra-map \n"); + log(" -extra-map \n"); log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index d4ebc3484..e4c78a1fb 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -91,4 +91,4 @@ def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl - yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic") + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic") From 7e6126f7533c313b61dada458764c6d822e7f3ca Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 01:58:08 +0200 Subject: [PATCH 118/188] rtlil: fix roundtrip test by eliminating absolute paths from src attributes with -relativeshare --- tests/rtlil/roundtrip-text.sh | 2 +- tests/rtlil/roundtrip-text.synth.ref.il | 562 ++++++++++++------------ 2 files changed, 282 insertions(+), 282 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 45db7ee72..c475a9d9a 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -26,7 +26,7 @@ diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -noabc; write_rtlil temp/roundtrip-text.synth.il" +$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" sed '/^$/d' -i.bak temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il index 04b27b1c1..ab48affc6 100644 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ b/tests/rtlil/roundtrip-text.synth.ref.il @@ -9,276 +9,276 @@ module \foo wire width 8 input 2 \b attribute \src "everything.v:35.17-35.18" wire width 8 input 1 \a - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.X attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$150_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$147_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$173_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$170_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$167_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$164_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$151_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$155_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$148_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$149_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$146_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$143_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] connect \B \b [7] connect \A \a [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] connect \B \b [6] connect \A \a [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] connect \B \b [5] connect \A \a [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] connect \B \b [4] connect \A \a [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] connect \B \b [3] connect \A \a [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] connect \B \b [2] connect \A \a [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] connect \B \b [1] connect \A \a [1] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 connect \Y \y [0] connect \B \b [0] connect \A \a [0] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 connect \Y \y [7] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 connect \Y \y [6] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 connect \Y \y [5] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 connect \Y \y [4] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 connect \Y \y [3] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 connect \Y \y [2] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] end - attribute \src "everything.v:39.16-39.22|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 connect \Y \y [1] connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] @@ -308,61 +308,61 @@ module \alu wire width 8 input 3 \B attribute \src "everything.v:3.14-3.15" wire width 8 input 2 \A - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y + attribute \src "+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y - attribute \src "/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" + wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y wire $procmux$9_CMP wire $procmux$8_CMP wire $auto$simplemap.cc:254:simplemap_eqne$247 @@ -374,23 +374,23 @@ module \alu wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 wire $auto$rtlil.cc:3196:NotGate$497 wire $auto$opt_dff.cc:247:make_patterns_logic$505 - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:214.23-214.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.26-270.27" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:270.23-270.24" + attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.X attribute \unused_bits "8" - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:274.23-274.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.21-279.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:268.22-268.23" + attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" attribute \force_downto 1 wire width 9 $auto$alumacc.cc:495:replace_alu$18.B attribute \src "everything.v:17.2-31.5" @@ -401,496 +401,496 @@ module \alu wire $0\SF[0:0] attribute \src "everything.v:17.2-31.5" wire $0\CF[0:0] - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.12-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$347_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$341_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$335_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.12-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:231.10-231.28" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$361_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$358_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$355_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:248.19-248.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:248$352_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$339_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:241.12-241.34" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$349_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$348_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$346_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$/home/emil/pulls/yosys/share/techmap.v:240$338_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$342_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y + connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$343_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:241$336_Y + connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$340_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$337_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$334_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.27-286.69|/home/emil/pulls/yosys/share/techmap.v:240.19-240.41" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$/home/emil/pulls/yosys/share/techmap.v:240$331_Y + connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:286.42-286.49" + attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A \A [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A \A [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A \A [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A \A [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A \A [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A \A [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A \A [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:288.13-288.20" + attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \A [0] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:289.13-289.25" + attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] connect \A \B [7] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] connect \A \B [6] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] connect \A \B [5] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] connect \A \B [4] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] connect \A \B [3] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] connect \A \B [2] end - attribute \src "/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] connect \A \B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] end - attribute \src "everything.v:23.11-23.16|/home/emil/pulls/yosys/share/techmap.v:279.31-279.37" + attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] connect \A \B [0] From 85bcdee23248b258f164e0cf3dad5afc4bd81199 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 3 Sep 2025 15:42:57 +0200 Subject: [PATCH 119/188] rtlil: fix roundtrip test on macOS due to sed non-POSIX non-sense --- tests/rtlil/roundtrip-text.sh | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index c475a9d9a..7a979879c 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -3,10 +3,17 @@ YS=../../yosys mkdir -p temp +# non-POSIX sed -i inconsistency workaround +remove_empty_lines() { + local file="$1" + sed '/^$/d' "$file" > temp/tmp + mv temp/tmp "$file" +} + # write_rtlil and dump are equivalent $YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" -sed '/^$/d' -i.bak temp/roundtrip-text.dump.il -sed '/^$/d' -i.bak temp/roundtrip-text.write.il +remove_empty_lines temp/roundtrip-text.dump.il +remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il @@ -14,19 +21,19 @@ diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL $YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload.il +remove_empty_lines temp/roundtrip-text.reload.il tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL $YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" -sed '/^$/d' -i.bak temp/roundtrip-text.reload-hash.il +remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il echo "Without ABC, we don't get any irreproducibility and can pin that" echo "Has this test case started failing for you? Consider updating the reference" $YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" -sed '/^$/d' -i.bak temp/roundtrip-text.synth.il +remove_empty_lines temp/roundtrip-text.synth.il tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il From 5ac6858f26cef9bf49c8434e7fc8208530e33dba Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 22:59:08 +0000 Subject: [PATCH 120/188] Remove .c_str() from log_cmd_error() and log_file_error() parameters --- backends/aiger2/aiger.cc | 2 +- backends/cxxrtl/cxxrtl_backend.cc | 4 +-- frontends/ast/ast.cc | 2 +- frontends/ast/genrtlil.cc | 4 +-- frontends/ast/simplify.cc | 2 +- frontends/rpc/rpc_frontend.cc | 14 ++++---- frontends/verific/verific.cc | 16 ++++----- frontends/verilog/const2ast.cc | 2 +- frontends/verilog/preproc.cc | 2 +- kernel/fmt.cc | 14 ++++---- kernel/gzip.cc | 6 ++-- kernel/register.cc | 10 +++--- passes/cmds/abstract.cc | 4 +-- passes/cmds/add.cc | 2 +- passes/cmds/connect.cc | 10 +++--- passes/cmds/connwrappers.cc | 4 +-- passes/cmds/copy.cc | 4 +-- passes/cmds/cover.cc | 2 +- passes/cmds/design.cc | 8 ++--- passes/cmds/exec.cc | 8 ++--- passes/cmds/glift.cc | 2 +- passes/cmds/logger.cc | 8 ++--- passes/cmds/plugin.cc | 4 +-- passes/cmds/rename.cc | 6 ++-- passes/cmds/select.cc | 14 ++++---- passes/cmds/setattr.cc | 2 +- passes/cmds/setenv.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/stat.cc | 4 +-- passes/cmds/tee.cc | 2 +- passes/cmds/viz.cc | 2 +- passes/equiv/equiv_add.cc | 8 ++--- passes/equiv/equiv_make.cc | 14 ++++---- passes/hierarchy/hierarchy.cc | 6 ++-- passes/hierarchy/submod.cc | 2 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_lut_ins.cc | 2 +- passes/pmgen/test_pmgen.cc | 2 +- passes/sat/eval.cc | 16 ++++----- passes/sat/miter.cc | 14 ++++---- passes/sat/mutate.cc | 2 +- passes/sat/qbfsat.cc | 8 ++--- passes/sat/sat.cc | 44 ++++++++++++------------- passes/sat/sim.cc | 2 +- passes/techmap/abc.cc | 4 +-- passes/techmap/cellmatch.cc | 2 +- passes/techmap/constmap.cc | 4 +-- passes/techmap/extract.cc | 2 +- passes/tests/test_cell.cc | 4 +-- techlibs/fabulous/synth_fabulous.cc | 2 +- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/lattice/synth_lattice.cc | 2 +- techlibs/microchip/synth_microchip.cc | 2 +- techlibs/nanoxplore/synth_nanoxplore.cc | 2 +- techlibs/nexus/synth_nexus.cc | 2 +- techlibs/quicklogic/synth_quicklogic.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 59 files changed, 163 insertions(+), 163 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c7ed3b81f..bf7497bb5 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1446,7 +1446,7 @@ struct XAiger2Backend : Backend { if (!map_filename.empty()) { writer.map_file.open(map_filename); if (!writer.map_file) - log_cmd_error("Failed to open '%s' for writing\n", map_filename.c_str()); + log_cmd_error("Failed to open '%s' for writing\n", map_filename); } design->bufNormalize(true); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 9a7e1383a..48710aff8 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1533,7 +1533,7 @@ struct CxxrtlWorker { } // Internal cells } else if (is_internal_cell(cell->type)) { - log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str()); + log_cmd_error("Unsupported internal cell `%s'.\n", cell->type); // User cells } else if (for_debug) { // Outlines are called on demand when computing the value of a debug item. Nothing to do here. @@ -3803,7 +3803,7 @@ struct CxxrtlBackend : public Backend { if (args[argidx] == "-print-output" && argidx+1 < args.size()) { worker.print_output = args[++argidx]; if (!(worker.print_output == "std::cout" || worker.print_output == "std::cerr")) { - log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output.c_str()); + log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output); worker.print_output = "std::cout"; } continue; diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 459b50683..488775d2c 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1446,7 +1446,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump if (design->has(child->str)) { RTLIL::Module *existing_mod = design->module(child->str); if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { - log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str.c_str()); + log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s.\n", child->str.c_str(), child->loc_string().c_str()); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 262dda43b..5fd478ff3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -795,7 +795,7 @@ struct AST_INTERNAL::ProcessGenerator fmt.append_literal("\n"); fmt.emit_rtlil(cell); } else if (!ast->str.empty()) { - log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str()); + log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str); } break; @@ -846,7 +846,7 @@ struct AST_INTERNAL::ProcessGenerator set_src_attr(cell, ast); for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } cell->setParam(ID::FLAVOR, flavor); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 2669f83e2..0df09030c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -164,7 +164,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ log_file_info(*location.begin.filename, location.begin.line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); return Fmt(); } else { - log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); + log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str, index + 1); } args.push_back(arg); } diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index df64ecd2f..80a6aae6d 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -91,9 +91,9 @@ struct RpcServer { std::string error; Json json_response = Json::parse(response, error); if (json_response.is_null()) - log_cmd_error("parsing JSON failed: %s\n", error.c_str()); + log_cmd_error("parsing JSON failed: %s\n", error); if (json_response["error"].is_string()) - log_cmd_error("RPC frontend returned an error: %s\n", json_response["error"].string_value().c_str()); + log_cmd_error("RPC frontend returned an error: %s\n", json_response["error"].string_value()); return json_response; } @@ -111,7 +111,7 @@ struct RpcServer { } } else is_valid = false; if (!is_valid) - log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump().c_str()); + log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump()); return modules; } @@ -149,7 +149,7 @@ struct RpcServer { source = response["source"].string_value(); else is_valid = false; if (!is_valid) - log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump().c_str()); + log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump()); return std::make_pair(frontend, source); } }; @@ -202,7 +202,7 @@ struct RpcModule : RTLIL::Module { } } if (!found_derived_top) - log_cmd_error("RPC frontend did not return requested module `%s`!\n", stripped_name.c_str()); + log_cmd_error("RPC frontend did not return requested module `%s`!\n", stripped_name); for (auto module : derived_design->modules()) for (auto cell : module->cells()) @@ -256,7 +256,7 @@ struct HandleRpcServer : RpcServer { do { DWORD data_written; if (!WriteFile(hsend, &data[offset], data.length() - offset, &data_written, /*lpOverlapped=*/NULL)) - log_cmd_error("WriteFile failed: %s\n", get_last_error_str().c_str()); + log_cmd_error("WriteFile failed: %s\n", get_last_error_str()); offset += data_written; } while(offset < (ssize_t)data.length()); } @@ -268,7 +268,7 @@ struct HandleRpcServer : RpcServer { data.resize(data.length() + 1024); DWORD data_read; if (!ReadFile(hrecv, &data[offset], data.length() - offset, &data_read, /*lpOverlapped=*/NULL)) - log_cmd_error("ReadFile failed: %s\n", get_last_error_str().c_str()); + log_cmd_error("ReadFile failed: %s\n", get_last_error_str()); offset += data_read; data.resize(offset); size_t term_pos = data.find('\n', offset); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8bb34582e..91af38ccd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1469,7 +1469,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (design->has(module_name)) { if (!nl->IsOperator() && !is_blackbox(nl)) - log_cmd_error("Re-definition of module `%s'.\n", netlist_name.c_str()); + log_cmd_error("Re-definition of module `%s'.\n", netlist_name); return; } @@ -3824,7 +3824,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87)) - log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3849,7 +3849,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93)) - log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3874,7 +3874,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K)) - log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3899,7 +3899,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2019)) - log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3924,7 +3924,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008)) - log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3938,7 +3938,7 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) { std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!edif.Read(filename.c_str())) - log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename); } goto check_error; } @@ -3961,7 +3961,7 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) { std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!synlib_file::Read(filename.c_str(), is_work_set ? work.c_str() : nullptr)) - log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename); SynlibLibrary *lib = synlib_file::GetLastLibraryAnalyzed(); if (lib && flag_lib) { MapIter mi ; diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 9b197b356..661b4ef96 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -45,7 +45,7 @@ using namespace AST; using namespace VERILOG_FRONTEND; void ConstParser::log_maybe_loc_error(std::string msg) { - log_file_error(*loc.begin.filename, loc.begin.line, "%s", msg.c_str()); + log_file_error(*loc.begin.filename, loc.begin.line, "%s", msg); } void ConstParser::log_maybe_loc_warn(std::string msg) { diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 8674758ab..1858edc97 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -741,7 +741,7 @@ read_define(const std::string &filename, defines_map.add(name, value, (state == 2) ? &args : nullptr); global_defines_cache.add(name, value, (state == 2) ? &args : nullptr); } else { - log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str()); + log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name); } } diff --git a/kernel/fmt.cc b/kernel/fmt.cc index 6e9f2924a..200e7e5ce 100644 --- a/kernel/fmt.cc +++ b/kernel/fmt.cc @@ -401,11 +401,11 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik part = {}; } if (++i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } if (++arg == args.end()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name, fmtarg - args.begin() + 1); } part.sig = arg->sig; part.signed_ = arg->signed_; @@ -420,7 +420,7 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik } else break; } if (i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } bool has_leading_zero = false, has_width = false; @@ -465,15 +465,15 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik if (!has_width && !has_leading_zero) part.width = 20; } else { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name, fmt[i], fmtarg - args.begin() + 1); } } else { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name, fmt[i], fmtarg - args.begin() + 1); } break; } if (i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } if (part.padding == '\0') { @@ -486,7 +486,7 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik } if (part.type == FmtPart::INTEGER && part.base != 10 && part.sign != FmtPart::MINUS) - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); if (part.base != 10) part.signed_ = false; diff --git a/kernel/gzip.cc b/kernel/gzip.cc index d19c06579..433c35902 100644 --- a/kernel/gzip.cc +++ b/kernel/gzip.cc @@ -103,11 +103,11 @@ gzip_istream::ibuf::~ibuf() { // Never returns nullptr or failed state istream* std::istream* uncompressed(const std::string filename, std::ios_base::openmode mode) { if (!check_file_exists(filename)) - log_cmd_error("File `%s' not found or is a directory\n", filename.c_str()); + log_cmd_error("File `%s' not found or is a directory\n", filename); std::ifstream* f = new std::ifstream(); f->open(filename, mode); if (f->fail()) - log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open input file `%s' for reading: %s\n", filename, strerror(errno)); // Check for gzip magic unsigned char magic[3]; int n = 0; @@ -131,7 +131,7 @@ std::istream* uncompressed(const std::string filename, std::ios_base::openmode m log_assert(ok && "Failed to open gzipped file.\n"); return s; #else - log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename); #endif // YOSYS_ENABLE_ZLIB } else { f->clear(); diff --git a/kernel/register.cc b/kernel/register.cc index 4afd7ada3..36e312968 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -262,7 +262,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) } if (pass_register.count(args[0]) == 0) - log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str()); + log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0]); if (pass_register[args[0]]->experimental_flag) log_experimental(args[0]); @@ -521,7 +521,7 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string if (args.size() == 0) return; if (frontend_register.count(args[0]) == 0) - log_cmd_error("No such frontend: %s\n", args[0].c_str()); + log_cmd_error("No such frontend: %s\n", args[0]); if (f != NULL) { auto state = frontend_register[args[0]]->pre_execute(); @@ -596,7 +596,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectoropen(filename)) { delete gf; - log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename, strerror(errno)); } yosys_output_files.insert(filename); f = gf; @@ -609,7 +609,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectorfail()) { delete ff; - log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } @@ -641,7 +641,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f if (args.size() == 0) return; if (backend_register.count(args[0]) == 0) - log_cmd_error("No such backend: %s\n", args[0].c_str()); + log_cmd_error("No such backend: %s\n", args[0]); size_t orig_sel_stack_pos = design->selection_stack.size(); diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index e475ba71c..88f07a5aa 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -53,7 +53,7 @@ struct Slice { } static void syntax_error(const std::string &slice) { - log_cmd_error("Invalid slice '%s', expected ':' or ''", slice.c_str()); + log_cmd_error("Invalid slice '%s', expected ':' or ''", slice); } std::string to_string() const { @@ -494,7 +494,7 @@ struct AbstractPass : public Pass { case Enable::ActiveHigh: { Wire *enable_wire = mod->wire("\\" + enable_name); if (!enable_wire) - log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str()); + log_cmd_error("Enable wire %s not found in module %s\n", enable_name, mod->name); if (GetSize(enable_wire) != 1) log_cmd_error("Enable wire %s must have width 1 but has width %d in module %s\n", enable_name.c_str(), GetSize(enable_wire), mod->name.c_str()); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 0d395f043..1011a093c 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -77,7 +77,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire = nullptr; if (wire == nullptr) - log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); + log_cmd_error("Found incompatible object with same name in module %s!\n", module->name); log("Module %s already has such an object.\n", module->name); } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 65292ef92..c6d3320ea 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -150,9 +150,9 @@ struct ConnectPass : public Pass { RTLIL::SigSpec sig_lhs, sig_rhs; if (!RTLIL::SigSpec::parse_sel(sig_lhs, design, module, set_lhs)) - log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str()); + log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs); if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs)) - log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str()); + log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs); sigmap.apply(sig_lhs); sigmap.apply(sig_rhs); @@ -173,7 +173,7 @@ struct ConnectPass : public Pass { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, unset_expr)) - log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str()); + log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr); sigmap.apply(sig); unset_drivers(design, module, sigmap, sig); @@ -185,11 +185,11 @@ struct ConnectPass : public Pass { log_cmd_error("Can't use -port together with -nounset.\n"); if (module->cell(RTLIL::escape_id(port_cell)) == nullptr) - log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); + log_cmd_error("Can't find cell %s.\n", port_cell); RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) - log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); + log_cmd_error("Failed to parse port expression `%s'.\n", port_expr); if (!flag_assert) { module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index dbe23ccf1..5677c666d 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -42,7 +42,7 @@ struct ConnwrappersWorker decl_celltypes.insert(key.first); if (decls.count(key)) - log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname); portdecl_t decl; decl.widthparam = RTLIL::escape_id(widthparam); @@ -57,7 +57,7 @@ struct ConnwrappersWorker decl_celltypes.insert(key.first); if (decls.count(key)) - log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname); portdecl_t decl; decl.widthparam = RTLIL::escape_id(widthparam); diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index e3fb3a0e6..5a5835a43 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -45,10 +45,10 @@ struct CopyPass : public Pass { std::string trg_name = RTLIL::escape_id(args[2]); if (design->module(src_name) == nullptr) - log_cmd_error("Can't find source module %s.\n", src_name.c_str()); + log_cmd_error("Can't find source module %s.\n", src_name); if (design->module(trg_name) != nullptr) - log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); + log_cmd_error("Target module name %s already exists.\n", trg_name); RTLIL::Module *new_mod = design->module(src_name)->clone(); new_mod->name = trg_name; diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index bab00c287..7f217329c 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -118,7 +118,7 @@ struct CoverPass : public Pass { if (f == NULL) { for (auto f : out_files) fclose(f); - log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx].c_str()); + log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx]); } out_files.push_back(f); continue; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 59cd39c98..ddbd98bfd 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -165,13 +165,13 @@ struct DesignPass : public Pass { got_mode = true; load_name = args[++argidx]; if (saved_designs.count(load_name) == 0) - log_cmd_error("No saved design '%s' found!\n", load_name.c_str()); + log_cmd_error("No saved design '%s' found!\n", load_name); continue; } if (!got_mode && args[argidx] == "-copy-from" && argidx+1 < args.size()) { got_mode = true; if (saved_designs.count(args[++argidx]) == 0) - log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No saved design '%s' found!\n", args[argidx]); copy_from_design = saved_designs.at(args[argidx]); copy_to_design = design; continue; @@ -188,7 +188,7 @@ struct DesignPass : public Pass { got_mode = true; import_mode = true; if (saved_designs.count(args[++argidx]) == 0) - log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No saved design '%s' found!\n", args[argidx]); copy_from_design = saved_designs.at(args[argidx]); copy_to_design = design; as_name = args[argidx]; @@ -202,7 +202,7 @@ struct DesignPass : public Pass { got_mode = true; delete_name = args[++argidx]; if (saved_designs.count(delete_name) == 0) - log_cmd_error("No saved design '%s' found!\n", delete_name.c_str()); + log_cmd_error("No saved design '%s' found!\n", delete_name); continue; } break; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index b346fc95d..ff1ef11ff 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -127,7 +127,7 @@ struct ExecPass : public Pass { x.re = YS_REGEX_COMPILE(args[argidx]); expect_stdout.push_back(x); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + log_cmd_error("Error in regex expression '%s' !\n", args[argidx]); } } else if (args[argidx] == "-not-expect-stdout") { flag_expect_stdout = true; @@ -142,11 +142,11 @@ struct ExecPass : public Pass { x.polarity = false; expect_stdout.push_back(x); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + log_cmd_error("Error in regex expression '%s' !\n", args[argidx]); } } else - log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx].c_str()); + log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx]); } } @@ -201,7 +201,7 @@ struct ExecPass : public Pass { if (flag_expect_stdout) for (auto &x : expect_stdout) if (x.polarity ^ x.matched) - log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str()); + log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str); log_pop(); } diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index d7264d392..d906c241d 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -184,7 +184,7 @@ private: for(auto &cell : module->cells().to_vector()) { if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) { - log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type.c_str()); + log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type); } if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) { const unsigned int A = 0, B = 1, Y = 2; diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index 37240bb7e..cab4ab81c 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -112,7 +112,7 @@ struct LoggerPass : public Pass { log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -124,7 +124,7 @@ struct LoggerPass : public Pass { log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -136,7 +136,7 @@ struct LoggerPass : public Pass { log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -188,7 +188,7 @@ struct LoggerPass : public Pass { else log_abort(); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 6c7921d53..afa830552 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -70,7 +70,7 @@ void load_plugin(std::string filename, std::vector aliases) if(module_p == NULL) { PyErr_Print(); - log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); + log_cmd_error("Can't load python module `%s'\n", full_path.filename()); return; } loaded_python_plugins[orig_filename] = module_p; @@ -100,7 +100,7 @@ void load_plugin(std::string filename, std::vector aliases) } if (hdl == NULL) - log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + log_cmd_error("Can't load module `%s': %s\n", filename, dlerror()); loaded_plugins[orig_filename] = hdl; Pass::init_register(); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index c4bb7135e..078ffb769 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -31,7 +31,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: to_name = RTLIL::escape_id(to_name); if (module->count_id(to_name)) - log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str()); + log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name); RTLIL::Wire *wire_to_rename = module->wire(from_name); RTLIL::Cell *cell_to_rename = module->cell(from_name); @@ -55,7 +55,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: return; } - log_cmd_error("Object `%s' not found!\n", from_name.c_str()); + log_cmd_error("Object `%s' not found!\n", from_name); } static std::string derive_name_from_src(const std::string &src, int counter) @@ -632,7 +632,7 @@ struct RenamePass : public Pass { log("Renaming module %s to %s.\n", module_to_rename->name, to_name); design->rename(module_to_rename, to_name); } else - log_cmd_error("Object `%s' not found!\n", from_name.c_str()); + log_cmd_error("Object `%s' not found!\n", from_name); } } } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 7fcf5cfcd..469e36ef1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -592,7 +592,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char while (pos < int(arg.size())) { if (arg[pos] != ':' || pos+1 == int(arg.size())) - log_cmd_error("Syntax error in expand operator '%s'.\n", arg.c_str()); + log_cmd_error("Syntax error in expand operator '%s'.\n", arg); pos++; if (arg[pos] == '+' || arg[pos] == '-') { expand_rule_t rule; @@ -617,7 +617,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char for (auto i2 : i1.second) limits.insert(i2); } else - log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str()); + log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str)); } else limits.insert(RTLIL::escape_id(str)); } @@ -804,7 +804,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp log_cmd_error("Must have at least one element on the stack for operator %%coe.\n"); select_op_expand(design, arg, 'o', true); } else - log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str()); + log_cmd_error("Unknown selection operator '%s'.\n", arg); if (work_stack.size() >= 1) select_filter_active_mod(design, work_stack.back()); return; @@ -815,7 +815,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (design->selection_vars.count(set_name) > 0) work_stack.push_back(design->selection_vars[set_name]); else - log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str()); + log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name)); select_filter_active_mod(design, work_stack.back()); return; } @@ -934,7 +934,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (arg_memb.compare(2, 1, "@") == 0) { std::string set_name = RTLIL::escape_id(arg_memb.substr(3)); if (!design->selection_vars.count(set_name)) - log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str()); + log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name)); auto &muster = design->selection_vars[set_name]; for (auto cell : mod->cells()) @@ -1428,7 +1428,7 @@ struct SelectPass : public Pass { continue; } if (arg.size() > 0 && arg[0] == '-') - log_cmd_error("Unknown option %s.\n", arg.c_str()); + log_cmd_error("Unknown option %s.\n", arg); bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_modcount != -1) || (assert_count != -1) || (assert_max != -1) || (assert_min != -1); select_stmt(design, arg, disable_empty_warning); @@ -1762,7 +1762,7 @@ struct CdPass : public Pass { return; } - log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str()); + log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname)); } } CdPass; diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index f590c2fa9..25d8fd34c 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -39,7 +39,7 @@ struct setunset_t } else { RTLIL::SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value)) - log_cmd_error("Can't decode value '%s'!\n", set_value.c_str()); + log_cmd_error("Can't decode value '%s'!\n", set_value); value = sig_value.as_const(); } } diff --git a/passes/cmds/setenv.cc b/passes/cmds/setenv.cc index 850d7c961..90eeab702 100644 --- a/passes/cmds/setenv.cc +++ b/passes/cmds/setenv.cc @@ -52,7 +52,7 @@ struct SetenvPass : public Pass { _putenv_s(name.c_str(), value.c_str()); #else if (setenv(name.c_str(), value.c_str(), 1)) - log_cmd_error("Invalid name \"%s\".\n", name.c_str()); + log_cmd_error("Invalid name \"%s\".\n", name); #endif } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index c2d446162..d0d9c0f85 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -926,7 +926,7 @@ struct ShowPass : public Pass { if (f == nullptr) { for (auto lib : libs) delete lib; - log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); + log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file); } ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); fclose(f); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 1b9e6106c..6e46ab5e2 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -949,7 +949,7 @@ struct StatPass : public Pass { } if (args[argidx] == "-top" && argidx + 1 < args.size()) { if (design->module(RTLIL::escape_id(args[argidx + 1])) == nullptr) - log_cmd_error("Can't find module %s.\n", args[argidx + 1].c_str()); + log_cmd_error("Can't find module %s.\n", args[argidx + 1]); top_mod = design->module(RTLIL::escape_id(args[++argidx])); continue; } @@ -969,7 +969,7 @@ struct StatPass : public Pass { log_header(design, "Printing statistics.\n"); if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode) - log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); + log_cmd_error("Unsupported technology: '%s'\n", techname); if (json_mode) { log("{\n"); diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index fbd42e311..cef94b9ce 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -83,7 +83,7 @@ struct TeePass : public Pass { if (f == NULL) { for (auto cf : files_to_close) fclose(cf); - log_cmd_error("Can't create file %s.\n", args[argidx].c_str()); + log_cmd_error("Can't create file %s.\n", args[argidx]); } log_files.push_back(f); files_to_close.push_back(f); diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index fd45d6ba0..e3b09d029 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -994,7 +994,7 @@ struct VizPass : public Pass { if (f != nullptr) return; f = fopen(dot_file.c_str(), "w"); if (f == nullptr) - log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); + log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file); }; for (auto module : modlist) { VizWorker worker(module, config); diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 1bcd4a887..4deef6e32 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -64,7 +64,7 @@ struct EquivAddPass : public Pass { log_warning("Can't find gold cell '%s'.\n", args[2].c_str()); return; } - log_cmd_error("Can't find gold cell '%s'.\n", args[2].c_str()); + log_cmd_error("Can't find gold cell '%s'.\n", args[2]); } if (gate_cell == nullptr) { @@ -72,7 +72,7 @@ struct EquivAddPass : public Pass { log_warning("Can't find gate cell '%s'.\n", args[3].c_str()); return; } - log_cmd_error("Can't find gate cell '%s'.\n", args[3].c_str()); + log_cmd_error("Can't find gate cell '%s'.\n", args[3]); } for (auto conn : gold_cell->connections()) @@ -129,7 +129,7 @@ struct EquivAddPass : public Pass { log_warning("Error in gate signal: %s\n", args[2].c_str()); return; } - log_cmd_error("Error in gate signal: %s\n", args[2].c_str()); + log_cmd_error("Error in gate signal: %s\n", args[2]); } if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) { @@ -137,7 +137,7 @@ struct EquivAddPass : public Pass { log_warning("Error in gold signal: %s\n", args[1].c_str()); return; } - log_cmd_error("Error in gold signal: %s\n", args[1].c_str()); + log_cmd_error("Error in gold signal: %s\n", args[1]); } log_assert(GetSize(gold_signal) == GetSize(gate_signal)); diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e15e510be..bae7452f7 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -47,7 +47,7 @@ struct EquivMakeWorker { std::ifstream f(fn); if (f.fail()) - log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str()); + log_cmd_error("Can't open blacklist file '%s'!\n", fn); string line, token; while (std::getline(f, line)) { @@ -67,7 +67,7 @@ struct EquivMakeWorker { std::ifstream f(fn); if (f.fail()) - log_cmd_error("Can't open encfile '%s'!\n", fn.c_str()); + log_cmd_error("Can't open encfile '%s'!\n", fn); dict *ed = nullptr; string line, token; @@ -81,7 +81,7 @@ struct EquivMakeWorker IdString modname = RTLIL::escape_id(next_token(line)); IdString signame = RTLIL::escape_id(next_token(line)); if (encdata.count(signame)) - log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame.c_str(), fn.c_str()); + log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn); encdata[signame] = dict(); ed = &encdata[signame]; continue; @@ -94,7 +94,7 @@ struct EquivMakeWorker continue; } - log_cmd_error("Syntax error in encfile '%s'!\n", fn.c_str()); + log_cmd_error("Syntax error in encfile '%s'!\n", fn); } } } @@ -492,13 +492,13 @@ struct EquivMakePass : public Pass { worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2])); if (worker.gold_mod == nullptr) - log_cmd_error("Can't find gold module %s.\n", args[argidx].c_str()); + log_cmd_error("Can't find gold module %s.\n", args[argidx]); if (worker.gate_mod == nullptr) - log_cmd_error("Can't find gate module %s.\n", args[argidx+1].c_str()); + log_cmd_error("Can't find gate module %s.\n", args[argidx+1]); if (worker.equiv_mod != nullptr) - log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str()); + log_cmd_error("Equiv module %s already exists.\n", args[argidx+2]); if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes()) log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 6fec628c2..f670d1fd2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -957,7 +957,7 @@ struct HierarchyPass : public Pass { for (auto ¶ : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) - log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + log_cmd_error("Can't decode value '%s'!\n", para.second); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } } @@ -991,7 +991,7 @@ struct HierarchyPass : public Pass { } #endif if (top_mod == NULL) - log_cmd_error("Module `%s' not found!\n", load_top_mod.c_str()); + log_cmd_error("Module `%s' not found!\n", load_top_mod); } else { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) @@ -1045,7 +1045,7 @@ struct HierarchyPass : public Pass { for (auto ¶ : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) - log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + log_cmd_error("Can't decode value '%s'!\n", para.second); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 486d21920..f979e7acc 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -408,7 +408,7 @@ struct SubmodPass : public Pass { RTLIL::Module *module = nullptr; for (auto mod : design->selected_modules()) { if (module != nullptr) - log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod->name.c_str()); + log_cmd_error("More than one module selected: %s %s\n", module->name, mod->name); module = mod; } if (module == nullptr) diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 248c3dfe9..37ae38225 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -555,7 +555,7 @@ struct OptLutPass : public Pass { { std::string tech = args[++argidx]; if (tech != "ice40") - log_cmd_error("Unsupported -tech argument: %s\n", tech.c_str()); + log_cmd_error("Unsupported -tech argument: %s\n", tech); dlogic = {{ ID(SB_CARRY), diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 9e471c3de..fa8eb563b 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -59,7 +59,7 @@ struct OptLutInsPass : public Pass { extra_args(args, argidx, design); if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") - log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); + log_cmd_error("Unsupported technology: '%s'\n", techname); for (auto module : design->selected_modules()) { diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 892500850..f6d6a3f93 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -238,7 +238,7 @@ struct TestPmgenPass : public Pass { if (pattern == "xilinx_srl.variable") return GENERATE_PATTERN(xilinx_srl_pm, variable); - log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); + log_cmd_error("Unknown pattern: %s\n", pattern); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index f71e8124b..b0eaaca22 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -94,11 +94,11 @@ struct BruteForceEquivChecker continue; if (mod2->wire(w->name) == nullptr) - log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str()); + log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name); RTLIL::Wire *w2 = mod2->wire(w->name); if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output) - log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str()); + log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name); if (w->port_input) { mod1_inputs.append(w); @@ -454,11 +454,11 @@ struct EvalPass : public Pass { for (auto &it : sets) { RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second); if (!rhs.is_fully_const()) - log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str()); + log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second); if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size()); @@ -476,7 +476,7 @@ struct EvalPass : public Pass { for (auto &it : shows) { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) - log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", it); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { @@ -502,14 +502,14 @@ struct EvalPass : public Pass { for (auto &it : shows) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, it)) - log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", it); signal.append(sig); } for (auto &it : tables) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, it)) - log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse table expression `%s'.\n", it); tabsigs.append(sig); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9bcf25547..55a41909d 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -76,11 +76,11 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); if (design->module(gold_name) == nullptr) - log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); + log_cmd_error("Can't find gold module %s!\n", gold_name); if (design->module(gate_name) == nullptr) - log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); + log_cmd_error("Can't find gate module %s!\n", gate_name); if (design->module(miter_name) != nullptr) - log_cmd_error("There is already a module %s!\n", miter_name.c_str()); + log_cmd_error("There is already a module %s!\n", miter_name); RTLIL::Module *gold_module = design->module(gold_name); RTLIL::Module *gate_module = design->module(gate_name); @@ -105,7 +105,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gold_port_error; continue; match_gold_port_error: - log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str()); + log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name); } for (auto gate_wire : gate_module->wires()) { @@ -125,7 +125,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gate_port_error; continue; match_gate_port_error: - log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str()); + log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); } log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); @@ -322,9 +322,9 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : ""; if (design->module(module_name) == nullptr) - log_cmd_error("Can't find module %s!\n", module_name.c_str()); + log_cmd_error("Can't find module %s!\n", module_name); if (!miter_name.empty() && design->module(miter_name) != nullptr) - log_cmd_error("There is already a module %s!\n", miter_name.c_str()); + log_cmd_error("There is already a module %s!\n", miter_name); Module *module = design->module(module_name); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 58d932f20..79ffcd88d 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -989,7 +989,7 @@ struct MutatePass : public Pass { return; } - log_cmd_error("Invalid mode: %s\n", opts.mode.c_str()); + log_cmd_error("Invalid mode: %s\n", opts.mode); } } MutatePass; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index 20cee7956..ad28884f7 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -87,7 +87,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { if (!std::regex_search(buf, bit_m, hole_bit_assn_regex)) { bit_assn = false; if (!std::regex_search(buf, m, hole_assn_regex)) - log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf.c_str()); + log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf); } std::string hole_loc = bit_assn? bit_m[1].str() : m[1].str(); @@ -108,7 +108,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { pool hole_loc_pool(locs.begin(), locs.end()); auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool); if (hole_cell_it == anyconst_loc_to_cell.end()) - log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf.c_str()); + log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf); RTLIL::Cell *hole_cell = hole_cell_it->second; hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit]; @@ -420,7 +420,7 @@ QbfSolveOptions parse_args(const std::vector &args) { else if (args[opt.argidx+1] == "cvc5") opt.solver = opt.Solver::CVC5; else - log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1].c_str()); + log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1]); opt.argidx++; } continue; @@ -457,7 +457,7 @@ QbfSolveOptions parse_args(const std::vector &args) { opt.oflag = opt.OptimizationLevel::O2; break; default: - log_cmd_error("unknown argument %s\n", args[opt.argidx].c_str()); + log_cmd_error("unknown argument %s\n", args[opt.argidx]); } continue; } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 5216390da..90b85d709 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -106,9 +106,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -127,9 +127,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -148,7 +148,7 @@ struct SatHelper RTLIL::SigSpec lhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s); show_signal_pool.add(sigmap(lhs)); log("Import unset-constraint for this timestep: %s\n", log_signal(lhs)); @@ -167,28 +167,28 @@ struct SatHelper for (auto &s : sets_def) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].insert(sig); } for (auto &s : sets_any_undef) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[1].insert(sig); } for (auto &s : sets_all_undef) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[2].insert(sig); } for (auto &s : sets_def_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].insert(sig); sets_def_undef[1].erase(sig); sets_def_undef[2].erase(sig); @@ -197,7 +197,7 @@ struct SatHelper for (auto &s : sets_any_undef_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].erase(sig); sets_def_undef[1].insert(sig); sets_def_undef[2].erase(sig); @@ -206,7 +206,7 @@ struct SatHelper for (auto &s : sets_all_undef_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].erase(sig); sets_def_undef[1].erase(sig); sets_def_undef[2].insert(sig); @@ -295,9 +295,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -362,9 +362,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -390,9 +390,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -540,7 +540,7 @@ struct SatHelper for (auto &s : shows) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", s); log("Import show expression: %s\n", log_signal(sig)); modelSig.append(sig); } @@ -670,7 +670,7 @@ struct SatHelper rewrite_filename(vcd_file_name); FILE *f = fopen(vcd_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name, strerror(errno)); log("Dumping SAT model to VCD file %s\n", vcd_file_name); @@ -775,7 +775,7 @@ struct SatHelper rewrite_filename(json_file_name); FILE *f = fopen(json_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name, strerror(errno)); log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name); @@ -1535,7 +1535,7 @@ struct SatPass : public Pass { rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno)); log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); @@ -1639,7 +1639,7 @@ struct SatPass : public Pass { rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno)); log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index aadea328f..56b207a58 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2887,7 +2887,7 @@ struct SimPass : public Pass { } else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".yw") == 0) { worker.run_cosim_yw_witness(top_mod, append); } else { - log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str()); + log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename); } } diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c5bdd6ecf..9cd02b455 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -988,7 +988,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module } if (dff_mode && clk_sig.empty()) - log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); + log_cmd_error("Clock domain %s not found.\n", clk_str); const AbcConfig &config = run_abc.config; if (config.cleanup) @@ -2322,7 +2322,7 @@ struct AbcPass : public Pass { if (g_arg_from_cmd) cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g)); else - log_cmd_error("Unsupported gate type: %s", g.c_str()); + log_cmd_error("Unsupported gate type: %s", g); ok_gate: gate_list.push_back(g); ok_alias: diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index a2a4c4b2c..ce1a75193 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -173,7 +173,7 @@ struct CellmatchPass : Pass { derive_luts = true; } else if (args[argidx] == "-lib" && argidx + 1 < args.size()) { if (!saved_designs.count(args[++argidx])) - log_cmd_error("No design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No design '%s' found!\n", args[argidx]); lib = saved_designs.at(args[argidx]); } else { break; diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc index f0757403d..6d18b8494 100644 --- a/passes/techmap/constmap.cc +++ b/passes/techmap/constmap.cc @@ -82,7 +82,7 @@ struct ConstmapPass : public Pass { } } if (!has_port) - log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str()); + log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype, cell_portname); bool has_param = false; for (auto &p : existing->avail_parameters){ @@ -91,7 +91,7 @@ struct ConstmapPass : public Pass { } if (!has_param) - log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str()); + log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype, cell_paramname); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 6527b683e..7461e21d8 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -605,7 +605,7 @@ struct ExtractPass : public Pass { f.open(filename.c_str()); if (f.fail()) { delete map; - log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); + log_cmd_error("Can't open map file `%s'.\n", filename); } Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); f.close(); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 75a63b2e0..f882aa356 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -958,7 +958,7 @@ struct TestCellPass : public Pass { if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) { vlog_file.open(args[++argidx], std::ios_base::trunc); if (!vlog_file.is_open()) - log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str()); + log_cmd_error("Failed to open output file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-bloat" && argidx+1 < GetSize(args)) { @@ -1079,7 +1079,7 @@ struct TestCellPass : public Pass { for (; argidx < GetSize(args); argidx++) { if (args[argidx].rfind("-", 0) == 0) - log_cmd_error("Unexpected option: %s\n", args[argidx].c_str()); + log_cmd_error("Unexpected option: %s\n", args[argidx]); if (args[argidx] == "all") { for (auto &it : cell_types) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0e6553fa1..3b95ff91e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -236,7 +236,7 @@ struct SynthPass : public ScriptPass if (args[argidx] == "-carry") { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") - log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str()); + log_cmd_error("Unsupported carry style: %s\n", carry_mode); continue; } if (args[argidx] == "-noflatten") { diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 99fe45dc4..fa52ecfc6 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -123,7 +123,7 @@ struct SynthGreenPAK4Pass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V") - log_cmd_error("Invalid part name: '%s'\n", part.c_str()); + log_cmd_error("Invalid part name: '%s'\n", part); log_header(design, "Executing SYNTH_GREENPAK4 pass.\n"); log_push(); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index d433c0408..0a4144451 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -265,7 +265,7 @@ struct SynthIce40Pass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") - log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str()); + log_cmd_error("Invalid or no device specified: '%s'\n", device_opt); if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index af0717235..d3202d5cb 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -174,7 +174,7 @@ struct SynthIntelPass : public ScriptPass { family_opt != "cycloneiv" && family_opt != "cycloneive" && family_opt != "cyclone10lp") - log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); + log_cmd_error("Invalid or no family specified: '%s'\n", family_opt); log_header(design, "Executing SYNTH_INTEL pass.\n"); log_push(); diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index e1df20dd7..b13c22518 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -306,7 +306,7 @@ struct SynthLatticePass : public ScriptPass family == "lifmd" || family == "lifmdf") {*/ } else - log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc index 77cedcd1f..e1d3c393a 100644 --- a/techlibs/microchip/synth_microchip.cc +++ b/techlibs/microchip/synth_microchip.cc @@ -234,7 +234,7 @@ struct SynthMicrochipPass : public ScriptPass { if (family == "polarfire") { lut_size = 4; } else { - log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family); } if (!design->full_selection()) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index a8f4a05d1..3445ea1be 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -218,7 +218,7 @@ struct SynthNanoXplorePass : public ScriptPass } else if (family == "large") { postfix = "_l"; } else - log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); diff --git a/techlibs/nexus/synth_nexus.cc b/techlibs/nexus/synth_nexus.cc index 83abd156a..c0df06a21 100644 --- a/techlibs/nexus/synth_nexus.cc +++ b/techlibs/nexus/synth_nexus.cc @@ -249,7 +249,7 @@ struct SynthNexusPass : public ScriptPass { if (family != "lifcl" && family != "lfd2nx") - log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family); if (check_label("begin")) { diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 84f9c48a7..ade6f944c 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -176,7 +176,7 @@ struct SynthQuickLogicPass : public ScriptPass { log_cmd_error("This command only operates on fully selected designs!\n"); if (family != "pp3" && family != "qlf_k6n10f") - log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); + log_cmd_error("Invalid family specified: '%s'\n", family); if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4e422c5cd..20b8c98c3 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -310,7 +310,7 @@ struct SynthXilinxPass : public ScriptPass lut_size = 4; widelut_size = 6; } else - log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family); if (widemux != 0 && lut_size != 6) log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n"); From d1fd6de6da916cc3fbb64c962d94236e02568e71 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:00:42 +0000 Subject: [PATCH 121/188] Remove .c_str() calls from parameters to log_header() --- frontends/ast/ast.cc | 2 +- frontends/liberty/liberty.cc | 2 +- frontends/rpc/rpc_frontend.cc | 2 +- frontends/verilog/verilog_frontend.cc | 2 +- kernel/register.cc | 2 +- passes/cmds/exec.cc | 2 +- passes/cmds/logcmd.cc | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 488775d2c..4a16abee9 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1822,7 +1822,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict rewritten; diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 72ad8b2b7..80553347c 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -537,7 +537,7 @@ struct LibertyFrontend : public Frontend { if (flag_wb && flag_lib) log_error("-wb and -lib cannot be specified together!\n"); - log_header(design, "Executing Liberty frontend: %s\n", filename.c_str()); + log_header(design, "Executing Liberty frontend: %s\n", filename); LibertyParser parser(*f, filename); int cell_count = 0; diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 80a6aae6d..625b2c0e8 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -163,7 +163,7 @@ struct RpcModule : RTLIL::Module { stripped_name = stripped_name.substr(9); log_assert(stripped_name[0] == '\\'); - log_header(design, "Executing RPC frontend `%s' for module `%s'.\n", server->name.c_str(), stripped_name.c_str()); + log_header(design, "Executing RPC frontend `%s' for module `%s'.\n", server->name, stripped_name); std::string parameter_info; for (auto ¶m : parameters) { diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 231891271..2bdaf40ce 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -485,7 +485,7 @@ struct VerilogFrontend : public Frontend { extra_args(f, filename, args, argidx); - log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename); log("Parsing %s%s input from `%s' to AST representation.\n", parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str()); diff --git a/kernel/register.cc b/kernel/register.cc index 36e312968..fe67cc35c 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -199,7 +199,7 @@ void Pass::call(RTLIL::Design *design, std::string command) while (!cmd_buf.empty() && (cmd_buf.back() == ' ' || cmd_buf.back() == '\t' || cmd_buf.back() == '\r' || cmd_buf.back() == '\n')) cmd_buf.resize(cmd_buf.size()-1); - log_header(design, "Shell command: %s\n", cmd_buf.c_str()); + log_header(design, "Shell command: %s\n", cmd_buf); int retCode = run_command(cmd_buf); if (retCode != 0) log_cmd_error("Shell command returned error code %d.\n", retCode); diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index ff1ef11ff..ea82ff908 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -150,7 +150,7 @@ struct ExecPass : public Pass { } } - log_header(design, "Executing command \"%s\".\n", cmd.c_str()); + log_header(design, "Executing command \"%s\".\n", cmd); log_push(); fflush(stdout); diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 57759fc90..dd2d708d8 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -107,7 +107,7 @@ struct LogPass : public Pass { if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end); if (to_log) { if (!header) log("%s%s", text, line_end); - else log_header(design, "%s%s", text.c_str(), line_end); + else log_header(design, "%s%s", text, line_end); } } } LogPass; From a7c46f7b4afc182af11b6f6ffb7a166d60fe7997 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:02:16 +0000 Subject: [PATCH 122/188] Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() --- backends/edif/edif.cc | 2 +- backends/firrtl/firrtl.cc | 6 +++--- frontends/ast/simplify.cc | 8 ++++---- frontends/verific/verific.cc | 4 ++-- frontends/verific/verificsva.cc | 2 +- kernel/log.cc | 4 ++-- kernel/register.cc | 2 +- kernel/tclapi.cc | 2 +- passes/cmds/check.cc | 6 +++--- passes/cmds/select.cc | 8 ++++---- passes/cmds/stat.cc | 4 ++-- passes/cmds/timeest.cc | 2 +- passes/equiv/equiv_add.cc | 8 ++++---- passes/fsm/fsm_detect.cc | 2 +- passes/hierarchy/hierarchy.cc | 2 +- passes/hierarchy/submod.cc | 4 ++-- passes/memory/memlib.cc | 2 +- passes/opt/opt_clean.cc | 2 +- passes/sat/qbfsat.cc | 2 +- passes/sat/sim.cc | 24 ++++++++++++------------ passes/techmap/abc9_exe.cc | 2 +- passes/techmap/libparse.cc | 4 ++-- passes/tests/test_cell.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 25 files changed, 54 insertions(+), 54 deletions(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 83d0afaf3..d1be0b37f 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -513,7 +513,7 @@ struct EdifBackend : public Backend { if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) { if (sig == RTLIL::State::Sx) { for (auto &ref : it.second) - log_warning("Exporting x-bit on %s as zero bit.\n", ref.first.c_str()); + log_warning("Exporting x-bit on %s as zero bit.\n", ref.first); sig = RTLIL::State::S0; } else if (sig == RTLIL::State::Sz) { continue; diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index e54b46e63..577d95ad7 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -465,7 +465,7 @@ struct FirrtlWorker // If there is no instance for this, just return. if (instModule == NULL) { - log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str()); + log_warning("No instance for %s.%s\n", cell_type, cell_name); return; } @@ -490,7 +490,7 @@ struct FirrtlWorker const SigSpec *sinkSig = nullptr; switch (dir) { case FD_INOUT: - log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type, log_signal(it->second)); YS_FALLTHROUGH case FD_OUT: sourceExpr = firstName; @@ -498,7 +498,7 @@ struct FirrtlWorker sinkSig = &secondSig; break; case FD_NODIRECTION: - log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type, log_signal(it->second)); YS_FALLTHROUGH case FD_IN: sourceExpr = secondExpr; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0df09030c..9b679d0aa 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -974,7 +974,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin message += stringf("%s%s", first_element ? " See " : ", ", place); first_element = false; } - log_warning("%s\n", message.c_str()); + log_warning("%s\n", message); } silent_activate: @@ -1144,7 +1144,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin i--; // Adjust index since we removed an element } else { // If we can't find the package, just remove the import node to avoid errors later - log_warning("Package `%s' not found for import, removing import statement\n", child->str.c_str()); + log_warning("Package `%s' not found for import, removing import statement\n", child->str); children.erase(children.begin() + i); i--; // Adjust index since we removed an element } @@ -1438,7 +1438,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic) children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg) - log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str.c_str(), loc_string().c_str()); + log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str, loc_string()); if (type == AST_ASSIGN && children[0]->id2ast->is_reg) { bool is_rand_reg = false; if (children[1]->type == AST_FCALL) { @@ -1452,7 +1452,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin is_rand_reg = true; } if (!is_rand_reg) - log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str.c_str(), loc_string().c_str()); + log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str, loc_string()); } children[0]->was_checked = true; } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 91af38ccd..279b0dd52 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -141,7 +141,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil #endif } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) - log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); + log_warning_noprefix("%s%s\n", message_prefix, message); else log("%s%s\n", message_prefix, message); } @@ -4098,7 +4098,7 @@ struct VerificPass : public Pass { unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(), 1 /* force_overwrite */); if (!new_insertion) - log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str()); + log_warning_noprefix("-chparam %s already specified: overwriting.\n", key); continue; } if (args[argidx] == "-V") { diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index cc5f07004..3908947eb 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1025,7 +1025,7 @@ struct VerificSvaImporter { if (!importer->mode_keep) log_error("%s", errmsg); - log_warning("%s", errmsg.c_str()); + log_warning("%s", errmsg); throw ParserErrorException(); } diff --git a/kernel/log.cc b/kernel/log.cc index 3a44a3ddc..0085980b1 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -187,7 +187,7 @@ static void logv_string(std::string_view format, std::string str) { if (!linebuffer.empty() && linebuffer.back() == '\n') { for (auto &re : log_warn_regexes) if (std::regex_search(linebuffer, re)) - log_warning("Found log message matching -W regex:\n%s", str.c_str()); + log_warning("Found log message matching -W regex:\n%s", str); for (auto &[_, item] : log_expect_log) if (std::regex_search(linebuffer, item.pattern)) @@ -704,7 +704,7 @@ dict> get_coverage_data() for (auto &it : extra_coverage_data) { if (coverage_data.count(it.first)) - log_warning("found duplicate coverage id \"%s\".\n", it.first.c_str()); + log_warning("found duplicate coverage id \"%s\".\n", it.first); coverage_data[it.first].first = it.second.first; coverage_data[it.first].second += it.second.second; } diff --git a/kernel/register.cc b/kernel/register.cc index fe67cc35c..9436b540a 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -972,7 +972,7 @@ struct HelpPass : public Pass { } for (auto &it : cell_help_messages.cell_help) { if (cells.count(it.first) == 0) { - log_warning("Found cell model '%s' without matching cell type.\n", it.first.c_str()); + log_warning("Found cell model '%s' without matching cell type.\n", it.first); } } diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 729d06ca0..a2ebaffa2 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -137,7 +137,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a if (err.empty()) { Tcl_SetObjResult(interp, json_to_tcl(interp, json)); } else - log_warning("Ignoring result.json scratchpad value due to parse error: %s\n", err.c_str()); + log_warning("Ignoring result.json scratchpad value due to parse error: %s\n", err); } else if ((result = scratchpad.find("result.string")) != scratchpad.end()) { Tcl_SetObjResult(interp, Tcl_NewStringObj(result->second.data(), result->second.size())); } diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index b532b4527..9f72d90f7 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -323,7 +323,7 @@ struct CheckPass : public Pass { string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state)); for (auto str : wire_drivers[state]) message += stringf(" %s\n", str); - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } @@ -332,7 +332,7 @@ struct CheckPass : public Pass { string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first)); for (auto str : it.second) message += stringf(" %s\n", str); - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } @@ -418,7 +418,7 @@ struct CheckPass : public Pass { prev = bit; } - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 469e36ef1..6da15c19a 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -658,7 +658,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char } if (rem_objects == 0) - log_warning("reached configured limit at `%s'.\n", arg.c_str()); + log_warning("reached configured limit at `%s'.\n", arg); } static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel) @@ -1002,14 +1002,14 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (it.second == false && !disable_empty_warning) { std::string selection_str = select_blackboxes ? "=" : ""; selection_str += it.first; - log_warning("Selection \"%s\" did not match any module.\n", selection_str.c_str()); + log_warning("Selection \"%s\" did not match any module.\n", selection_str); } } for (auto &it : arg_memb_found) { if (it.second == false && !disable_empty_warning) { std::string selection_str = select_blackboxes ? "=" : ""; selection_str += it.first; - log_warning("Selection \"%s\" did not match any object.\n", selection_str.c_str()); + log_warning("Selection \"%s\" did not match any object.\n", selection_str); } } } @@ -1451,7 +1451,7 @@ struct SelectPass : public Pass { while (std::getline(f, line)) { size_t slash_pos = line.find('/'); if (slash_pos == string::npos) { - log_warning("Ignoring line without slash in 'select -read': %s\n", line.c_str()); + log_warning("Ignoring line without slash in 'select -read': %s\n", line); continue; } IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos)); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 6e46ab5e2..61135e066 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -228,7 +228,7 @@ struct statdata_t { cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } else { - log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type.c_str(), max_width, + log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type, max_width, (int)cell_data.single_parameter_area.size()); cell_area.at(cell_type).area = cell_data.single_parameter_area.back(); cell_area.at(cell_type).is_sequential = cell_data.is_sequential; @@ -274,7 +274,7 @@ struct statdata_t { cell_data.double_parameter_area.at(width_a - 1).at(width_b - 1); cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } else { - log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type.c_str(), + log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type, width_a, width_b, (int)cell_data.double_parameter_area.size(), (int)cell_data.double_parameter_area.at(width_a - 1).size()); cell_area.at(cell_type).area = cell_data.double_parameter_area.back().back(); diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 86a529520..b878050da 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -403,7 +403,7 @@ struct TimeestPass : Pass { for (auto m : d->selected_modules()) { if (!m->wire(RTLIL::escape_id(clk))) { - log_warning("No domain '%s' in module %s\n", clk.c_str(), log_id(m)); + log_warning("No domain '%s' in module %s\n", clk, log_id(m)); continue; } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 4deef6e32..b3c97fa80 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -61,7 +61,7 @@ struct EquivAddPass : public Pass { if (gold_cell == nullptr) { if (try_mode) { - log_warning("Can't find gold cell '%s'.\n", args[2].c_str()); + log_warning("Can't find gold cell '%s'.\n", args[2]); return; } log_cmd_error("Can't find gold cell '%s'.\n", args[2]); @@ -69,7 +69,7 @@ struct EquivAddPass : public Pass { if (gate_cell == nullptr) { if (try_mode) { - log_warning("Can't find gate cell '%s'.\n", args[3].c_str()); + log_warning("Can't find gate cell '%s'.\n", args[3]); return; } log_cmd_error("Can't find gate cell '%s'.\n", args[3]); @@ -126,7 +126,7 @@ struct EquivAddPass : public Pass { if (!SigSpec::parse(gate_signal, module, args[2])) { if (try_mode) { - log_warning("Error in gate signal: %s\n", args[2].c_str()); + log_warning("Error in gate signal: %s\n", args[2]); return; } log_cmd_error("Error in gate signal: %s\n", args[2]); @@ -134,7 +134,7 @@ struct EquivAddPass : public Pass { if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) { if (try_mode) { - log_warning("Error in gold signal: %s\n", args[1].c_str()); + log_warning("Error in gold signal: %s\n", args[1]); return; } log_cmd_error("Error in gold signal: %s\n", args[1]); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 86d654cc4..9cffbf95a 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -225,7 +225,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false) if (!warnings.empty()) { string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire)); for (auto w : warnings) warnmsg += " " + w; - log_warning("%s", warnmsg.c_str()); + log_warning("%s", warnmsg); } else { log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire)); } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f670d1fd2..a7f86c3f0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -937,7 +937,7 @@ struct HierarchyPass : public Pass { const std::string &value = args[++argidx]; auto r = parameters.emplace(key, value); if (!r.second) { - log_warning("-chparam %s already specified: overwriting.\n", key.c_str()); + log_warning("-chparam %s already specified: overwriting.\n", key); r.first->second = value; } continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index f979e7acc..bf135386c 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -95,7 +95,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { - log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type); for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } @@ -111,7 +111,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) - log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type); } } diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index 216b750fd..11c9f9074 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -1097,7 +1097,7 @@ Library MemLibrary::parse_library(const std::vector &filenames, con Parser(file, res, defines, defines_unused); } for (auto def: defines_unused) { - log_warning("define %s not used in the library.\n", def.c_str()); + log_warning("define %s not used in the library.\n", def); } return res; } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cef2c0dc3..b9df09ea6 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -233,7 +233,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto it : driver_driver_logs) { if (used_raw_bits.count(it.first)) for (auto msg : it.second) - log_warning("%s\n", msg.c_str()); + log_warning("%s\n", msg); } } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index ad28884f7..b011227e2 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -233,7 +233,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, ret.stdout_lines.push_back(line.substr(0, line.size()-1)); //don't include trailing newline auto warning_pos = line.find(smtbmc_warning); if (warning_pos != std::string::npos) - log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str()); + log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1)); else if (opt.show_smtbmc && !quiet) log("smtbmc output: %s", line); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 56b207a58..1b653a218 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -256,7 +256,7 @@ struct SimInstance if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) { fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0 && wire->name.isPublic()) - log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name))); fst_handles[wire] = id; } @@ -927,7 +927,7 @@ struct SimInstance if (shared->serious_asserts) log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); else - log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_warning("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); } } } @@ -1244,7 +1244,7 @@ struct SimInstance Const fst_val = Const::from_string(shared->fst->valueOf(item.second)); Const sim_val = get_state(item.first); if (sim_val.size()!=fst_val.size()) { - log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope.c_str(), log_id(item.first)); + log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first)); continue; } if (shared->sim_mode == SimulationMode::sim) { @@ -1252,7 +1252,7 @@ struct SimInstance } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;isim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X for(int i=0;icell(escaped_s); if (!c) - log_warning("Wire/cell %s not present in module %s\n",symbol.c_str(),log_id(topmod)); + log_warning("Wire/cell %s not present in module %s\n",symbol,log_id(topmod)); if (c->is_mem_cell()) { std::string memid = c->parameters.at(ID::MEMID).decode_string(); @@ -1873,7 +1873,7 @@ struct SimWorker : SimShared log("witness hierarchy: found wire %s\n", path.str()); bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second; if (!inserted) - log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); + log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str()); } } else if (item.mem) { auto it = mem_paths.find(path); @@ -1890,7 +1890,7 @@ struct SimWorker : SimShared continue; bool inserted = hierarchy.paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second; if (!inserted) - log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); + log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str()); } } } @@ -1899,7 +1899,7 @@ struct SimWorker : SimShared for (auto &path : paths) if (!hierarchy.paths.count(path)) - log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str().c_str()); + log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str()); dict> clock_inputs; @@ -1922,7 +1922,7 @@ struct SimWorker : SimShared for (int t = 0; t < GetSize(yw.steps); t++) { if (yw.get_bits(t, clock_bits_offset, 1) != expected) - log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str().c_str(), t); + log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str(), t); } } } @@ -2000,7 +2000,7 @@ struct SimWorker : SimShared YwHierarchy hierarchy = prepare_yw_hierarchy(yw); if (yw.steps.empty()) { - log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str()); + log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename); } else { top->set_initstate_outputs(initstate ? State::S1 : State::S0); set_yw_state(yw, hierarchy, 0); diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index d7a7e3d4a..ac723fdbb 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -329,7 +329,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe #endif if (ret != 0) { if (check_file_exists(stringf("%s/output.aig", tempdir_name))) - log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); else log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index c89495c62..7d4fd77ad 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -191,7 +191,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { s.next(); lhs = parse(s); if (s.peek() != ')') { - log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr().c_str()); + log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr()); return lhs; } s.next(); @@ -200,7 +200,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { lhs.kind = Kind::NOT; lhs.children.push_back(parse(s, 7)); } else { - log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr().c_str()); + log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr()); return lhs; } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index f882aa356..9603956a8 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -1192,7 +1192,7 @@ struct TestCellPass : public Pass { worst_abs = num_cells - num_cells_estimate; worst_rel = (float)(num_cells - num_cells_estimate) / (float)num_cells_estimate; } - log_warning("Upper bound violated for %s: %d > %d\n", cell_type.c_str(), num_cells, num_cells_estimate); + log_warning("Upper bound violated for %s: %d > %d\n", cell_type, num_cells, num_cells_estimate); } } } diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index d3202d5cb..e02885cd0 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -242,7 +242,7 @@ struct SynthIntelPass : public ScriptPass { run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); } else { - log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str()); + log_warning("BRAM mapping is not currently supported for %s.\n", family_opt); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 20b8c98c3..46b30573c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -316,7 +316,7 @@ struct SynthXilinxPass : public ScriptPass log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n"); if (lut_size != 6) { - log_warning("Shift register inference not yet supported for family %s.\n", family.c_str()); + log_warning("Shift register inference not yet supported for family %s.\n", family); nosrl = true; } From 548deba259e8f58ed2704ee237347a965b0b8b26 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:03:45 +0000 Subject: [PATCH 123/188] Remove .c_str() calls from parameters to log_file_warning() --- frontends/ast/genrtlil.cc | 4 ++-- frontends/ast/simplify.cc | 4 ++-- frontends/verilog/const2ast.cc | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 5fd478ff3..84f2f9d73 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1539,7 +1539,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (dynamic_cast(current_module)) { /* nothing to do here */ } else if (flag_autowire) - log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str); else input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str); } @@ -2200,7 +2200,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_info(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$warning") { if (sz > 0) - log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str); else log_file_warning(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$error") { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9b679d0aa..d4e78b730 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1032,7 +1032,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin // note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" || str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { - log_file_warning(*location.begin.filename, location.begin.line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str); delete_children(); str = std::string(); } @@ -1042,7 +1042,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo")) { if (!current_always) { - log_file_warning(*location.begin.filename, location.begin.line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "System task `%s' outside initial or always block is unsupported.\n", str); delete_children(); str = std::string(); } else { diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 661b4ef96..573af336b 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -49,7 +49,7 @@ void ConstParser::log_maybe_loc_error(std::string msg) { } void ConstParser::log_maybe_loc_warn(std::string msg) { - log_file_warning(*loc.begin.filename, loc.begin.line, "%s", msg.c_str()); + log_file_warning(*loc.begin.filename, loc.begin.line, "%s", msg); } // divide an arbitrary length decimal number by two and return the rest From d276529d46c747b1ba8c4b5f038067f6264c5ee2 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:06:28 +0000 Subject: [PATCH 124/188] Remove .c_str() calls from parameters to log_file_info() --- frontends/ast/genrtlil.cc | 2 +- frontends/ast/simplify.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 84f2f9d73..7518e4a3e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2195,7 +2195,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int sz = children.size(); if (str == "$info") { if (sz > 0) - log_file_info(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str()); + log_file_info(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str); else log_file_info(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$warning") { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d4e78b730..d249bc8ad 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -161,7 +161,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ arg.sig = node_arg->bitsAsConst(); arg.signed_ = node_arg->is_signed; } else if (may_fail) { - log_file_info(*location.begin.filename, location.begin.line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); + log_file_info(*location.begin.filename, location.begin.line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str, index + 1); return Fmt(); } else { log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str, index + 1); From a1141f1a4c68a2d70829aedc412c2b257734f944 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:12:14 +0000 Subject: [PATCH 125/188] Remove some unnecessary .c_str() calls to the result of unescape_id() --- backends/aiger2/aiger.cc | 2 +- frontends/ast/genrtlil.cc | 8 ++++---- frontends/ast/simplify.cc | 30 +++++++++++++++--------------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index bf7497bb5..6aea97fda 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1012,7 +1012,7 @@ struct XAigerWriter : AigerWriter { for (auto box : minfo.found_blackboxes) { log_debug(" - %s.%s (type %s): ", cursor.path().c_str(), - RTLIL::unescape_id(box->name).c_str(), + RTLIL::unescape_id(box->name), log_id(box->type)); Module *box_module = design->module(box->type), *box_derived; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 7518e4a3e..c26750c98 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1241,7 +1241,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("System function %s called with non-const argument!\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); width_hint = max(width_hint, int(children[0]->asInt(true))); } break; @@ -1291,7 +1291,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (right->simplify(true, 1, -1, false)) { } if (left->type != AST_CONSTANT || right->type != AST_CONSTANT) input_error("Function %s has non-constant width!", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); result_width = abs(int(left->asInt(true) - right->asInt(true))); } width_hint = max(width_hint, result_width); @@ -2237,12 +2237,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (GetSize(children) > 1) input_error("System function %s got %d arguments, expected 1 or 0.\n", - RTLIL::unescape_id(str).c_str(), GetSize(children)); + RTLIL::unescape_id(str), GetSize(children)); if (GetSize(children) == 1) { if (children[0]->type != AST_CONSTANT) input_error("System function %s called with non-const argument!\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); width = children[0]->asInt(true); } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d249bc8ad..cf9d7443e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1915,7 +1915,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (current_scope.at(modname)->type != AST_CELL) input_error("Defparam argument `%s . %s` does not match a cell!\n", - RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); + RTLIL::unescape_id(modname), RTLIL::unescape_id(paramname)); auto paraset = std::make_unique(location, AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : nullptr); paraset->str = paramname; @@ -3394,11 +3394,11 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) != 1 && GetSize(children) != 2) input_error("System function %s got %d arguments, expected 1 or 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); if (!current_always_clocked) input_error("System function %s is only allowed in clocked blocks.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); if (GetSize(children) == 2) { @@ -3469,11 +3469,11 @@ skip_dynamic_range_lvalue_expansion:; { if (GetSize(children) != 1) input_error("System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); if (!current_always_clocked) input_error("System function %s is only allowed in clocked blocks.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); auto present = children.at(0)->clone(); auto past = clone(); @@ -3511,7 +3511,7 @@ skip_dynamic_range_lvalue_expansion:; { if (children.size() != 1) input_error("System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); auto buf = children[0]->clone(); while (buf->simplify(true, stage, width_hint, sign_hint)) { } @@ -3538,11 +3538,11 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$dimensions" || str == "\\$unpacked_dimensions" || str == "\\$bits") { if (children.size() != 1) input_error("System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); } else { if (children.size() != 1 && children.size() != 2) input_error("System function %s got %d arguments, expected 1 or 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); if (children.size() == 2) { auto buf = children[1]->clone(); // Evaluate constant expression @@ -3634,18 +3634,18 @@ skip_dynamic_range_lvalue_expansion:; if (func_with_two_arguments) { if (children.size() != 2) input_error("System function %s got %d arguments, expected 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); } else { if (children.size() != 1) input_error("System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); } if (children.size() >= 1) { while (children[0]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[0]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[0]->detectSignWidth(child_width_hint, child_sign_hint); @@ -3656,7 +3656,7 @@ skip_dynamic_range_lvalue_expansion:; while (children[1]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[1]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str)); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[1]->detectSignWidth(child_width_hint, child_sign_hint); @@ -3703,7 +3703,7 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$countbits") { if (children.size() < 2) input_error("System function %s got %d arguments, expected at least 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); std::vector control_bits; @@ -3760,7 +3760,7 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$countones" || str == "\\$isunknown" || str == "\\$onehot" || str == "\\$onehot0") { if (children.size() != 1) input_error("System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); auto countbits = clone(); countbits->str = "\\$countbits"; @@ -3834,7 +3834,7 @@ skip_dynamic_range_lvalue_expansion:; { if (GetSize(children) < 2 || GetSize(children) > 4) input_error("System function %s got %d arguments, expected 2-4.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str), int(children.size())); auto node_filename = children[0]->clone(); while (node_filename->simplify(true, stage, width_hint, sign_hint)) { } From f80be49fa16dc331039f0148a8282f6bfc08e170 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:14:11 +0000 Subject: [PATCH 126/188] Remove unnecessary .c_str() in EDIF_ macros --- backends/edif/edif.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index d1be0b37f..61d6ee254 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -30,9 +30,9 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str() -#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br).c_str() -#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str() +#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true) +#define EDIF_DEFR(_id, _ren, _bl, _br) edif_names(RTLIL::unescape_id(_id), true, _ren, _bl, _br) +#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false) struct EdifNames { From 64ffcbc3944b5b8fe9b53ad63dd415c9af13e34b Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:26:01 +0000 Subject: [PATCH 127/188] Deprecate logv_file_error() --- kernel/log.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/log.h b/kernel/log.h index 78b202159..16bf96de8 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -119,6 +119,7 @@ extern int log_make_debug; extern int log_force_debug; extern int log_debug_suppressed; +[[deprecated]] [[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); From 5e550ddc3085c1bf524517e45f30b6c4f3ee248f Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 17 Sep 2025 00:22:59 +0000 Subject: [PATCH 128/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 281f5a868..ef63f23ad 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+88 +YOSYS_VER := 0.57+125 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From d24488d3a5539895a652a44ba7f1863c2dc2ef3e Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 17 Sep 2025 03:23:52 +0000 Subject: [PATCH 129/188] Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff() --- backends/verilog/verilog_backend.cc | 8 ++++---- kernel/celledges.cc | 2 +- kernel/cost.cc | 2 +- kernel/ffmerge.cc | 2 +- kernel/functional.cc | 2 +- kernel/rtlil.cc | 10 +++++++++- kernel/rtlil.h | 2 ++ kernel/satgen.cc | 2 +- passes/cmds/check.cc | 4 ++-- passes/cmds/clean_zerowidth.cc | 2 +- passes/cmds/dft_tag.cc | 4 ++-- passes/cmds/future.cc | 2 +- passes/cmds/setundef.cc | 2 +- passes/cmds/timeest.cc | 2 +- passes/cmds/xprop.cc | 4 ++-- passes/equiv/equiv_induct.cc | 2 +- passes/equiv/equiv_simple.cc | 4 ++-- passes/opt/opt_clean.cc | 2 +- passes/opt/opt_dff.cc | 4 ++-- passes/opt/opt_ffinv.cc | 2 +- passes/opt/opt_merge.cc | 6 +++--- passes/sat/async2sync.cc | 2 +- passes/sat/clk2fflogic.cc | 2 +- passes/sat/fmcombine.cc | 2 +- passes/sat/formalff.cc | 16 ++++++++-------- passes/sat/sim.cc | 4 ++-- passes/techmap/abc.cc | 4 ++-- passes/techmap/abc9_ops.cc | 2 +- passes/techmap/clockgate.cc | 2 +- passes/techmap/dfflegalize.cc | 4 ++-- passes/techmap/dffunmap.cc | 2 +- passes/techmap/zinit.cc | 2 +- 32 files changed, 61 insertions(+), 51 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b03639b8d..aea29f710 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -970,7 +970,7 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) + if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { RTLIL::SigSpec sig = cell->getPort(ID::Q); if (GetSize(sig) != 1 || sig.is_fully_const()) @@ -1498,7 +1498,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(nullptr, cell); @@ -1976,7 +1976,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - if (siminit && RTLIL::builtin_ff_cell_types().count(cell->type) && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { + if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { std::stringstream ss; dump_reg_init(ss, cell->getPort(ID::Q)); if (!ss.str().empty()) { @@ -2334,7 +2334,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type) || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) + if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) continue; RTLIL::SigSpec sig = cell->getPort(ID::Q); diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 8e52d0380..c39ced95a 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -447,7 +447,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL return true; } - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { ff_op(this, cell); return true; } diff --git a/kernel/cost.cc b/kernel/cost.cc index 985220f14..29787fa52 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -145,7 +145,7 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) if (design_ && design_->module(cell->type) && cell->parameters.empty()) { log_debug("%s is a module, recurse\n", cell->name.c_str()); return get(design_->module(cell->type)); - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { log_assert(cell->hasPort(ID::Q) && "Weird flip flop"); log_debug("%s is ff\n", cell->name.c_str()); return cell->getParam(ID::WIDTH).as_int(); diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 632cba05c..709549e4d 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -335,7 +335,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) } for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { if (cell->hasPort(ID::D)) { SigSpec d = (*sigmap)(cell->getPort(ID::D)); for (int i = 0; i < GetSize(d); i++) diff --git a/kernel/functional.cc b/kernel/functional.cc index 75c9b580b..2a1bf598a 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -605,7 +605,7 @@ private: } Node node = handle_memory(mem); factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { FfData ff(&ff_initvals, cell); if (!ff.has_gclk) log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 586262f97..2d29dab9f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -87,7 +87,7 @@ static_assert(check_well_known_id_order()); dict RTLIL::constpad; -const pool &RTLIL::builtin_ff_cell_types() { +static const pool &builtin_ff_cell_types_internal() { static const pool res = { ID($sr), ID($ff), @@ -238,6 +238,10 @@ const pool &RTLIL::builtin_ff_cell_types() { return res; } +const pool &RTLIL::builtin_ff_cell_types() { + return builtin_ff_cell_types_internal(); +} + #define check(condition) log_assert(condition && "malformed Const union") const Const::bitvectype& Const::get_bits() const { @@ -4497,6 +4501,10 @@ bool RTLIL::Cell::is_mem_cell() const return type.in(ID($mem), ID($mem_v2)) || has_memid(); } +bool RTLIL::Cell::is_builtin_ff() const { + return builtin_ff_cell_types_internal().count(type) > 0; +} + RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) { wire = bit.wire; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6b4bc0c7d..2d7bf9a9c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -556,6 +556,7 @@ template <> struct IDMacroHelper<-1> { namespace RTLIL { extern dict constpad; + [[deprecated("Call cell->is_builtin_ff() instead")]] const pool &builtin_ff_cell_types(); static inline std::string escape_id(const std::string &str) { @@ -2147,6 +2148,7 @@ public: bool has_memid() const; bool is_mem_cell() const; + bool is_builtin_ff() const; }; struct RTLIL::CaseRule : public RTLIL::AttrObject diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 7885eccf8..f2c1e00c2 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -1202,7 +1202,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (timestep > 0 && (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit))) + if (timestep > 0 && (cell->is_builtin_ff() || cell->type == ID($anyinit))) { FfData ff(nullptr, cell); diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index b532b4527..44dbdf28e 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -285,7 +285,7 @@ struct CheckPass : public Pass { } if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \ - || RTLIL::builtin_ff_cell_types().count(cell->type)) { + || cell->is_builtin_ff()) { if (!edges_db.add_edges_from_cell(cell)) coarsened_cells.insert(cell); } @@ -426,7 +426,7 @@ struct CheckPass : public Pass { { for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0) + if (cell->is_builtin_ff() == 0) continue; for (auto bit : sigmap(cell->getPort(ID::Q))) diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index 021726450..d48d3a958 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -73,7 +73,7 @@ struct CleanZeroWidthPass : public Pass { cell->unsetPort(it.first); } } - } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + } else if (cell->is_builtin_ff()) { // Coarse FF cells: remove if WIDTH == 0 (no outputs). // This will also trigger on fine cells, so use the Q port // width instead of actual WIDTH parameter. diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 5d9756ca0..0a306d113 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -430,7 +430,7 @@ struct DftTagWorker { return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if (ff.has_clk || ff.has_gclk) @@ -686,7 +686,7 @@ struct DftTagWorker { return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); // TODO handle some more variants if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) { diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc index 5dcf46bcf..81cc86bff 100644 --- a/passes/cmds/future.cc +++ b/passes/cmds/future.cc @@ -85,7 +85,7 @@ struct FutureWorker { if (found_driver->second.size() > 1) log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit)); auto driver = *found_driver->second.begin(); - if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit)) + if (!driver.cell->is_builtin_ff() && driver.cell->type != ID($anyinit)) log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type)); FfData ff(&initvals, driver.cell); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 6d3e30561..5d2ccfcc8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -364,7 +364,7 @@ struct SetundefPass : public Pass { for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; for (auto bit : sigmap(cell->getPort(ID::Q))) diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 86a529520..75356610c 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -88,7 +88,7 @@ struct EstimateSta { for (auto cell : m->cells()) { SigSpec launch, sample; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { // collect launch and sample points for FF cell FfData ff(nullptr, cell); if (!ff.has_clk) { diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 8b2e7ae08..7291bb859 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -302,7 +302,7 @@ struct XpropWorker return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if (cell->type != ID($anyinit)) @@ -853,7 +853,7 @@ struct XpropWorker return; } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff(&initvals, cell); if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) { diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index 1995be3cd..e1a3a7990 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -56,7 +56,7 @@ struct EquivInductWorker for (auto cell : cells) { if (!satgen.importCell(cell, step) && !cell_warn_cache.count(cell)) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) log_warning("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); else log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 9e3076077..97f95ac63 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -93,7 +93,7 @@ struct EquivSimpleWorker for (auto &conn : cell->connections()) if (yosys_celltypes.cell_input(cell->type, conn.first)) for (auto bit : model.sigmap(conn.second)) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { if (!conn.first.in(ID::CLK, ID::C)) next_seed.insert(bit); } else @@ -231,7 +231,7 @@ struct EquivSimpleWorker static void report_missing_model(Cell* cell) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) log_cmd_error("No SAT model available for async FF cell %s (%s). Consider running `async2sync` or `clk2fflogic` first.\n", log_id(cell), log_id(cell->type)); else log_cmd_error("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cef2c0dc3..68a2156fb 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -206,7 +206,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (verbose) log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); module->design->scratchpad_set_bool("opt.did_something", true); - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) ffinit.remove_init(cell->getPort(ID::Q)); module->remove(cell); count_rm_cells++; diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index a364539e4..04bcec835 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -89,7 +89,7 @@ struct OptDffWorker } } - if (module->design->selected(module, cell) && RTLIL::builtin_ff_cell_types().count(cell->type)) + if (module->design->selected(module, cell) && cell->is_builtin_ff()) dff_cells.push_back(cell); } @@ -802,7 +802,7 @@ struct OptDffWorker bool did_something = false; for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 882221e56..42d6da49b 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -209,7 +209,7 @@ struct OptFfInvWorker std::vector ffs; for (Cell *cell : module->selected_cells()) - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) ffs.push_back(cell); for (Cell *cell : ffs) { diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index fbfdb9b63..1cb499740 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -110,7 +110,7 @@ struct OptMergeWorker comm.eat(hash_ops>::hash(port, assign_map(sig))); } h = comm.hash_into(h); - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) h = initvals(cell->getPort(ID::Q)).hash_into(h); } return h; @@ -153,7 +153,7 @@ struct OptMergeWorker for (const auto &it : cell1->connections_) { if (cell1->output(it.first)) { - if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell1->type)) { + if (it.first == ID::Q && cell1->is_builtin_ff()) { // For the 'Q' output of state elements, // use the (* init *) attribute value conn1[it.first] = initvals(it.second); @@ -201,7 +201,7 @@ struct OptMergeWorker bool has_dont_care_initval(const RTLIL::Cell *cell) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) return false; return !initvals(cell->getPort(ID::Q)).is_fully_def(); diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index e86a78d81..eb3b154b2 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -129,7 +129,7 @@ struct Async2syncPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index db1eaad4b..dd94dd0d7 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -275,7 +275,7 @@ struct Clk2fflogicPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 2d31822c4..505526c14 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -118,7 +118,7 @@ struct FmcombineWorker Cell *gold = import_prim_cell(cell, "_gold"); Cell *gate = import_prim_cell(cell, "_gate"); if (opts.initeq) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { SigSpec gold_q = gold->getPort(ID::Q); SigSpec gate_q = gate->getPort(ID::Q); SigSpec en = module->Initstate(NEW_ID); diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index c0b0cfc15..452e0e59b 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -92,7 +92,7 @@ struct InitValWorker ModWalker::PortBit portbit = *portbits.begin(); RTLIL::Cell *cell = portbit.cell; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); @@ -224,7 +224,7 @@ struct InitValWorker for (auto portbit : portbits) { RTLIL::Cell *cell = portbit.cell; - if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !cell->is_builtin_ff()) { return true; } } @@ -232,7 +232,7 @@ struct InitValWorker for (auto portbit : portbits) { RTLIL::Cell *cell = portbit.cell; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); if (ff.has_aload || ff.has_sr || ff.has_arst || ff.has_gclk || !ff.has_clk) @@ -641,7 +641,7 @@ struct FormalFfPass : public Pass { pool input_bits; pool> input_clk_bits; for (auto cell : module->selected_cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); if (!ff.has_clk) continue; @@ -743,7 +743,7 @@ struct FormalFfPass : public Pass { auto gate_driver = *found->second.begin(); - if (!RTLIL::builtin_ff_cell_types().count(gate_driver.cell->type)) { + if (!gate_driver.cell->is_builtin_ff()) { log_debug("non FF driver for gate enable %s.%s of gated clk bit %s.%s\n", log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_signal(SigSpec(clk))); continue; @@ -784,7 +784,7 @@ struct FormalFfPass : public Pass { log_debug("rewriting cell %s.%s (%s)\n", log_id(module), log_id(clocked_cell), log_id(clocked_cell->type)); - if (RTLIL::builtin_ff_cell_types().count(clocked_cell->type)) { + if (clocked_cell->is_builtin_ff()) { FfData ff(&initvals, clocked_cell); log_assert(ff.has_clk); @@ -836,7 +836,7 @@ struct FormalFfPass : public Pass { for (auto cell : module->selected_cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) + if (cell->is_builtin_ff()) { FfData ff(&worker.initvals, cell); if (ff.has_aload || ff.has_sr || ff.has_arst || ff.val_init.is_fully_def()) @@ -883,7 +883,7 @@ struct FormalFfPass : public Pass { continue; } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index aadea328f..69c8367c2 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -308,7 +308,7 @@ struct SimInstance } } - if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + if (cell->is_builtin_ff() || cell->type == ID($anyinit)) { FfData ff_data(nullptr, cell); ff_state_t ff; ff.past_d = Const(State::Sx, ff_data.width); @@ -1017,7 +1017,7 @@ struct SimInstance dict registers; for (auto cell : module->cells()) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff_data(nullptr, cell); SigSpec q = sigmap(ff_data.sig_q); if (q.is_wire() && signal_database.count(q.as_wire()) != 0) { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c5bdd6ecf..9ec5e7aae 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -373,7 +373,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig) bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff) { - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (cell->is_builtin_ff()) { FfData ff(&initvals, cell); gate_type_t type = G(FF); if (!ff.has_clk) @@ -2427,7 +2427,7 @@ struct AbcPass : public Pass { } } - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 069b94204..9a9f7dcb5 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -224,7 +224,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) } else if (derived_module->get_bool_attribute(ID::abc9_box)) { for (auto derived_cell : derived_module->cells()) - if (derived_cell->is_mem_cell() || RTLIL::builtin_ff_cell_types().count(derived_cell->type)) { + if (derived_cell->is_mem_cell() || derived_cell->is_builtin_ff()) { derived_module->set_bool_attribute(ID::abc9_box, false); derived_module->set_bool_attribute(ID::abc9_bypass); break; diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index b834b8f35..f4e0b0f03 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -333,7 +333,7 @@ struct ClockgatePass : public Pass { int gated_flop_count = 0; for (auto module : design->selected_unboxed_whole_modules()) { for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(nullptr, cell); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 5a622c611..dc29750c8 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1196,7 +1196,7 @@ unrecognized: srst_used.clear(); for (auto cell : module->cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); @@ -1208,7 +1208,7 @@ unrecognized: } for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); legalize_ff(ff); diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc index 8703bf1a0..020597c4b 100644 --- a/passes/techmap/dffunmap.cc +++ b/passes/techmap/dffunmap.cc @@ -74,7 +74,7 @@ struct DffunmapPass : public Pass { for (auto cell : mod->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index 38936e64d..809651ebd 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -63,7 +63,7 @@ struct ZinitPass : public Pass { for (auto cell : module->selected_cells()) { - if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + if (!cell->is_builtin_ff()) continue; FfData ff(&initvals, cell); From 2d81726459ed15d360d30c75bab8e552b38568a9 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 16 Sep 2025 13:59:15 +0200 Subject: [PATCH 130/188] write_xaiger2: Fix output port mapping when opaque boxes are present --- backends/aiger2/aiger.cc | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c7ed3b81f..36365927c 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -903,6 +903,16 @@ struct XAigerWriter : AigerWriter { typedef std::pair HierBit; std::vector pos; std::vector pis; + + // * The aiger output port sequence is COs (inputs to modeled boxes), + // inputs to opaque boxes, then module outputs. COs going first is + // required by abc. + // * proper_pos_counter counts ports which follow after COs + // * The mapping file `pseudopo` and `po` statements use indexing relative + // to the first port following COs. + // * If a module output is directly driven by an opaque box, the emission + // of the po statement in the mapping file is skipped. This is done to + // aid re-integration of the mapped result. int proper_pos_counter = 0; pool driven_by_opaque_box; @@ -937,7 +947,7 @@ struct XAigerWriter : AigerWriter { lit_counter += 2; } - void append_box_ports(Cell *box, HierCursor &cursor, bool inputs) + void append_opaque_box_ports(Cell *box, HierCursor &cursor, bool inputs) { for (auto &conn : box->connections_) { bool is_input = box->input(conn.first); @@ -955,13 +965,14 @@ struct XAigerWriter : AigerWriter { continue; } + // Inputs to opaque boxes are proper POs as far as abc is concerned if (map_file.is_open()) { log_assert(cursor.is_top()); - map_file << "pseudopo " << proper_pos_counter++ << " " << bitp + map_file << "pseudopo " << proper_pos_counter << " " << bitp << " " << box->name.c_str() << " " << conn.first.c_str() << "\n"; } - + proper_pos_counter++; pos.push_back(std::make_pair(bit, cursor)); if (mapping_prep) @@ -1038,7 +1049,7 @@ struct XAigerWriter : AigerWriter { }); for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, false); + append_opaque_box_ports(box, cursor, false); holes_module = design->addModule(NEW_ID); std::vector holes_pis; @@ -1086,6 +1097,8 @@ struct XAigerWriter : AigerWriter { bit = RTLIL::Sx; } + // Nonopaque box inputs come first and are not part of + // the PO numbering used by the mapping file. pos.push_back(std::make_pair(bit, cursor)); } boxes_co_num += port->width; @@ -1138,7 +1151,7 @@ struct XAigerWriter : AigerWriter { } for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, true); + append_opaque_box_ports(box, cursor, true); write_be32(h_buffer, 1); write_be32(h_buffer, pis.size()); @@ -1195,10 +1208,14 @@ struct XAigerWriter : AigerWriter { for (auto w : top->wires()) if (w->port_output) for (int i = 0; i < w->width; i++) { + // When a module output is directly driven by an opaque box, we + // don't emit it to the mapping file to aid re-integration, but we + // do emit a proper PO. if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) { - map_file << "po " << proper_pos_counter++ << " " << i + map_file << "po " << proper_pos_counter << " " << i << " " << w->name.c_str() << "\n"; } + proper_pos_counter++; pos.push_back(std::make_pair(SigBit(w, i), HierCursor{})); } From 22423b97c10ebae511867b07262cb837f385870c Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 14 Aug 2025 16:13:43 +0200 Subject: [PATCH 131/188] kernel: Add RTLIL::PortDir for a combined input and output flag --- kernel/celltypes.h | 10 ++++++++++ kernel/rtlil.cc | 16 ++++++++++++++++ kernel/rtlil.h | 8 ++++++++ 3 files changed, 34 insertions(+) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 469017029..34592192f 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -320,6 +320,16 @@ struct CellTypes return it != cell_types.end() && it->second.inputs.count(port) != 0; } + RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const + { + auto it = cell_types.find(type); + if (it == cell_types.end()) + return RTLIL::PD_UNKNOWN; + bool is_input = it->second.inputs.count(port); + bool is_output = it->second.outputs.count(port); + return RTLIL::PortDir(is_input + is_output * 2); + } + bool cell_evaluable(const RTLIL::IdString &type) const { auto it = cell_types.find(type); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 2d29dab9f..4e94b8cc1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -4376,6 +4376,22 @@ bool RTLIL::Cell::output(const RTLIL::IdString& portname) const return false; } +RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const +{ + if (yosys_celltypes.cell_known(type)) + return yosys_celltypes.cell_port_dir(type, portname); + if (module && module->design) { + RTLIL::Module *m = module->design->module(type); + if (m == nullptr) + return PortDir::PD_UNKNOWN; + RTLIL::Wire *w = m->wire(portname); + if (w == nullptr) + return PortDir::PD_UNKNOWN; + return PortDir(w->port_input + w->port_output * 2); + } + return PortDir::PD_UNKNOWN; +} + bool RTLIL::Cell::hasParam(const RTLIL::IdString& paramname) const { return parameters.count(paramname) != 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 2d7bf9a9c..4c3e2182e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -91,6 +91,13 @@ namespace RTLIL STATIC_ID_END, }; + enum PortDir : unsigned char { + PD_UNKNOWN = 0, + PD_INPUT = 1, + PD_OUTPUT = 2, + PD_INOUT = 3 + }; + struct Const; struct AttrObject; struct NamedObject; @@ -2123,6 +2130,7 @@ public: bool known() const; bool input(const RTLIL::IdString &portname) const; bool output(const RTLIL::IdString &portname) const; + PortDir port_dir(const RTLIL::IdString &portname) const; // access cell parameters bool hasParam(const RTLIL::IdString ¶mname) const; From c4f435569f6c8d3649ed82d5d2e2588f94b0b6c5 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 3 Sep 2025 15:29:08 +0200 Subject: [PATCH 132/188] kernel: Add known_driver method to Wire/SigSpec --- kernel/rtlil.cc | 9 +++++++++ kernel/rtlil.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 4e94b8cc1..5f8e6ad66 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -5534,6 +5534,15 @@ bool RTLIL::SigSpec::is_chunk() const return GetSize(chunks_) == 1; } +bool RTLIL::SigSpec::known_driver() const +{ + pack(); + for (auto &chunk : chunks_) + if (chunk.is_wire() && !chunk.wire->known_driver()) + return false; + return true; +} + bool RTLIL::SigSpec::is_fully_const() const { cover("kernel.rtlil.sigspec.is_fully_const"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4c3e2182e..15154eb64 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1329,6 +1329,8 @@ public: bool is_chunk() const; inline bool is_bit() const { return width_ == 1; } + bool known_driver() const; + bool is_fully_const() const; bool is_fully_zero() const; bool is_fully_ones() const; @@ -2059,6 +2061,8 @@ public: int width, start_offset, port_id; bool port_input, port_output, upto, is_signed; + bool known_driver() const { return driverCell_ != nullptr; } + RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; }; RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; }; From 1251e92e3a988b33f2075118071f4454247041d6 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 3 Sep 2025 15:26:33 +0200 Subject: [PATCH 133/188] Add `$input_port` and `$connect` cell types --- kernel/celltypes.h | 2 ++ kernel/rtlil.cc | 13 +++++++++++++ techlibs/common/simlib.v | 23 +++++++++++++++++++++++ techlibs/common/techmap.v | 25 +++++++++++++++++++++++++ 4 files changed, 63 insertions(+) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 34592192f..2c3535eac 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -111,6 +111,8 @@ struct CellTypes setup_type(ID($original_tag), {ID::A}, {ID::Y}); setup_type(ID($future_ff), {ID::A}, {ID::Y}); setup_type(ID($scopeinfo), {}, {}); + setup_type(ID($input_port), {}, {ID::Y}); + setup_type(ID($connect), {ID::A, ID::B}, {}); } void setup_internals_eval() diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5f8e6ad66..3858a3372 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2451,6 +2451,19 @@ namespace { check_expected(); return; } + if (cell->type.in(ID($input_port))) { + param(ID::WIDTH); + port(ID::Y, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type.in(ID($connect))) { + param(ID::WIDTH); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH)); + check_expected(); + return; + } /* * Checklist for adding internal cell types * ======================================== diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 6e39aa60a..096df07b9 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -3216,3 +3216,26 @@ module \$scopeinfo (); parameter TYPE = ""; endmodule + +// -------------------------------------------------------- +//* group wire +module \$connect (A, B); + +parameter WIDTH = 0; + +inout [WIDTH-1:0] A; +inout [WIDTH-1:0] B; + +tran connect[WIDTH-1:0] (A, B); + +endmodule + +// -------------------------------------------------------- +//* group wire +module \$input_port (Y); + +parameter WIDTH = 0; + +inout [WIDTH-1:0] Y; + +endmodule diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index fdf11904b..7a9ad7693 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -647,3 +647,28 @@ module _90_lut; endmodule `endif + +// -------------------------------------------------------- +// Bufnorm helpers +// -------------------------------------------------------- + +(* techmap_celltype = "$connect" *) +module \$connect (A, B); + +parameter WIDTH = 0; + +inout [WIDTH-1:0] A; +inout [WIDTH-1:0] B; + +assign A = B; // RTLIL assignments are not inherently directed + +endmodule + +(* techmap_celltype = "$input_port" *) +module \$input_port (Y); + +parameter WIDTH = 0; + +inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven + +endmodule From d88d6fce87442dc3a020fd770a1952f6cedbb192 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 3 Sep 2025 15:34:51 +0200 Subject: [PATCH 134/188] kernel: Rewrite bufNormalize This is a complete rewrite of the RTLIL-kernel-side bufnorm code. This is done to support inout ports and undirected connections as well as to allow removal of cells while in bufnorm mode. This doesn't yet update the (experimental) `bufnorm` pass, so to manually test the new kernel functionality, it is important to only use `bufnorm -update` and `bufnorm -reset` which rely entirely on the kernel functionality. Other modes of the `bufnorm` pass may still fail in the presence of inout ports or undirected connections. --- Makefile | 1 + kernel/rtlil.cc | 211 ++----------- kernel/rtlil.h | 7 +- kernel/rtlil_bufnorm.cc | 679 ++++++++++++++++++++++++++++++++++++++++ tests/various/aiger2.ys | 2 + 5 files changed, 716 insertions(+), 184 deletions(-) create mode 100644 kernel/rtlil_bufnorm.cc diff --git a/Makefile b/Makefile index ef63f23ad..3e0849c09 100644 --- a/Makefile +++ b/Makefile @@ -644,6 +644,7 @@ $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o +OBJS += kernel/rtlil_bufnorm.o OBJS += kernel/log_help.o ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1) OBJS += kernel/log_compat.o diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3858a3372..4f34d6f7b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2844,7 +2844,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell) log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); cells_.erase(cell->name); - delete cell; + if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) { + cell->type.clear(); + cell->name.clear(); + pending_deleted_cells.insert(cell); + } else { + delete cell; + } } void RTLIL::Module::remove(RTLIL::Process *process) @@ -3019,6 +3025,14 @@ void RTLIL::Module::fixup_ports() std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare); + if (design && design->flagBufferedNormalized) { + for (auto &w : wires_) + if (w.second->driverCell_ && w.second->driverCell_->type == ID($input_port)) + buf_norm_wire_queue.insert(w.second); + + buf_norm_wire_queue.insert(all_ports.begin(), all_ports.end()); + } + ports.clear(); for (size_t i = 0; i < all_ports.size(); i++) { ports.push_back(all_ports[i]->name); @@ -4163,188 +4177,7 @@ bool RTLIL::Cell::hasPort(const RTLIL::IdString& portname) const return connections_.count(portname) != 0; } -void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) -{ - RTLIL::SigSpec signal; - auto conn_it = connections_.find(portname); - - if (conn_it != connections_.end()) - { - for (auto mon : module->monitors) - mon->notify_connect(this, conn_it->first, conn_it->second, signal); - - if (module->design) - for (auto mon : module->design->monitors) - mon->notify_connect(this, conn_it->first, conn_it->second, signal); - - if (yosys_xtrace) { - log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname)); - log_backtrace("-X- ", yosys_xtrace-1); - } - - connections_.erase(conn_it); - } -} - -void RTLIL::Design::bufNormalize(bool enable) -{ - if (!enable) - { - if (!flagBufferedNormalized) - return; - - for (auto module : modules()) { - module->bufNormQueue.clear(); - for (auto wire : module->wires()) { - wire->driverCell_ = nullptr; - wire->driverPort_ = IdString(); - } - } - - flagBufferedNormalized = false; - return; - } - - if (!flagBufferedNormalized) - { - for (auto module : modules()) - { - for (auto cell : module->cells()) - for (auto &conn : cell->connections()) { - if (!cell->output(conn.first) || GetSize(conn.second) == 0) - continue; - if (conn.second.is_wire()) { - Wire *wire = conn.second.as_wire(); - log_assert(wire->driverCell_ == nullptr); - wire->driverCell_ = cell; - wire->driverPort_ = conn.first; - } else { - pair key(cell, conn.first); - module->bufNormQueue.insert(key); - } - } - } - - flagBufferedNormalized = true; - } - - for (auto module : modules()) - module->bufNormalize(); -} - -void RTLIL::Module::bufNormalize() -{ - if (!design->flagBufferedNormalized) - return; - - while (GetSize(bufNormQueue) || !connections_.empty()) - { - pool> queue; - bufNormQueue.swap(queue); - - pool outWires; - for (auto &conn : connections()) - for (auto &chunk : conn.first.chunks()) - if (chunk.wire) outWires.insert(chunk.wire); - - SigMap sigmap(this); - new_connections({}); - - for (auto &key : queue) - { - Cell *cell = key.first; - const IdString &portname = key.second; - const SigSpec &sig = cell->getPort(portname); - if (GetSize(sig) == 0) continue; - - if (sig.is_wire()) { - Wire *wire = sig.as_wire(); - if (wire->driverCell_) { - log_error("Conflict between %s %s in module %s\n", - log_id(cell), log_id(wire->driverCell_), log_id(this)); - } - log_assert(wire->driverCell_ == nullptr); - wire->driverCell_ = cell; - wire->driverPort_ = portname; - continue; - } - - for (auto &chunk : sig.chunks()) - if (chunk.wire) outWires.insert(chunk.wire); - - Wire *wire = addWire(NEW_ID, GetSize(sig)); - sigmap.add(sig, wire); - cell->setPort(portname, wire); - - // FIXME: Move init attributes from old 'sig' to new 'wire' - } - - for (auto wire : outWires) - { - SigSpec outsig = wire, insig = sigmap(wire); - for (int i = 0; i < GetSize(wire); i++) - if (insig[i] == outsig[i]) - insig[i] = State::Sx; - addBuf(NEW_ID, insig, outsig); - } - } -} - -void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal) -{ - auto r = connections_.insert(portname); - auto conn_it = r.first; - if (!r.second && conn_it->second == signal) - return; - - for (auto mon : module->monitors) - mon->notify_connect(this, conn_it->first, conn_it->second, signal); - - if (module->design) - for (auto mon : module->design->monitors) - mon->notify_connect(this, conn_it->first, conn_it->second, signal); - - if (yosys_xtrace) { - log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal)); - log_backtrace("-X- ", yosys_xtrace-1); - } - - while (module->design && module->design->flagBufferedNormalized && output(portname)) - { - pair key(this, portname); - - if (conn_it->second.is_wire()) { - Wire *w = conn_it->second.as_wire(); - if (w->driverCell_ == this && w->driverPort_ == portname) { - w->driverCell_ = nullptr; - w->driverPort_ = IdString(); - } - } - - if (GetSize(signal) == 0) { - module->bufNormQueue.erase(key); - break; - } - - if (!signal.is_wire()) { - module->bufNormQueue.insert(key); - break; - } - - Wire *w = signal.as_wire(); - if (w->driverCell_ != nullptr) { - pair other_key(w->driverCell_, w->driverPort_); - module->bufNormQueue.insert(other_key); - } - w->driverCell_ = this; - w->driverPort_ = portname; - - module->bufNormQueue.erase(key); - break; - } - - conn_it->second = std::move(signal); -} +// bufnorm const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString& portname) const { @@ -5638,6 +5471,18 @@ bool RTLIL::SigSpec::has_const() const return false; } +bool RTLIL::SigSpec::has_const(State state) const +{ + cover("kernel.rtlil.sigspec.has_const"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) + if (it->width > 0 && it->wire == NULL && std::find(it->data.begin(), it->data.end(), state) != it->data.end()) + return true; + return false; +} + + bool RTLIL::SigSpec::has_marked_bits() const { cover("kernel.rtlil.sigspec.has_marked_bits"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 15154eb64..096d1dfcf 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1337,6 +1337,7 @@ public: bool is_fully_def() const; bool is_fully_undef() const; bool has_const() const; + bool has_const(State state) const; bool has_marked_bits() const; bool is_onehot(int *pos = nullptr) const; @@ -1728,7 +1729,11 @@ public: std::vector ports; void fixup_ports(); - pool> bufNormQueue; + pool buf_norm_cell_queue; + pool> buf_norm_cell_port_queue; + pool buf_norm_wire_queue; + pool pending_deleted_cells; + dict> buf_norm_connect_index; void bufNormalize(); template void rewrite_sigspecs(T &functor); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc new file mode 100644 index 000000000..6d619d9e6 --- /dev/null +++ b/kernel/rtlil_bufnorm.cc @@ -0,0 +1,679 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/modtools.h" + +#include +#include +#include + +YOSYS_NAMESPACE_BEGIN + + +void RTLIL::Design::bufNormalize(bool enable) +{ + if (!enable) + { + if (!flagBufferedNormalized) + return; + + for (auto module : modules()) { + module->buf_norm_cell_queue.clear(); + module->buf_norm_wire_queue.clear(); + module->buf_norm_cell_port_queue.clear(); + for (auto wire : module->wires()) { + wire->driverCell_ = nullptr; + wire->driverPort_ = IdString(); + } + } + + flagBufferedNormalized = false; + return; + } + + if (!flagBufferedNormalized) + { + for (auto module : modules()) + { + // When entering buf normalized mode, we need the first module-level bufNormalize + // call to know about all drivers, about all module ports (whether represented by + // a cell or not) and about all used but undriven wires (whether represented by a + // cell or not). We ensure this by enqueing all cell output ports and all wires. + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + if (GetSize(conn.second) == 0 || (cell->port_dir(conn.first) != RTLIL::PD_OUTPUT && cell->port_dir(conn.first) != RTLIL::PD_INOUT)) + continue; + module->buf_norm_cell_queue.insert(cell); + module->buf_norm_cell_port_queue.emplace(cell, conn.first); + } + for (auto wire : module->wires()) + module->buf_norm_wire_queue.insert(wire); + + } + + flagBufferedNormalized = true; + } + + for (auto module : modules()) + module->bufNormalize(); +} + +struct bit_drive_data_t { + int drivers = 0; + int inout = 0; + int users = 0; +}; + +typedef ModWalker::PortBit PortBit; + +void RTLIL::Module::bufNormalize() +{ + // Since this is kernel code, we only log with yosys_xtrace set to not get + // in the way when using `debug` to debug specific passes.q +#define xlog(...) do { if (yosys_xtrace) log("#X [bufnorm] " __VA_ARGS__); } while (0) + + if (!design->flagBufferedNormalized) + return; + + if (!buf_norm_cell_queue.empty() || !buf_norm_wire_queue.empty() || !connections_.empty()) + { + // Ensure that every enqueued input port is represented by a cell + for (auto wire : buf_norm_wire_queue) { + if (wire->port_input && !wire->port_output) { + if (wire->driverCell_ != nullptr && wire->driverCell_->type != ID($input_port)) { + wire->driverCell_ = nullptr; + wire->driverPort_.clear(); + } + if (wire->driverCell_ == nullptr) { + Cell *input_port_cell = addCell(NEW_ID, ID($input_port)); + input_port_cell->setParam(ID::WIDTH, GetSize(wire)); + input_port_cell->setPort(ID::Y, wire); // this hits the fast path that doesn't mutate the queues + } + } + } + + // Next we will temporarily undo buf normalization locally for + // everything enqueued. This means we will turn $buf and $connect back + // into connections. When doing this we also need to enqueue the other + // end of $buf and $connect cells, so we use a queue and do this until + // reaching a fixed point. + + // While doing this, we will also discover all drivers fully connected + // to enqueued wires. We keep track of which wires are driven by a + // unique and full cell ports (in which case the wire can stay + // connected to the port) and which cell ports will need to be + // reconnected to a fresh intermediate wire to re-normalize the module. + + idict wire_queue_entries; // Ordered queue of wires to process + int wire_queue_pos = 0; // Index up to which we processed the wires + + // Wires with their unique driving cell port. If we know a wire is + // driven by multiple (potential) drivers, this is indicated by a + // nullptr as cell. + dict> direct_driven_wires; + + // Set of non-unique or driving cell ports for each processed wire. + dict>> direct_driven_wires_conflicts; + + // Set of cell ports that need a fresh intermediate wire. + pool> pending_ports; + + // This helper will be called for every output/inout cell port that is + // already enqueued or becomes reachable when denormalizing $buf or + // $connect cells. + auto enqueue_cell_port = [&](Cell *cell, IdString port) { + xlog("processing cell port %s.%s\n", log_id(cell), log_id(port)); + + // An empty cell type means the cell got removed + if (cell->type.empty()) + return; + + + SigSpec const &sig = cell->getPort(port); + if (cell->type == ID($input_port)) { + // If an `$input_port` cell isn't fully connected to a full + // input port wire, we remove it since the wires are still the + // canonical source of module ports and the `$input_port` cells + // are just helpers to simplfiy the bufnorm invariant. + log_assert(port == ID::Y); + if (!sig.is_wire()) { + buf_norm_cell_queue.insert(cell); + remove(cell); + return; + } + + Wire *w = sig.as_wire(); + if (!w->port_input || w->port_output) { + buf_norm_cell_queue.insert(cell); + remove(cell); + return; + } + w->driverCell_ = cell; + w->driverPort_ = ID::Y; + } else if (cell->type == ID($buf) && cell->attributes.empty() && !cell->name.isPublic()) { + // For a plain `$buf` cell, we enqueue all wires on its input + // side, bypass it using module level connections (skipping 'z + // bits) and then remove the cell. Eventually the module level + // connections will turn back into `$buf` and `$connect` cells, + // but since we also need to handle externally added module + // level connections, turning everything into connections first + // simplifies the logic for doing so. + + // TODO: We could defer removing the $buf cells here, and + // re-use them in case we would create a new identical cell + // later. + log_assert(port == ID::Y); + SigSpec sig_a = cell->getPort(ID::A); + SigSpec sig_y = sig; + + for (auto const &s : {sig_a, sig}) + for (auto const &chunk : s.chunks()) + if (chunk.wire) + wire_queue_entries(chunk.wire); + + if (sig_a.has_const(State::Sz)) { + SigSpec new_a; + SigSpec new_y; + for (int i = 0; i < GetSize(sig_a); ++i) { + SigBit b = sig_a[i]; + if (b == State::Sz) + continue; + new_a.append(b); + new_y.append(sig_y[i]); + } + sig_a = std::move(new_a); + sig_y = std::move(new_y); + } + + if (!sig_y.empty()) + connect(sig_y, sig_a); + buf_norm_cell_queue.insert(cell); + remove(cell); + return; + } + + // Make sure all wires of the cell port are enqueued, ensuring we + // detect other connected drivers (output and inout). + for (auto const &chunk : sig.chunks()) + if (chunk.wire) + wire_queue_entries(chunk.wire); + + if (sig.is_wire()) { + // If the full cell port is connected to a full wire, we might be + // able to keep that connection if this is a unique output port driving that wire + Wire *w = sig.as_wire(); + + // We try to store the current port as unique driver, if this + // succeeds we're done with the port. + auto [found, inserted] = direct_driven_wires.emplace(w, {cell, port}); + if (inserted || (found->second.first == cell && found->second.second == port)) + return; + + // When this failed, we store this port as a conflict. If we + // had already stored a candidate for a unique driver, we also + // move it to the conflicts, leaving a nullptr marker. + + auto &conflicts = direct_driven_wires_conflicts[w]; + if (Cell *other_cell = found->second.first) { + if (other_cell->type == ID($input_port)) { + // Multiple input port cells + log_assert(cell->type != ID($input_port)); + } else { + pending_ports.insert(found->second); + conflicts.emplace(found->second); + found->second = {nullptr, {}}; + } + } + if (cell->type == ID($input_port)) { + found->second = {cell, port}; + } else { + conflicts.emplace(cell, port); + } + } + + // Adds this port to the ports that need a fresh intermediate wire. + // For full wires uniquely driven by a full output port, this isn't + // reached due to the `return` above. + pending_ports.emplace(cell, port); + }; + + // We process all explicitly enqueued cell ports (clearing the module level queue). + for (auto const &[cell, port_name] : buf_norm_cell_port_queue) + enqueue_cell_port(cell, port_name); + buf_norm_cell_port_queue.clear(); + + // And enqueue all wires for `$buf`/`$connect` processing (clearing the module level queue). + for (auto wire : buf_norm_wire_queue) + wire_queue_entries(wire); + buf_norm_wire_queue.clear(); + + // We also enqueue all wires that saw newly added module level connections. + for (auto &[a, b] : connections_) + for (auto &sig : {a, b}) + for (auto const &chunk : sig.chunks()) + if (chunk.wire) + wire_queue_entries(chunk.wire); + + // We then process all wires by processing known driving cell ports + // (previously buf normalized) and following all `$connect` cells (that + // have a dedicated module level index while the design is in buf + // normalized mode). + while (wire_queue_pos < GetSize(wire_queue_entries)) { + auto wire = wire_queue_entries[wire_queue_pos++]; + xlog("processing wire %s\n", log_id(wire)); + + if (wire->driverCell_) { + Cell *cell = wire->driverCell_; + IdString port = wire->driverPort_; + enqueue_cell_port(cell, port); + } + + while (true) { + auto found = buf_norm_connect_index.find(wire); + if (found == buf_norm_connect_index.end()) + break; + while (!found->second.empty()) { + Cell *connect_cell = *found->second.begin(); + log_assert(connect_cell->type == ID($connect)); + SigSpec const &sig_a = connect_cell->getPort(ID::A); + SigSpec const &sig_b = connect_cell->getPort(ID::B); + xlog("found $connect cell %s: %s <-> %s\n", log_id(connect_cell), log_signal(sig_a), log_signal(sig_b)); + for (auto &side : {sig_a, sig_b}) + for (auto chunk : side.chunks()) + if (chunk.wire) + wire_queue_entries(chunk.wire); + connect(sig_a, sig_b); + buf_norm_cell_queue.insert(connect_cell); + remove(connect_cell); + } + } + } + + // At this point we know all cell ports and wires that need to be + // re-normalized and know their connectivity is represented by module + // level connections. + + // As a first step for re-normalization we add all require intermediate + // wires for cell output and inout ports. + for (auto &[cell, port] : pending_ports) { + SigSpec const &sig = cell->getPort(port); + Wire *w = addWire(NEW_ID, GetSize(sig)); + + // We update the module level connections, `direct_driven_wires` + // and `direct_driven_wires_conflicts` in such a way that they + // correspond to what you would get if the intermediate wires had + // been in place from the beginning. + connect(sig, w); + auto port_dir = cell->port_dir(port); + if (port_dir == RTLIL::PD_INOUT || port_dir == RTLIL::PD_UNKNOWN) { + direct_driven_wires.emplace(w, {nullptr, {}}); + direct_driven_wires_conflicts[w].emplace(cell, port); + } else { + direct_driven_wires.emplace(w, {cell, port}); + } + + cell->setPort(port, w); + wire_queue_entries(w); + } + + // At this point we're done with creating wires and know which ones are + // fully driven by full output ports of existing cells. + + // First we clear the bufnorm data for all processed wires, all of + // these will be reassigned later, but we use `driverCell_ == nullptr` + // to keep track of the wires that we still have to update. + for (auto wire : wire_queue_entries) { + wire->driverCell_ = nullptr; + wire->driverPort_.clear(); + } + + // For the unique output cell ports fully connected to a full wire, we + // can update the bufnorm data right away. For all other wires we will + // have to create new `$buf` cells. + for (auto const &[wire, cellport] : direct_driven_wires) { + wire->driverCell_ = cellport.first; + wire->driverPort_ = cellport.second; + } + + + // To create fresh `$buf` cells for all remaining wires, we need to + // process the module level connectivity to figure out what the input + // of those `$buf` cells should be and to figure out whether we need + // any `$connect` cells to represent bidirectional inout connections + // (or driver conflicts). + + if (yosys_xtrace) + for (auto const &[lhs, rhs] : connections_) + xlog("connection %s <-> %s\n", log_signal(lhs), log_signal(rhs)); + + + // We transfer the connectivity into a sigmap and then clear the module + // level connections. This forgets about the structure of module level + // connections, but bufnorm only guarantees that the connectivity as + // maintained by a `SigMap` is preserved. + SigMap sigmap(this); + new_connections({}); + + pool conflicted; + pool driven; + + // We iterate over all direct driven wires and try to make that wire's + // sigbits the representative sigbit for the net. We do a second pass + // to detect conflicts to then remove the conflicts from `driven`. + for (bool check : {false, true}) { + for (auto const &[wire, cellport] : direct_driven_wires) { + if (cellport.first == nullptr) + continue; + auto const &[cell, port] = cellport; + + SigSpec z_mask; + if (cell->type == ID($buf)) + z_mask = cell->getPort(ID::A); + + for (int i = 0; i != GetSize(wire); ++i) { + SigBit driver = SigBit(wire, i); + if (!z_mask.empty() && z_mask[i] == State::Sz) + continue; + if (check) { + SigBit repr = sigmap(driver); + if (repr != driver) + conflicted.insert(repr); + else + driven.insert(repr); + } else { + sigmap.database.promote(driver); + } + } + } + } + + // Ensure that module level inout ports are directly driven or + // connected using `$connect` cells and never `$buf`fered. + for (auto wire : wire_queue_entries) { + if (!wire->port_input || !wire->port_output) + continue; + for (int i = 0; i != GetSize(wire); ++i) { + SigBit driver = SigBit(wire, i); + SigBit repr = sigmap(driver); + if (driver != repr) + driven.erase(repr); + } + } + + for (auto &bit : conflicted) + driven.erase(bit); + + // Module level bitwise connections not representable by `$buf` cells + pool> undirected_connections; + + // Starts out empty but is updated with the connectivity realized by freshly added `$buf` cells + SigMap buf_connected; + + // For every enqueued wire, we compute a SigSpec of representative + // drivers. If there are any bits without a unique driver we represent + // that with `Sz`. If there are multiple drivers for a net, they become + // connected via `$connect` cells but every wire of the net has the + // corresponding bit still driven by a buffered `Sz`. + for (auto wire : wire_queue_entries) { + SigSpec wire_drivers; + for (int i = 0; i < GetSize(wire); ++i) { + SigBit bit(wire, i); + SigBit mapped = sigmap(bit); + xlog("bit %s -> mapped %s\n", log_signal(bit), log_signal(mapped)); + + + buf_connected.apply(bit); + buf_connected.add(bit, mapped); + buf_connected.database.promote(mapped); + + if (wire->driverCell_ == nullptr) { + if (!mapped.is_wire() || driven.count(mapped)) { + wire_drivers.append(mapped); + continue; + } else { + wire_drivers.append(State::Sz); + } + } + + if (bit < mapped) + undirected_connections.emplace(bit, mapped); + else if (mapped < bit) + undirected_connections.emplace(mapped, bit); + } + + if (wire->driverCell_ == nullptr) { + xlog("wire %s drivers %s\n", log_id(wire), log_signal(wire_drivers)); + addBuf(NEW_ID, wire_drivers, wire); + } + } + + // Finally we group the bitwise connections to emit word-level $connect cells + + static auto sort_key = [](std::pair const &p) { + int first_offset = p.first.is_wire() ? p.first.offset : 0; + int second_offset = p.second.is_wire() ? p.second.offset : 0; + return std::make_tuple(p.first.wire, p.second.wire, first_offset - second_offset, p); + }; + + undirected_connections.sort([](std::pair const &p, std::pair const &q) { + return sort_key(p) < sort_key(q); + }); + + SigSpec tmp_a, tmp_b; + + for (auto &[bit_a, bit_b] : undirected_connections) { + tmp_a.append(bit_a); + tmp_b.append(bit_b); + } + + xlog("LHS: %s\n", log_signal(tmp_a)); + xlog("RHS: %s\n", log_signal(tmp_b)); + + + SigSpec sig_a, sig_b; + SigBit next_a, next_b; + + auto emit_connect_cell = [&]() { + if (sig_a.empty()) + return; + xlog("connect %s <-> %s\n", log_signal(sig_a), log_signal(sig_b)); + Cell *connect_cell = addCell(NEW_ID, ID($connect)); + connect_cell->setParam(ID::WIDTH, GetSize(sig_a)); + connect_cell->setPort(ID::A, sig_a); + connect_cell->setPort(ID::B, sig_b); + sig_a = SigSpec(); + sig_b = SigSpec(); + }; + + for (auto &[bit_a, bit_b] : undirected_connections) { + if (bit_a == bit_b) + continue; + if (bit_a != next_a || bit_b != next_b) + emit_connect_cell(); + + sig_a.append(bit_a); + sig_b.append(bit_b); + next_a = bit_a; + next_b = bit_b; + if (next_a.is_wire()) + next_a.offset++; + if (next_b.is_wire()) + next_b.offset++; + + } + emit_connect_cell(); + + buf_norm_cell_queue.clear(); + + log_assert(buf_norm_cell_port_queue.empty()); + log_assert(buf_norm_wire_queue.empty()); + log_assert(connections_.empty()); + } + + for (auto cell : pending_deleted_cells) { + delete cell; + } + pending_deleted_cells.clear(); +} + +void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) +{ + RTLIL::SigSpec signal; + auto conn_it = connections_.find(portname); + + if (conn_it != connections_.end()) + { + for (auto mon : module->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); + + if (module->design) + for (auto mon : module->design->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); + + if (yosys_xtrace) { + log("#X# Unconnect %s.%s.%s\n", log_id(this->module), log_id(this), log_id(portname)); + log_backtrace("-X- ", yosys_xtrace-1); + } + + if (module->design && module->design->flagBufferedNormalized) { + if (conn_it->second.is_wire()) { + Wire *w = conn_it->second.as_wire(); + if (w->driverCell_ == this && w->driverPort_ == portname) { + w->driverCell_ = nullptr; + w->driverPort_ = IdString(); + module->buf_norm_wire_queue.insert(w); + } + } + + if (type == ID($connect)) { + for (auto &[port, sig] : connections_) { + for (auto &chunk : sig.chunks()) { + if (!chunk.wire) + continue; + auto it = module->buf_norm_connect_index.find(chunk.wire); + if (it == module->buf_norm_connect_index.end()) + continue; + it->second.erase(this); + if (it->second.empty()) + module->buf_norm_connect_index.erase(it); + } + } + connections_.erase(conn_it); + for (auto &[port, sig] : connections_) { + for (auto &chunk : sig.chunks()) { + if (!chunk.wire) + continue; + module->buf_norm_connect_index[chunk.wire].insert(this); + } + } + return; + } + } + + connections_.erase(conn_it); + } +} + +void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal) +{ + auto r = connections_.insert(portname); + auto conn_it = r.first; + if (!r.second && conn_it->second == signal) + return; + + for (auto mon : module->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); + + if (module->design) + for (auto mon : module->design->monitors) + mon->notify_connect(this, conn_it->first, conn_it->second, signal); + + if (yosys_xtrace) { + log("#X# Connect %s.%s.%s = %s (%d)\n", log_id(this->module), log_id(this), log_id(portname), log_signal(signal), GetSize(signal)); + log_backtrace("-X- ", yosys_xtrace-1); + } + + if (module->design && module->design->flagBufferedNormalized) + { + // We eagerly clear a driver that got disconnected by changing this port connection + if (conn_it->second.is_wire()) { + Wire *w = conn_it->second.as_wire(); + if (w->driverCell_ == this && w->driverPort_ == portname) { + w->driverCell_ = nullptr; + w->driverPort_ = IdString(); + module->buf_norm_wire_queue.insert(w); + } + } + + auto dir = port_dir(portname); + // This is a fast path that handles connecting a full driverless wire to an output port, + // everything else is goes through the bufnorm queues and is handled during the next + // bufNormalize call + if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) { + Wire *w = signal.as_wire(); + if (w->driverCell_ == nullptr) { + w->driverCell_ = this; + w->driverPort_ = portname; + + conn_it->second = std::move(signal); + return; + } + } + + if (dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) { + module->buf_norm_cell_queue.insert(this); + module->buf_norm_cell_port_queue.emplace(this, portname); + } else { + for (auto &chunk : signal.chunks()) + if (chunk.wire != nullptr && chunk.wire->driverCell_ == nullptr) + module->buf_norm_wire_queue.insert(chunk.wire); + } + + if (type == ID($connect)) { + for (auto &[port, sig] : connections_) { + for (auto &chunk : sig.chunks()) { + if (!chunk.wire) + continue; + auto it = module->buf_norm_connect_index.find(chunk.wire); + if (it == module->buf_norm_connect_index.end()) + continue; + it->second.erase(this); + if (it->second.empty()) + module->buf_norm_connect_index.erase(it); + } + } + conn_it->second = std::move(signal); + for (auto &[port, sig] : connections_) { + for (auto &chunk : sig.chunks()) { + if (!chunk.wire) + continue; + module->buf_norm_connect_index[chunk.wire].insert(this); + } + } + return; + } + } + conn_it->second = std::move(signal); + +} + +YOSYS_NAMESPACE_END diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index d2b024d2f..6f6958141 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -157,6 +157,7 @@ splitnets -ports copy test gold flatten gold techmap submodule1 +opt_clean select test write_aiger2 -flatten aiger2_ops.aig select -clear @@ -216,6 +217,7 @@ prep -top top techmap t:$add splitnets -ports top +opt_clean write_aiger2 -flatten aiger2_flatten.aig flatten rename top gold From 5f79a6e868118bb9f91a3d72f23621a5b1f40f90 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 3 Sep 2025 15:36:42 +0200 Subject: [PATCH 135/188] Clean up $buf with 'z inputs, $input_port and $connect cells This ensures that entering and leaving bufnorm followed by `opt_clean` is equivalent to just running `opt_clean`. Also make sure that 'z-$buf cells get techmapped in a compatible way. --- passes/opt/opt_clean.cc | 29 +++++++++++++++++++++++++++-- passes/techmap/simplemap.cc | 17 ++++++++++++++++- 2 files changed, 43 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d9bd4c027..a254dc915 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -600,15 +600,40 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool log("Finding unused cells or wires in module %s..\n", module->name); std::vector delcells; - for (auto cell : module->cells()) + for (auto cell : module->cells()) { if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) { bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool(); RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec y = cell->getPort(ID::Y); a.extend_u0(GetSize(y), is_signed); - module->connect(y, a); + + if (a.has_const(State::Sz)) { + SigSpec new_a; + SigSpec new_y; + for (int i = 0; i < GetSize(a); ++i) { + SigBit b = a[i]; + if (b == State::Sz) + continue; + new_a.append(b); + new_y.append(y[i]); + } + a = std::move(new_a); + y = std::move(new_y); + } + if (!y.empty()) + module->connect(y, a); + delcells.push_back(cell); + } else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) { + RTLIL::SigSpec a = cell->getPort(ID::A); + RTLIL::SigSpec b = cell->getPort(ID::B); + if (a.has_const() && !b.has_const()) + std::swap(a, b); + module->connect(a, b); + delcells.push_back(cell); + } else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) { delcells.push_back(cell); } + } for (auto cell : delcells) { if (verbose) log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(), diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index b23985770..ddfd7e03e 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -47,7 +47,22 @@ void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_y = cell->getPort(ID::Y); - module->connect(RTLIL::SigSig(sig_y, sig_a)); + if (sig_a.has_const(State::Sz)) { + SigSpec new_a; + SigSpec new_y; + for (int i = 0; i < GetSize(sig_a); ++i) { + SigBit b = sig_a[i]; + if (b == State::Sz) + continue; + new_a.append(b); + new_y.append(sig_y[i]); + } + sig_a = std::move(new_a); + sig_y = std::move(new_y); + } + + if (!sig_y.empty()) + module->connect(RTLIL::SigSig(sig_y, sig_a)); } void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) From 4918f37be3787045709ce9bd68bcaf25417632e1 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 16 Sep 2025 14:01:15 +0200 Subject: [PATCH 136/188] write_aiger2: Treat inout ports as output ports With the previous bufnorm implementation inout ports were not supported at all, so this didn't matter, but with the new bufnorm implementation they need to be treated as output ports. --- backends/aiger2/aiger.cc | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 956e9c43a..fad73ba9b 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -566,7 +566,7 @@ struct Index { } Lit ret; - if (!bit.wire->port_input) { + if (!bit.wire->port_input || bit.wire->port_output) { // an output of a cell Cell *driver = bit.wire->driverCell(); @@ -618,7 +618,7 @@ struct Index { if (!cursor) { log_assert(bit.wire->module == top); - log_assert(bit.wire->port_input); + log_assert(bit.wire->port_input && !bit.wire->port_output); return lits[top_minfo->windices[bit.wire] + bit.offset]; } else { log_assert(bit.wire->module == cursor->leaf_module(*this)); @@ -723,7 +723,7 @@ struct AigerWriter : Index { for (auto id : top->ports) { Wire *w = top->wire(id); log_assert(w); - if (w->port_input) + if (w->port_input && !w->port_output) for (int i = 0; i < w->width; i++) { pi_literal(SigBit(w, i)) = lit_counter; inputs.push_back(SigBit(w, i)); @@ -828,7 +828,7 @@ struct XAigerAnalysis : Index { { log_assert(cursor.is_top()); // TOOD: fix analyzer to work with hierarchy - if (bit.wire->port_input) + if (bit.wire->port_input && !bit.wire->port_output) return false; Cell *driver = bit.wire->driverCell(); @@ -838,7 +838,7 @@ struct XAigerAnalysis : Index { int max = 1; for (auto wire : mod->wires()) - if (wire->port_input) + if (wire->port_input && !wire->port_output) for (int i = 0; i < wire->width; i++) { int ilevel = visit(cursor, driver->getPort(wire->name)[i]); max = std::max(max, ilevel + 1); @@ -858,7 +858,7 @@ struct XAigerAnalysis : Index { for (auto id : top->ports) { Wire *w = top->wire(id); log_assert(w); - if (w->port_input) + if (w->port_input && !w->port_output) for (int i = 0; i < w->width; i++) pi_literal(SigBit(w, i)) = 0; } @@ -868,7 +868,7 @@ struct XAigerAnalysis : Index { Module *def = design->module(box->type); if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) - if (box->output(conn.first)) + if (box->port_dir(conn.first) != RTLIL::PD_INPUT) for (auto bit : conn.second) pi_literal(bit, &cursor) = 0; } @@ -883,7 +883,7 @@ struct XAigerAnalysis : Index { Module *def = design->module(box->type); if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) - if (box->input(conn.first)) + if (box->port_dir(conn.first) == RTLIL::PD_INPUT) for (auto bit : conn.second) (void) eval_po(bit); } @@ -950,12 +950,7 @@ struct XAigerWriter : AigerWriter { void append_opaque_box_ports(Cell *box, HierCursor &cursor, bool inputs) { for (auto &conn : box->connections_) { - bool is_input = box->input(conn.first); - bool is_output = box->output(conn.first); - - if (!(is_input || is_output) || (is_input && is_output)) - log_error("Ambiguous port direction on %s/%s\n", - log_id(box->type), log_id(conn.first)); + bool is_input = box->port_dir(conn.first) == RTLIL::PD_INPUT; if (is_input && inputs) { int bitp = 0; @@ -980,10 +975,10 @@ struct XAigerWriter : AigerWriter { bitp++; } - } else if (is_output && !inputs) { + } else if (!is_input && !inputs) { for (auto &bit : conn.second) { - if (!bit.wire || bit.wire->port_input) - log_error("Bad connection"); + if (!bit.wire || (bit.wire->port_input && !bit.wire->port_output)) + log_error("Bad connection %s/%s ~ %s\n", log_id(box), log_id(conn.first), log_signal(conn.second)); ensure_pi(bit, cursor); @@ -1119,7 +1114,7 @@ struct XAigerWriter : AigerWriter { holes_pi_idx++; } holes_wb->setPort(port_id, in_conn); - } else if (port->port_output && !port->port_input) { + } else if (port->port_output) { // primary for (int i = 0; i < port->width; i++) { SigBit bit; @@ -1172,7 +1167,7 @@ struct XAigerWriter : AigerWriter { log_assert(port); if (port->port_input && !port->port_output) { box_co_num += port->width; - } else if (port->port_output && !port->port_input) { + } else if (port->port_output) { box_ci_num += port->width; } else { log_abort(); @@ -1195,7 +1190,7 @@ struct XAigerWriter : AigerWriter { reset_counters(); for (auto w : top->wires()) - if (w->port_input) + if (w->port_input && !w->port_output) for (int i = 0; i < w->width; i++) ensure_pi(SigBit(w, i)); From 47b3ee8c8bafb5e1fc8f884b28eaf474e0a8ae8b Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 16 Sep 2025 14:02:32 +0200 Subject: [PATCH 137/188] write_aiger2: Ignore the $input_port cell during indexing. The $input_port cell is added by the bufnorm code to simplify handling of input ports for new code that uses bufnorm, but the aiger2 backend does already handle input ports separately, so we just ignore those. --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index fad73ba9b..05714bc2e 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -91,7 +91,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3))) + if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port))) continue; Module *submodule = m->design->module(cell->type); From 4f239b536bafd8f358c9b08600f1146bcb6f6120 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 16 Sep 2025 13:40:12 +0200 Subject: [PATCH 138/188] abc_new: Hide buffered 'z drivers from read/write_xaiger2 With the updated bufnorm code, buffered 'z drivers are used as anchor points for undirected connections. These are currently not supported by read/write_xaiger2, so we temporarily replace those by roughly equivalent $tribuf cells which will be handled as blackboxes that properly roundtrip through the xaiger2 front and backend. --- passes/techmap/abc9_ops.cc | 82 +++++++++++++++++++++++++++++++++++++- passes/techmap/abc_new.cc | 2 + 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 9a9f7dcb5..ecba519bf 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1566,6 +1566,70 @@ clone_lut: design->remove(mapped_mod); } + +static void replace_zbufs(Design *design) +{ + design->bufNormalize(true); + std::vector zbufs; + + for (auto mod : design->modules()) { + zbufs.clear(); + for (auto cell : mod->cells()) { + if (cell->type != ID($buf)) + continue; + auto &sig = cell->getPort(ID::A); + for (int i = 0; i < GetSize(sig); ++i) { + if (sig[i] == State::Sz) { + zbufs.push_back(cell); + break; + } + } + } + + for (auto cell : zbufs) { + auto sig = cell->getPort(ID::A); + for (int i = 0; i < GetSize(sig); ++i) { + if (sig[i] == State::Sz) { + Wire *w = mod->addWire(NEW_ID); + Cell *ud = mod->addCell(NEW_ID, ID($tribuf)); + ud->set_bool_attribute(ID(aiger2_zbuf)); + ud->setParam(ID::WIDTH, 1); + ud->setPort(ID::Y, w); + ud->setPort(ID::EN, State::S0); + ud->setPort(ID::A, State::S0); + sig[i] = w; + } + } + log("XXX %s -> %s\n", log_signal(cell->getPort(ID::A)), log_signal(sig)); + cell->setPort(ID::A, sig); + } + + mod->bufNormalize(); + } +} + + + +static void restore_zbufs(Design *design) +{ + std::vector to_remove; + + for (auto mod : design->modules()) { + to_remove.clear(); + for (auto cell : mod->cells()) + if (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf))) + to_remove.push_back(cell); + + for (auto cell : to_remove) { + SigSpec sig_y = cell->getPort(ID::Y); + mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y); + mod->remove(cell); + } + mod->bufNormalize(); + } +} + + struct Abc9OpsPass : public Pass { Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { } void help() override @@ -1668,6 +1732,8 @@ struct Abc9OpsPass : public Pass { bool prep_lut_mode = false; bool prep_box_mode = false; bool reintegrate_mode = false; + bool replace_zbufs_mode = false; + bool restore_zbufs_mode = false; bool dff_mode = false; std::string write_lut_dst; int maxlut = 0; @@ -1754,16 +1820,30 @@ struct Abc9OpsPass : public Pass { dff_mode = true; continue; } + if (arg == "-replace_zbufs") { + replace_zbufs_mode = true; + valid = true; + continue; + } + if (arg == "-restore_zbufs") { + restore_zbufs_mode = true; + valid = true; + continue; + } break; } extra_args(args, argidx, design); if (!valid) - log_cmd_error("At least one of -check, -break_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n"); + log_cmd_error("At least one of -check, -break_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate, -{replace,restore}_zbufs must be specified.\n"); if (dff_mode && !check_mode && !prep_hier_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode) log_cmd_error("'-dff' option is only relevant for -prep_{hier,delay,xaiger} or -reintegrate.\n"); + if (replace_zbufs_mode) + replace_zbufs(design); + if (restore_zbufs_mode) + restore_zbufs(design); if (check_mode) check(design, dff_mode); if (prep_hier_mode) diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 286ab4d5b..c48295916 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -169,10 +169,12 @@ struct AbcNewPass : public ScriptPass { } run(stringf(" abc9_ops -write_box %s/input.box", tmpdir)); + run(" abc9_ops -replace_zbufs"); run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir, tmpdir)); run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options, tmpdir, tmpdir)); run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); + run(" abc9_ops -restore_zbufs"); if (!help_mode && mod->has_attribute(ID(abc9_script))) { if (script_save.empty()) From 79e05a195db710f52778ee38f45ed338d14f691e Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 16 Sep 2025 15:49:36 +0200 Subject: [PATCH 139/188] verilog: Bufnorm cell backend and frontend support This makes the Verilog backend handle the $connect and $input_port cells. This represents the undirected $connect cell using the `tran` primitive, so we also extend the frontend to support this. --- backends/verilog/verilog_backend.cc | 50 +++++++++++++++++++++++++++++ frontends/ast/simplify.cc | 26 ++++++++++----- frontends/verilog/verilog_lexer.l | 2 +- 3 files changed, 69 insertions(+), 9 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index aea29f710..c747aa901 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1099,6 +1099,33 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) } if (cell->type.in(ID($_BUF_), ID($buf))) { + if (cell->type == ID($buf) && cell->getPort(ID::A).has_const(State::Sz)) { + RTLIL::SigSpec a = cell->getPort(ID::A); + RTLIL::SigSpec y = cell->getPort(ID::Y); + a.extend_u0(GetSize(y)); + + if (a.has_const(State::Sz)) { + SigSpec new_a; + SigSpec new_y; + for (int i = 0; i < GetSize(a); ++i) { + SigBit b = a[i]; + if (b == State::Sz) + continue; + new_a.append(b); + new_y.append(y[i]); + } + a = std::move(new_a); + y = std::move(new_y); + } + if (!y.empty()) { + f << stringf("%s" "assign ", indent); + dump_sigspec(f, y); + f << stringf(" = "); + dump_sigspec(f, a); + f << stringf(";\n"); + } + return true; + } f << stringf("%s" "assign ", indent); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); @@ -1498,6 +1525,29 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == ID($input_port)) + return true; + + if (cell->type == ID($connect)) + { + int width = cell->getParam(ID::WIDTH).as_int() ; + if (width == 1) { + f << stringf("%s" "tran(", indent); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(", "); + dump_sigspec(f, cell->getPort(ID::B)); + f << stringf(");\n"); + } else { + auto tran_id = next_auto_id(); + f << stringf("%s" "tran %s[%d:0](", indent, tran_id, width - 1); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(", "); + dump_sigspec(f, cell->getPort(ID::B)); + f << stringf(");\n"); + } + return true; + } + if (cell->is_builtin_ff()) { FfData ff(nullptr, cell); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index cf9d7443e..81018e137 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2756,19 +2756,24 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin newNode = std::make_unique(location, AST_GENBLOCK); int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1; + if (this->children.at(1)->type == AST_PRIMITIVE) { + // Move the range to the AST_PRIMITIVE node and replace this with the AST_PRIMITIVE node handled below + newNode = std::move(this->children.at(1)); + newNode->range_left = this->children.at(0)->range_left; + newNode->range_right = this->children.at(0)->range_right; + newNode->range_valid = true; + goto apply_newNode; + } + for (int i = 0; i < num; i++) { int idx = children.at(0)->range_left > children.at(0)->range_right ? children.at(0)->range_right + i : children.at(0)->range_right - i; auto new_cell_owned = children.at(1)->clone(); auto* new_cell = new_cell_owned.get(); newNode->children.push_back(std::move(new_cell_owned)); new_cell->str += stringf("[%d]", idx); - if (new_cell->type == AST_PRIMITIVE) { - input_error("Cell arrays of primitives are currently not supported.\n"); - } else { - this->dumpAst(NULL, " "); - log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); - new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str); - } + + log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); + new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str); } goto apply_newNode; @@ -2789,6 +2794,11 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } children.clear(); + // TODO handle bit-widths of primitives and support cell arrays for more primitives + + if (range_valid && str != "tran") + input_error("Cell arrays of primitives are currently not supported.\n"); + if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) @@ -2817,7 +2827,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin fixup_hierarchy_flags(); did_something = true; } - else if (str == "buf" || str == "not") + else if (str == "buf" || str == "not" || str == "tran") { auto& input = children_list.back(); if (str == "not") diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index c6d2ed992..62a7f7bbb 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -493,7 +493,7 @@ TIME_SCALE_SUFFIX [munpf]?s \"{3}(\"{0,2}([^\\"]|\\.|\\\n))*\"{3} { return process_str(yytext + 3, yyleng - 6, true, out_loc); } -and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { +and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1|tran { auto val = std::make_unique(YYText()); return parser::make_TOK_PRIMITIVE(std::move(val), out_loc); } From 5b099abda4e05af0830d840ee6bd144ec6047b78 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 17 Sep 2025 16:02:04 +0100 Subject: [PATCH 140/188] help: fix memory leak for -dump-cells-json --- kernel/register.cc | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/kernel/register.cc b/kernel/register.cc index 9436b540a..bd12dcc38 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -956,13 +956,7 @@ struct HelpPass : public Pass { auto name = it.first.str(); if (cell_help_messages.contains(name)) { auto cell_help = cell_help_messages.get(name); - if (groups.count(cell_help.group) != 0) { - auto group_cells = &groups.at(cell_help.group); - group_cells->push_back(name); - } else { - auto group_cells = new vector(1, name); - groups.emplace(cell_help.group, *group_cells); - } + groups[cell_help.group].emplace_back(name); auto cell_pair = pair(cell_help, it.second); cells.emplace(name, cell_pair); } else { From a686c5a73c71c238ce5ac25baac84af10932a997 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 18 Sep 2025 00:22:24 +0000 Subject: [PATCH 141/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3e0849c09..1a5ecf35b 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+125 +YOSYS_VER := 0.57+148 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 96f87aa2d43aab7c21293cbc32c2699ca0a36276 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 18 Sep 2025 12:59:12 +0200 Subject: [PATCH 142/188] simplemap: fix src attribute transfer --- passes/techmap/simplemap.cc | 44 +++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index ddfd7e03e..86ff5c149 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -18,6 +18,7 @@ */ #include "simplemap.h" +#include "backends/rtlil/rtlil_backend.h" #include "kernel/sigtools.h" #include "kernel/ff.h" #include @@ -27,6 +28,14 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN +static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) { + if (from->has_attribute(attr)) + to->attributes[attr] = from->attributes.at(attr); +} +static void transfer_src (Cell* to, const Cell* from) { + transfer_attr(to, from, ID::src); +} + void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); @@ -36,7 +45,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -96,7 +105,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -147,11 +156,14 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + log("huh\n"); + RTLIL_BACKEND::dump_cell(std::cout, "", cell); + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); last_output_cell = gate; + RTLIL_BACKEND::dump_cell(std::cout, "", gate); } sig_a = sig_t; @@ -160,7 +172,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -188,7 +200,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -217,7 +229,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -246,7 +258,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -262,20 +274,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(xor_cell, cell); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(reduce_cell, cell); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->attributes[ID::src] = cell->attributes[ID::src]; - simplemap_lognot(module, not_cell); + transfer_src(not_cell, cell); + simplemap_lognot(module, not_cell); module->remove(not_cell); } } @@ -288,7 +300,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, cell->getPort(ID::S)); @@ -305,7 +317,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, sig_s[i]); @@ -321,7 +333,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); @@ -339,7 +351,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); gate->setPort(ID::S, sel[idx]); @@ -362,7 +374,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); gate->setPort(ID::S, lut_ctrl[idx]); From 042aff7c77ae9b7766e6e530e4427f07471bc287 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 19 Sep 2025 11:39:24 +1200 Subject: [PATCH 143/188] Bump test-compile to gcc-14 as newest --- .github/workflows/test-compile.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 45d3d7b90..7c18c7ba0 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -42,7 +42,7 @@ jobs: - 'gcc-10' # newest, make sure to update maximum standard step to match - 'clang-19' - - 'gcc-13' + - 'gcc-14' include: # macOS x86 - os: macos-13 @@ -81,7 +81,7 @@ jobs: # maximum standard, only on newest compilers - name: Build C++20 - if: ${{ matrix.compiler == 'clang-19' || matrix.compiler == 'gcc-13' }} + if: ${{ matrix.compiler == 'clang-19' || matrix.compiler == 'gcc-14' }} shell: bash run: | make config-$CC_SHORT From 19667dd6f11e21320b1913d38fc316e7adcd36e4 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 29 Aug 2025 11:35:16 +1200 Subject: [PATCH 144/188] CI: Don't use self-hosted runner on forks --- .github/workflows/prepare-docs.yml | 2 +- .github/workflows/test-build.yml | 2 +- .github/workflows/test-verific.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index a02febb3b..17d37d08c 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -26,7 +26,7 @@ jobs: # docs builds are needed for anything on main, any tagged versions, and any tag # or branch starting with docs-preview needs: check_docs_rebuild - if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' }} + if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 65d931797..d7f2073fe 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -253,7 +253,7 @@ jobs: name: Try build docs runs-on: [self-hosted, linux, x64, fast] needs: [pre_docs_job] - if: needs.pre_docs_job.outputs.should_skip != 'true' + if: ${{ needs.pre_docs_job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} strategy: matrix: docs-target: [html, latexpdf] diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 9af07b920..c2e4228c4 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -27,7 +27,7 @@ jobs: test-verific: needs: pre-job - if: needs.pre-job.outputs.should_skip != 'true' + if: ${{ needs.pre-job.outputs.should_skip != 'true' && github.repository == 'YosysHQ/Yosys' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys From 0d8c21129fb2d988752e0d9624aa54454e76bdb5 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 19 Sep 2025 16:23:26 +0200 Subject: [PATCH 145/188] rtlil: remove textual RTLIL reference tests for ease of maintenance --- tests/rtlil/roundtrip-text.ref.il | 283 ------ tests/rtlil/roundtrip-text.sh | 8 - tests/rtlil/roundtrip-text.synth.ref.il | 1194 ----------------------- 3 files changed, 1485 deletions(-) delete mode 100644 tests/rtlil/roundtrip-text.ref.il delete mode 100644 tests/rtlil/roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il deleted file mode 100644 index cc45f53dd..000000000 --- a/tests/rtlil/roundtrip-text.ref.il +++ /dev/null @@ -1,283 +0,0 @@ -autoidx 15 -attribute \src "everything.v:1.1-32.10" -attribute \cells_not_processed 1 -module \alu - attribute \src "everything.v:2.8-2.11" - wire input 1 \clk - attribute \src "everything.v:3.14-3.15" - wire width 8 input 2 \A - attribute \src "everything.v:4.14-4.15" - wire width 8 input 3 \B - attribute \src "everything.v:5.14-5.23" - wire width 4 input 4 \operation - attribute \src "everything.v:6.19-6.25" - wire width 8 output 5 \result - attribute \src "everything.v:7.13-7.15" - wire output 6 \CF - attribute \src "everything.v:8.13-8.15" - wire output 7 \ZF - attribute \src "everything.v:9.13-9.15" - wire output 8 \SF - attribute \src "everything.v:15.12-15.15" - wire width 9 \tmp - attribute \src "everything.v:17.2-31.5" - wire width 8 $0\result[7:0] - attribute \src "everything.v:17.2-31.5" - wire $0\CF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\ZF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\SF[0:0] - attribute \src "everything.v:17.2-31.5" - wire width 9 $0\tmp[8:0] - attribute \src "everything.v:17.2-31.5" - wire width 9 $1\tmp[8:0] - attribute \src "everything.v:21.11-21.16" - wire width 9 $add$everything.v:21$2_Y - attribute \src "everything.v:23.11-23.16" - wire width 9 $sub$everything.v:23$3_Y - attribute \src "everything.v:27.9-27.22" - wire $eq$everything.v:27$4_Y - attribute \src "everything.v:21.11-21.16" - cell $add $add$everything.v:21$2 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 9 - connect \A \A - connect \B \B - connect \Y $add$everything.v:21$2_Y - end - attribute \src "everything.v:23.11-23.16" - cell $sub $sub$everything.v:23$3 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 9 - connect \A \A - connect \B \B - connect \Y $sub$everything.v:23$3_Y - end - attribute \src "everything.v:27.9-27.22" - cell $eq $eq$everything.v:27$4 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A $1\tmp[8:0] [7:0] - connect \B 0 - connect \Y $eq$everything.v:27$4_Y - end - attribute \src "everything.v:17.2-31.5" - process $proc$everything.v:17$1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\tmp[8:0] $1\tmp[8:0] - assign $0\CF[0:0] $1\tmp[8:0] [8] - assign $0\ZF[0:0] $eq$everything.v:27$4_Y - assign $0\SF[0:0] $1\tmp[8:0] [7] - assign $0\result[7:0] $1\tmp[8:0] [7:0] - attribute \src "everything.v:19.3-24.10" - switch \operation - attribute \src "everything.v:19.19-19.19" - case 4'0000 - assign { } { } - assign $1\tmp[8:0] $add$everything.v:21$2_Y - attribute \src "everything.v:21.17-21.17" - case 4'0001 - assign { } { } - assign $1\tmp[8:0] $sub$everything.v:23$3_Y - case - assign $1\tmp[8:0] \tmp - end - sync posedge \clk - update \result $0\result[7:0] - update \CF $0\CF[0:0] - update \ZF $0\ZF[0:0] - update \SF $0\SF[0:0] - update \tmp $0\tmp[8:0] - end -end -attribute \src "everything.v:34.1-40.10" -attribute \cells_not_processed 1 -module \foo - attribute \src "everything.v:35.17-35.18" - wire width 8 input 1 \a - attribute \src "everything.v:35.32-35.33" - wire width 8 input 2 \b - attribute \src "everything.v:35.48-35.49" - wire width 8 output 3 \y - attribute \src "everything.v:37.16-37.18" - wire width 8 \bb - attribute \src "everything.v:39.16-39.22" - wire width 8 $add$everything.v:39$5_Y - attribute \src "everything.v:39.16-39.22" - cell $add $add$everything.v:39$5 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \a - connect \B \bb - connect \Y $add$everything.v:39$5_Y - end - connect \b \bb - connect \y $add$everything.v:39$5_Y -end -attribute \cells_not_processed 1 -attribute \src "everything.v:1.1-32.10" -module \zzz - attribute \src "everything.v:27.9-27.22" - wire $eq$everything.v:27$4_Y - attribute \src "everything.v:23.11-23.16" - wire width 9 $sub$everything.v:23$3_Y - attribute \src "everything.v:21.11-21.16" - wire width 9 $add$everything.v:21$2_Y - attribute \src "everything.v:17.2-31.5" - wire width 9 $1\tmp[8:0] - attribute \src "everything.v:17.2-31.5" - wire width 9 $0\tmp[8:0] - attribute \src "everything.v:17.2-31.5" - wire $0\SF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\ZF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\CF[0:0] - attribute \src "everything.v:17.2-31.5" - wire width 8 $0\result[7:0] - attribute \src "everything.v:15.12-15.15" - wire width 9 \tmp - attribute \src "everything.v:9.13-9.15" - wire output 8 \SF - attribute \src "everything.v:8.13-8.15" - wire output 7 \ZF - attribute \src "everything.v:7.13-7.15" - wire output 6 \CF - attribute \src "everything.v:6.19-6.25" - wire width 8 output 5 \result - attribute \src "everything.v:5.14-5.23" - wire width 4 input 4 \operation - attribute \src "everything.v:4.14-4.15" - wire width 8 input 3 \B - attribute \src "everything.v:3.14-3.15" - wire width 8 input 2 \A - attribute \src "everything.v:2.8-2.11" - wire input 1 \clk - wire $procmux$8_CMP - wire width 9 $procmux$7_Y - wire $procmux$9_CMP - attribute \src "everything.v:27.9-27.22" - cell $logic_not $eq$everything.v:27$4 - parameter \A_SIGNED 0 - parameter \Y_WIDTH 1 - parameter \A_WIDTH 8 - connect \A $1\tmp[8:0] [7:0] - connect \Y $eq$everything.v:27$4_Y - end - attribute \src "everything.v:23.11-23.16" - cell $sub $sub$everything.v:23$3 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 9 - connect \A \A - connect \B \B - connect \Y $sub$everything.v:23$3_Y - end - attribute \src "everything.v:21.11-21.16" - cell $add $add$everything.v:21$2 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 9 - connect \A \A - connect \B \B - connect \Y $add$everything.v:21$2_Y - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - attribute \full_case 1 - cell $eq $procmux$8_CMP0 - parameter \A_SIGNED 0 - parameter \B_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \operation - connect \B 4'0001 - connect \Y $procmux$8_CMP - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - attribute \full_case 1 - cell $pmux $procmux$7 - parameter \WIDTH 9 - parameter \S_WIDTH 2 - connect \A \tmp - connect \B { $add$everything.v:21$2_Y $sub$everything.v:23$3_Y } - connect \S { $procmux$9_CMP $procmux$8_CMP } - connect \Y $procmux$7_Y - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - attribute \full_case 1 - cell $logic_not $procmux$9_CMP0 - parameter \A_SIGNED 0 - parameter \Y_WIDTH 1 - parameter \A_WIDTH 4 - connect \A \operation - connect \Y $procmux$9_CMP - end - attribute \src "everything.v:17.2-31.5" - cell $dff $procdff$10 - parameter \WIDTH 8 - parameter \CLK_POLARITY 1'1 - connect \D $procmux$7_Y [7:0] - connect \Q \result - connect \CLK \clk - end - attribute \src "everything.v:17.2-31.5" - cell $dff $procdff$11 - parameter \WIDTH 1 - parameter \CLK_POLARITY 1'1 - connect \D $procmux$7_Y [8] - connect \Q \CF - connect \CLK \clk - end - attribute \src "everything.v:17.2-31.5" - cell $dff $procdff$12 - parameter \WIDTH 1 - parameter \CLK_POLARITY 1'1 - connect \D $eq$everything.v:27$4_Y - connect \Q \ZF - connect \CLK \clk - end - attribute \src "everything.v:17.2-31.5" - cell $dff $procdff$13 - parameter \WIDTH 1 - parameter \CLK_POLARITY 1'1 - connect \D $procmux$7_Y [7] - connect \Q \SF - connect \CLK \clk - end - attribute \src "everything.v:17.2-31.5" - cell $dff $procdff$14 - parameter \WIDTH 9 - parameter \CLK_POLARITY 1'1 - connect \D $procmux$7_Y - connect \Q \tmp - connect \CLK \clk - end - connect $0\result[7:0] $1\tmp[8:0] [7:0] - connect $0\SF[0:0] $1\tmp[8:0] [7] - connect $0\ZF[0:0] $eq$everything.v:27$4_Y - connect $0\CF[0:0] $1\tmp[8:0] [8] - connect $0\tmp[8:0] $1\tmp[8:0] - connect $1\tmp[8:0] $procmux$7_Y -end diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 7a979879c..35417cff7 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -17,7 +17,6 @@ remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il -diff temp/roundtrip-text.dump.il roundtrip-text.ref.il # Loading and writing it out again doesn't change the RTLIL $YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" @@ -30,10 +29,3 @@ $YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il - -echo "Without ABC, we don't get any irreproducibility and can pin that" -echo "Has this test case started failing for you? Consider updating the reference" -$YS -p "read_verilog -sv everything.v; synth -relativeshare -noabc; write_rtlil temp/roundtrip-text.synth.il" -remove_empty_lines temp/roundtrip-text.synth.il -tail -n +2 temp/roundtrip-text.synth.il > temp/roundtrip-text.synth-nogen.il -diff temp/roundtrip-text.synth-nogen.il roundtrip-text.synth.ref.il diff --git a/tests/rtlil/roundtrip-text.synth.ref.il b/tests/rtlil/roundtrip-text.synth.ref.il deleted file mode 100644 index ab48affc6..000000000 --- a/tests/rtlil/roundtrip-text.synth.ref.il +++ /dev/null @@ -1,1194 +0,0 @@ -autoidx 511 -attribute \src "everything.v:34.1-40.10" -module \foo - attribute \src "everything.v:35.48-35.49" - wire width 8 output 3 \y - attribute \src "everything.v:37.16-37.18" - wire width 8 \bb - attribute \src "everything.v:35.32-35.33" - wire width 8 input 2 \b - attribute \src "everything.v:35.17-35.18" - wire width 8 input 1 \a - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y - attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" - attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.lcu.G - attribute \src "everything.v:39.16-39.22|+/techmap.v:270.23-270.24" - attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.X - attribute \unused_bits "7" - attribute \src "everything.v:39.16-39.22|+/techmap.v:274.23-274.25" - attribute \force_downto 1 - wire width 8 $auto$alumacc.cc:495:replace_alu$21.CO - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$219 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$218 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$217 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$216 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$213 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$211 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$150_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$210 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$or$+/techmap.v:240$147_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$209 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y - connect \A $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$207 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$173_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$206 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$170_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$205 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$167_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$204 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:248$164_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$201 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$151_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.X [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$200 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.X [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$197 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$155_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:241$148_Y - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$195 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$149_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$194 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$146_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$193 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$21.lcu.$and$+/techmap.v:240$143_Y - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$138 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [6] - connect \B \b [6] - connect \A \a [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$137 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [5] - connect \B \b [5] - connect \A \a [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$136 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [4] - connect \B \b [4] - connect \A \a [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$135 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [3] - connect \B \b [3] - connect \A \a [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$134 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [2] - connect \B \b [2] - connect \A \a [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$133 - connect \Y $auto$alumacc.cc:495:replace_alu$21.lcu.G [1] - connect \B \b [1] - connect \A \a [1] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$132 - connect \Y $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \B \b [0] - connect \A \a [0] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$131 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [7] - connect \B \b [7] - connect \A \a [7] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$130 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [6] - connect \B \b [6] - connect \A \a [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$129 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [5] - connect \B \b [5] - connect \A \a [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$128 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [4] - connect \B \b [4] - connect \A \a [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$127 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [3] - connect \B \b [3] - connect \A \a [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$126 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [2] - connect \B \b [2] - connect \A \a [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$125 - connect \Y $auto$alumacc.cc:495:replace_alu$21.X [1] - connect \B \b [1] - connect \A \a [1] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$124 - connect \Y \y [0] - connect \B \b [0] - connect \A \a [0] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$122 - connect \Y \y [7] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [6] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [7] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$121 - connect \Y \y [6] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [6] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$120 - connect \Y \y [5] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [4] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [5] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$119 - connect \Y \y [4] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [4] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$118 - connect \Y \y [3] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [2] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [3] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$117 - connect \Y \y [2] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [2] - end - attribute \src "everything.v:39.16-39.22|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$116 - connect \Y \y [1] - connect \B $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$21.X [1] - end - connect $auto$alumacc.cc:495:replace_alu$21.X [0] \y [0] - connect $auto$alumacc.cc:495:replace_alu$21.lcu.G [0] $auto$alumacc.cc:495:replace_alu$21.CO [0] - connect \bb \b -end -attribute \src "everything.v:1.1-32.10" -module \alu - attribute \src "everything.v:15.12-15.15" - wire width 9 \tmp - attribute \src "everything.v:6.19-6.25" - wire width 8 output 5 \result - attribute \src "everything.v:5.14-5.23" - wire width 4 input 4 \operation - attribute \src "everything.v:2.8-2.11" - wire input 1 \clk - attribute \src "everything.v:8.13-8.15" - wire output 7 \ZF - attribute \src "everything.v:9.13-9.15" - wire output 8 \SF - attribute \src "everything.v:7.13-7.15" - wire output 6 \CF - attribute \src "everything.v:4.14-4.15" - wire width 8 input 3 \B - attribute \src "everything.v:3.14-3.15" - wire width 8 input 2 \A - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y - attribute \src "+/techmap.v:270.26-270.27" - attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y - attribute \src "+/techmap.v:274.23-274.25" - attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO - attribute \src "+/techmap.v:279.21-279.23" - attribute \force_downto 1 - wire width 9 $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - wire $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y - wire $procmux$9_CMP - wire $procmux$8_CMP - wire $auto$simplemap.cc:254:simplemap_eqne$247 - wire $auto$simplemap.cc:166:logic_reduce$268 - wire width 2 $auto$simplemap.cc:166:logic_reduce$265 - wire $auto$simplemap.cc:166:logic_reduce$235 - wire width 2 $auto$simplemap.cc:166:logic_reduce$232 - wire width 4 $auto$simplemap.cc:166:logic_reduce$227 - wire width 2 $auto$simplemap.cc:125:simplemap_reduce$249 - wire $auto$rtlil.cc:3196:NotGate$497 - wire $auto$opt_dff.cc:247:make_patterns_logic$505 - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:214.23-214.24" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.lcu.G - attribute \src "everything.v:23.11-23.16|+/techmap.v:270.26-270.27" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.Y - attribute \src "everything.v:23.11-23.16|+/techmap.v:270.23-270.24" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.X - attribute \unused_bits "8" - attribute \src "everything.v:23.11-23.16|+/techmap.v:274.23-274.25" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.CO - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.21-279.23" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.BB - attribute \src "everything.v:23.11-23.16|+/techmap.v:268.22-268.23" - attribute \force_downto 1 - wire width 9 $auto$alumacc.cc:495:replace_alu$18.B - attribute \src "everything.v:17.2-31.5" - wire width 8 $0\result[7:0] - attribute \src "everything.v:17.2-31.5" - wire $0\ZF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\SF[0:0] - attribute \src "everything.v:17.2-31.5" - wire $0\CF[0:0] - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$481 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$480 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$479 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$478 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$477 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$476 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$342_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$475 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$339_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$474 - connect \Y $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$473 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$348_Y - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$471 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.lcu.$and$+/techmap.v:241$336_Y - end - attribute \src "+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$467 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$427 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [6] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$426 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [5] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$425 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [4] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$424 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [3] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$423 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [2] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$422 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [1] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] - end - attribute \src "+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$421 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$418 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$417 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$416 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.12-248.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$415 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$414 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$413 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$347_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$412 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$411 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$341_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$410 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$409 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$335_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.12-240.41" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$408 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:231.10-231.28" - cell $_OR_ $auto$simplemap.cc:83:simplemap_bitop$407 - connect \Y $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.X [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$405 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$361_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$404 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$358_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$403 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$355_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:248.19-248.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$402 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:248$352_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$401 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$400 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$399 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$339_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:241.12-241.34" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$398 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.X [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$397 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$349_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$348_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$396 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$346_Y - connect \B $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$or$+/techmap.v:240$338_Y - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$342_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$395 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$343_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:241$336_Y - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$394 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$340_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$393 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$337_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$392 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$334_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.27-286.69|+/techmap.v:240.19-240.41" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$391 - connect \Y $techmap$auto$alumacc.cc:495:replace_alu$18.lcu.$and$+/techmap.v:240$331_Y - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$326 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] - connect \A \A [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$325 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] - connect \A \A [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$324 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] - connect \A \A [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$323 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] - connect \A \A [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$322 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] - connect \A \A [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$321 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] - connect \A \A [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$320 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] - connect \A \A [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:286.42-286.49" - cell $_AND_ $auto$simplemap.cc:83:simplemap_bitop$319 - connect \Y $auto$alumacc.cc:495:replace_alu$18.lcu.G [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A \A [0] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$317 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [7] - connect \A \A [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$316 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [6] - connect \A \A [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$315 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [5] - connect \A \A [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$314 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [4] - connect \A \A [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$313 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [3] - connect \A \A [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$312 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [2] - connect \A \A [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$311 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [1] - connect \A \A [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:288.13-288.20" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$310 - connect \Y $auto$alumacc.cc:495:replace_alu$18.X [0] - connect \B $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A \A [0] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$308 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [8] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [7] - connect \A $auto$alumacc.cc:495:replace_alu$18.BB [8] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$307 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [7] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$306 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [6] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$305 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [5] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$304 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [4] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$303 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [3] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$302 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [2] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:289.13-289.25" - cell $_XOR_ $auto$simplemap.cc:83:simplemap_bitop$301 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [1] - connect \B $auto$alumacc.cc:495:replace_alu$18.CO [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [1] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$464 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [7] - connect \A \B [7] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$463 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [6] - connect \A \B [6] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$462 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [5] - connect \A \B [5] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$461 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [4] - connect \A \B [4] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$460 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [3] - connect \A \B [3] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$459 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [2] - connect \A \B [2] - end - attribute \src "+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$458 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [1] - connect \A \B [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$384 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [8] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [8] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$383 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [7] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [7] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$382 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [6] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [6] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$381 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [5] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [5] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$380 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [4] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [4] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$379 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [3] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [3] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$378 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [2] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [2] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$377 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [1] - connect \A $auto$alumacc.cc:495:replace_alu$18.B [1] - end - attribute \src "everything.v:23.11-23.16|+/techmap.v:279.31-279.37" - cell $_NOT_ $auto$simplemap.cc:38:simplemap_not$376 - connect \Y $auto$alumacc.cc:495:replace_alu$18.BB [0] - connect \A \B [0] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$299 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [8] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] - connect \A 1'0 - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$298 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [7] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [7] - connect \A \B [7] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$297 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [6] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [6] - connect \A \B [6] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$296 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [5] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [5] - connect \A \B [5] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$295 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [4] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [4] - connect \A \B [4] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$294 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [3] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [3] - connect \A \B [3] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$293 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [2] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [2] - connect \A \B [2] - end - attribute \src 0'x - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$292 - connect \Y $auto$alumacc.cc:495:replace_alu$18.B [1] - connect \S $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [1] - connect \A \B [1] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$264 - connect \Y $0\CF[0:0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [8] - connect \A 1'x - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$263 - connect \Y $0\SF[0:0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [7] - connect \A \tmp [7] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$262 - connect \Y $0\result[7:0] [6] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [6] - connect \A \tmp [6] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$261 - connect \Y $0\result[7:0] [5] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [5] - connect \A \tmp [5] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$260 - connect \Y $0\result[7:0] [4] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [4] - connect \A \tmp [4] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$259 - connect \Y $0\result[7:0] [3] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [3] - connect \A \tmp [3] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$258 - connect \Y $0\result[7:0] [2] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [2] - connect \A \tmp [2] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$257 - connect \Y $0\result[7:0] [1] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [1] - connect \A \tmp [1] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_MUX_ $auto$simplemap.cc:275:simplemap_mux$256 - connect \Y $0\result[7:0] [0] - connect \S $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $auto$alumacc.cc:495:replace_alu$18.Y [0] - connect \A \tmp [0] - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$270 - connect \Y $procmux$9_CMP - connect \A $auto$simplemap.cc:166:logic_reduce$268 - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$255 - connect \Y $procmux$8_CMP - connect \A $auto$simplemap.cc:254:simplemap_eqne$247 - end - attribute \src "everything.v:27.9-27.22" - cell $_NOT_ $auto$simplemap.cc:204:simplemap_lognot$237 - connect \Y $0\ZF[0:0] - connect \A $auto$simplemap.cc:166:logic_reduce$235 - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$269 - connect \Y $auto$simplemap.cc:166:logic_reduce$268 - connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$265 [0] - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$267 - connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \B \operation [3] - connect \A \operation [2] - end - attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$266 - connect \Y $auto$simplemap.cc:166:logic_reduce$265 [0] - connect \B \operation [1] - connect \A \operation [0] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$236 - connect \Y $auto$simplemap.cc:166:logic_reduce$235 - connect \B $auto$simplemap.cc:166:logic_reduce$232 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$232 [0] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$234 - connect \Y $auto$simplemap.cc:166:logic_reduce$232 [1] - connect \B $auto$simplemap.cc:166:logic_reduce$227 [3] - connect \A $auto$simplemap.cc:166:logic_reduce$227 [2] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$233 - connect \Y $auto$simplemap.cc:166:logic_reduce$232 [0] - connect \B $auto$simplemap.cc:166:logic_reduce$227 [1] - connect \A $auto$simplemap.cc:166:logic_reduce$227 [0] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$231 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [3] - connect \B $0\SF[0:0] - connect \A $0\result[7:0] [6] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$230 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [2] - connect \B $0\result[7:0] [5] - connect \A $0\result[7:0] [4] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$229 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [1] - connect \B $0\result[7:0] [3] - connect \A $0\result[7:0] [2] - end - attribute \src "everything.v:27.9-27.22" - cell $_OR_ $auto$simplemap.cc:175:logic_reduce$228 - connect \Y $auto$simplemap.cc:166:logic_reduce$227 [0] - connect \B $0\result[7:0] [1] - connect \A $0\result[7:0] [0] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$253 - connect \Y $auto$simplemap.cc:254:simplemap_eqne$247 - connect \B $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect \A $auto$simplemap.cc:125:simplemap_reduce$249 [0] - end - attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10" - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$250 - connect \Y $auto$simplemap.cc:125:simplemap_reduce$249 [0] - connect \B \operation [1] - connect \A $auto$rtlil.cc:3196:NotGate$497 - end - attribute \src 0'x - cell $_OR_ $auto$simplemap.cc:134:simplemap_reduce$226 - connect \Y $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \B $procmux$9_CMP - connect \A $procmux$8_CMP - end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$502 - connect \Y $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [8] - connect \A $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] - end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$500 - connect \Y $auto$alumacc.cc:495:replace_alu$18.Y [0] - connect \A $auto$alumacc.cc:495:replace_alu$18.X [0] - end - cell $_NOT_ $auto$opt_expr.cc:617:replace_const_cells$496 - connect \Y $auto$rtlil.cc:3196:NotGate$497 - connect \A \operation [0] - end - attribute \src "everything.v:17.2-31.5" - cell $_DFFE_PP_ $auto$ff.cc:266:slice$504 - connect \Q \CF - connect \E $auto$opt_dff.cc:247:make_patterns_logic$505 - connect \D $0\CF[0:0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$289 - connect \Q \tmp [7] - connect \D $0\SF[0:0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$288 - connect \Q \tmp [6] - connect \D $0\result[7:0] [6] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$287 - connect \Q \tmp [5] - connect \D $0\result[7:0] [5] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$286 - connect \Q \tmp [4] - connect \D $0\result[7:0] [4] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$285 - connect \Q \tmp [3] - connect \D $0\result[7:0] [3] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$284 - connect \Q \tmp [2] - connect \D $0\result[7:0] [2] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$283 - connect \Q \tmp [1] - connect \D $0\result[7:0] [1] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$282 - connect \Q \tmp [0] - connect \D $0\result[7:0] [0] - connect \C \clk - end - attribute \src "everything.v:17.2-31.5" - cell $_DFF_P_ $auto$ff.cc:266:slice$280 - connect \Q \ZF - connect \D $0\ZF[0:0] - connect \C \clk - end - connect $0\result[7:0] [7] $0\SF[0:0] - connect $auto$alumacc.cc:495:replace_alu$18.B [0] \B [0] - connect $auto$alumacc.cc:495:replace_alu$18.X [8] $auto$alumacc.cc:495:replace_alu$18.BB [8] - connect $auto$alumacc.cc:495:replace_alu$18.lcu.G [8] 1'0 - connect $auto$simplemap.cc:166:logic_reduce$265 [1] $auto$simplemap.cc:125:simplemap_reduce$249 [1] - connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [8] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.BB [0] } { 1'1 $auto$alumacc.cc:495:replace_alu$18.BB [0] } - connect { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [7] $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [0] } { $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.CO [8] $auto$alumacc.cc:495:replace_alu$18.BB [0] } - connect $techmap$auto$opt_share.cc:199:merge_operators$24.$auto$alumacc.cc:495:replace_alu$238.Y [0] \B [0] - connect \SF \tmp [7] - connect \result \tmp [7:0] - connect \tmp [8] \CF -end From 6b3a7e244037e891dc98774845516b2a1b0c1840 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 20 Sep 2025 00:21:36 +0000 Subject: [PATCH 146/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1a5ecf35b..720fd6323 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+148 +YOSYS_VER := 0.57+153 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 9fa27dae3cc68205eab8d9d06302ace2bc6ddf41 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 13 Sep 2025 17:15:24 +0300 Subject: [PATCH 147/188] hotfix: fix new log functions being incompatible with pyosys Modify python wrapper generator script with corner-case handlers such that functions that start with `log_formatted` have the format string coerced to `"%s"` and also have an alias without the `_formatted` part. --- misc/py_wrap_generator.py | 38 +++++++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index ef0862587..e695d1ef0 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -71,7 +71,7 @@ keyword_aliases = { #These can be used without any explicit conversion primitive_types = ["void", "bool", "int", "double", "size_t", "std::string", - "string", "State", "char_p", "std::source_location", "source_location"] + "string", "string_view", "std::string_view", "State", "char_p", "std::source_location", "source_location"] from enum import Enum @@ -557,6 +557,7 @@ class Attribute: default_value = None pos = None pos_counter = 0 + coerce_arg = None def __init__(self, wtype, varname, is_const = False, default_value = None): self.wtype = wtype @@ -566,7 +567,7 @@ class Attribute: self.container = None @staticmethod - def from_string(str_def, containing_file, line_number): + def from_string(str_def, containing_file, line_number, *, owner_fn_name=""): if len(str_def) < 3: return None orig = str_def @@ -630,6 +631,14 @@ class Attribute: else: arg.wtype.attr_type = attr_types.amp arg.varname = arg.varname[1:] + + # special exception: format strings + if arg.wtype.name in ["std::string_view", "string_view"]: + if arg.varname == "format": + arg.coerce_arg = '"%s"' + elif arg.varname == "prefix" and "warning" in owner_fn_name: + arg.coerce_arg = '"Warning: "' + return arg #Generates the varname. If the attribute has no name in the header file, @@ -1391,7 +1400,7 @@ class WFunction: for i, arg in enumerate(args): if arg.strip() == "...": continue - parsed = Attribute.from_string(arg.strip(), containing_file, line_number) + parsed = Attribute.from_string(arg.strip(), containing_file, line_number, owner_fn_name=func.name) if parsed == None: return None # Only allow std::source_location as defaulted last argument, and @@ -1431,6 +1440,8 @@ class WFunction: text += "static " text += self.ret_type.gen_text() + " " + self.alias + "(" for arg in self.args: + if arg.coerce_arg: + continue text += arg.gen_listitem() text += ", " if len(self.args) > 0: @@ -1497,6 +1508,8 @@ class WFunction: text += self.member_of.name + "::" text += self.alias + "(" for arg in self.args: + if arg.coerce_arg: + continue text += arg.gen_listitem() text += ", " if len(self.args) > 0: @@ -1516,13 +1529,14 @@ class WFunction: if self.ret_type.name in classnames: text += self.ret_type.name + "::get_py_obj(" if self.member_of == None: - text += "::" + self.namespace + "::" + self.alias + "(" + text += "::" + self.namespace + "::" + self.name + "(" elif self.is_static: text += self.member_of.namespace + "::" + self.member_of.name + "::" + self.name + "(" else: text += "this->get_cpp_obj()->" + self.name + "(" for arg in self.args: - text += arg.gen_call() + ", " + text += arg.coerce_arg or arg.gen_call() + text += ", " if len(self.args) > 0: text = text[:-2] if self.ret_type.name in classnames: @@ -1639,6 +1653,8 @@ class WFunction: else: text += "(" + self.member_of.name + "::*)(" for a in self.args: + if a.coerce_arg: + continue text += a.gen_listitem_hash() + ", " if len(self.args) > 0: text = text[0:-2] + f"){self.gen_post_qualifiers(True)}>" @@ -2122,6 +2138,16 @@ def parse_header(source): if class_ == None: debug("\tFound unowned function \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces),2) unowned_functions.append(candidate) + + # generate log aliases + if candidate.name.startswith("log_formatted"): + alias = candidate.name.replace("log_formatted", "log") + if alias == "log_string": + alias = "log" + copied_candidate = copy.copy(candidate) + copied_candidate.alias = alias + unowned_functions.append(copied_candidate) + else: debug("\t\tFound function \"" + candidate.name + "\" of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) class_[0].found_funs.append(candidate) @@ -2359,6 +2385,8 @@ def gen_wrappers(filename, debug_level_ = 0): #include USING_YOSYS_NAMESPACE +using std::string_view; + namespace YOSYS_PYTHON { [[noreturn]] static void log_python_exception_as_error() { From 1fa5ceee8c57347b9a834ecd3f4a80cf343f91fa Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 15 Sep 2025 17:02:11 +0300 Subject: [PATCH 148/188] pyosys: restore remaining log functions Co-authored-by: George Rennie <19538554+georgerennie@users.noreply.github.com> --- kernel/log.h | 5 +++++ misc/py_wrap_generator.py | 9 +++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/kernel/log.h b/kernel/log.h index 78b202159..bd5788758 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -153,6 +153,11 @@ inline void log_warning(FmtString...> fmt, const Args &... ar { log_formatted_warning("Warning: ", fmt.format(args...)); } + +inline void log_formatted_warning_noprefix(std::string str) +{ + log_formatted_warning("", str); +} template inline void log_warning_noprefix(FmtString...> fmt, const Args &... args) { diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index e695d1ef0..aa1406f9b 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -632,12 +632,17 @@ class Attribute: arg.wtype.attr_type = attr_types.amp arg.varname = arg.varname[1:] - # special exception: format strings + # handle string views if arg.wtype.name in ["std::string_view", "string_view"]: - if arg.varname == "format": + if arg.varname == "format" and owner_fn_name.startswith("log_"): + # coerce format strings to "%s" (not bridgable) arg.coerce_arg = '"%s"' elif arg.varname == "prefix" and "warning" in owner_fn_name: + # coerce warning prefix to "warning:" arg.coerce_arg = '"Warning: "' + else: + # boost::python can't bridge string views, so just copy them + arg.wtype.name = "string" return arg From d60dc93e9223e33b635194ed5efc49c4fb89fc49 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Sat, 20 Sep 2025 11:01:25 +1000 Subject: [PATCH 149/188] Gowin. Renaming inputs of the DCS primitive. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dynamic clock selection (DCS) primitive has undergone changes with the release of the GW5A series—the CLK0,1,2,3 inputs are now CLKIN0,1,2,3, but only for GW5A series chips. There are no functional changes, only renaming. Here we are transferring the description of the DCS primitive from general to specialized files for each chip series. We have also fixed a bug in the generation script that caused the loss of primitive parameters. Fortunately, this only affected the analog-to-digital converter, which has not yet been implemented. Signed-off-by: YRabbit --- techlibs/gowin/cells_sim.v | 8 --- techlibs/gowin/cells_xtra.py | 4 +- techlibs/gowin/cells_xtra_gw1n.v | 7 +++ techlibs/gowin/cells_xtra_gw2a.v | 12 +++++ techlibs/gowin/cells_xtra_gw5a.v | 84 ++++++++++++++++++++++++++++++++ 5 files changed, 105 insertions(+), 10 deletions(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 58a2f52e6..5e6083426 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -1958,14 +1958,6 @@ parameter FREQ_DIV = 100; parameter REGULATOR_EN = 1'b0; endmodule -(* blackbox *) -module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT); -input CLK0, CLK1, CLK2, CLK3, SELFORCE; -input [3:0] CLKSEL; -output CLKOUT; -parameter DCS_MODE = "RISING"; -endmodule - (* blackbox *) module EMCU ( input FCLK, diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py index 7a7c9ac0a..01416268a 100644 --- a/techlibs/gowin/cells_xtra.py +++ b/techlibs/gowin/cells_xtra.py @@ -25,7 +25,7 @@ _skip = { # These are already described, no need to extract them from the vendor 'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4', 'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4', 'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP', - 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU', + 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'EMCU', # These are not planned for implementation 'MUX2_MUX8', 'MUX2_MUX16', 'MUX2_MUX32', 'MUX4', 'MUX8', 'MUX16', 'MUX32', 'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE', @@ -50,7 +50,7 @@ def xtract_cells_decl(dir, fout): fout.write('\n') if l.rstrip()[-1] != ';': state = State.IN_MODULE_MULTILINE - elif l.startswith('parameter') and state == State.IN_MODULE: + elif l.lstrip().startswith('parameter') and state == State.IN_MODULE: fout.write(l) if l.rstrip()[-1] == ',': state = State.IN_PARAMETER diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v index abf2c0493..436fda0fa 100644 --- a/techlibs/gowin/cells_xtra_gw1n.v +++ b/techlibs/gowin/cells_xtra_gw1n.v @@ -1109,6 +1109,13 @@ parameter IDLE = 4'd0, RD_S2 = 4'd12; endmodule +module DCS (...); +input CLK0, CLK1, CLK2, CLK3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; + parameter DCS_MODE = "RISING"; +endmodule + module DQCE (...); input CLKIN; input CE; diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v index 5c365f8da..4df48ab64 100644 --- a/techlibs/gowin/cells_xtra_gw2a.v +++ b/techlibs/gowin/cells_xtra_gw2a.v @@ -1082,6 +1082,11 @@ input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; output DQSR90, DQSW0, DQSW270; output [2:0] RPOINT, WPOINT; output RVALID,RBURST, RFLAG, WFLAG; + parameter FIFO_MODE_SEL = 1'b0; + parameter RD_PNTR = 3'b000; + parameter DQS_MODE = "X1"; + parameter HWL = "false"; + parameter GSREN = "false"; endmodule module DLLDLY (...); @@ -1095,6 +1100,13 @@ parameter DLY_SIGN = 1'b0; parameter DLY_ADJ = 0; endmodule +module DCS (...); +input CLK0, CLK1, CLK2, CLK3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; + parameter DCS_MODE = "RISING"; +endmodule + module DQCE (...); input CLKIN; input CE; diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index c82f6af25..b4df1f33e 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -1143,6 +1143,13 @@ input CE; output CLKOUT; endmodule +module DCS (...); +input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; +parameter DCS_MODE = "RISING"; +endmodule + module DDRDLL (...); input CLKIN; input STOP; @@ -1714,18 +1721,94 @@ input LOAD; endmodule module ADCLRC (...); + parameter DYN_BKEN = "FALSE"; + parameter BUF_SERDES_Q1_EN = 3'b000; + parameter BUF_BK2_EN = 6'b000000; + parameter BUF_BK3_EN = 6'b000000; + parameter BUF_BK4_EN = 6'b000000; + parameter BUF_BK5_EN = 6'b000000; + parameter BUF_BK10_EN = 5'b00000; + parameter BUF_BK11_EN = 5'b00000; + parameter CLK_SEL = 1'b0; + parameter PIOCLK_SEL = 1'b0; + parameter VSEN_CTL = 3'b000; + parameter VSEN_CTL_SEL = 1'b0; + parameter ADC_MODE = 1'b0; + parameter DIV_CTL = 2'd0; + parameter SAMPLE_CNT_SEL = 3'd4; + parameter RATE_CHANGE_CTRL = 3'd4; endmodule module ADCULC (...); + parameter DYN_BKEN = "FALSE"; + parameter BUF_VCC_EN = 1'b0; + parameter BUF_VCCM_EN = 1'b0; + parameter BUF_MIPI_M0_EN = 3'b000; + parameter BUF_MIPI_M1_EN = 3'b000; + parameter BUF_SERDES_Q0_EN = 3'b000; + parameter BUF_BK6_EN = 6'b000000; + parameter BUF_BK7_EN = 6'b000000; + parameter CLK_SEL = 1'b0; + parameter PIOCLK_SEL = 1'b0; + parameter VSEN_CTL = 3'b000; + parameter VSEN_CTL_SEL = 1'b0; + parameter ADC_MODE = 1'b0; + parameter DIV_CTL = 2'd0; + parameter SAMPLE_CNT_SEL = 3'd4; + parameter RATE_CHANGE_CTRL = 3'd4; endmodule module ADC (...); + parameter CLK_SEL = 1'b0; + parameter DIV_CTL = 2'd0; + parameter BUF_EN = 12'b000000000000; + parameter BUF_BK0_VREF_EN = 1'b0; + parameter BUF_BK1_VREF_EN = 1'b0; + parameter BUF_BK2_VREF_EN = 1'b0; + parameter BUF_BK3_VREF_EN = 1'b0; + parameter BUF_BK4_VREF_EN = 1'b0; + parameter BUF_BK5_VREF_EN = 1'b0; + parameter BUF_BK6_VREF_EN = 1'b0; + parameter BUF_BK7_VREF_EN = 1'b0; + parameter CSR_ADC_MODE = 1'b1; + parameter CSR_VSEN_CTRL = 3'd0; + parameter CSR_SAMPLE_CNT_SEL = 3'd4; + parameter CSR_RATE_CHANGE_CTRL = 3'd4; + parameter CSR_FSCAL = 10'd730; + parameter CSR_OFFSET = -12'd1180; endmodule module ADC_SAR (...); + parameter BUF_EN = 29'b0; + parameter CLK_SEL = 1'b1; + parameter DIV_CTL = 2'd2; + parameter ADC_EN_SEL = 1'b0; + parameter PHASE_SEL = 1'b0; + parameter CSR_ADC_MODE = 1'b1; + parameter CSR_VSEN_CTRL = 3'd0; + parameter CSR_SAMPLE_CNT_SEL = 3'd4; + parameter CSR_RATE_CHANGE_CTRL = 3'd4; + parameter CSR_FSCAL = 10'd730; + parameter CSR_OFFSET = -12'd1180; + parameter ADC_CLK_DIV = 2'b00; + parameter ADC_CLKDIV_EN = 1'b0; + parameter CLK_SRC_SEL = 1'b1; + parameter VREF_BUF_EN = 1'b1; + parameter COUNT_LEN = 5'b10100; + parameter DAC_SAMPLE_END = 5'b10010; + parameter DAC_SAMPLE_START = 5'b01101; + parameter SH_SAMPLE_END = 5'b01011; + parameter SH_SAMPLE_START = 5'b00001; + parameter AUTO_CHOP_EN = 1'b0; + parameter CHOP_CLK_DIV = 4'b0; endmodule module LICD (...); + parameter STAGE_NUM = 2'b00; + parameter ENCDEC_NUM = 2'b00; + parameter CODE_WIDTH = 2'b00; + parameter INTERLEAVE_EN = 3'b000; + parameter INTERLEAVE_MODE = 3'b000; endmodule module MIPI_DPHY (...); @@ -2456,6 +2539,7 @@ parameter EQ_ZLD_LN2 = 4'b1000; endmodule module GTR12_QUAD (...); + parameter POSITION = "Q0"; endmodule module GTR12_UPAR (...); From b9dc5784119d5ca95847324a64f5a57d9aa66f22 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 21 Sep 2025 00:25:14 +0000 Subject: [PATCH 150/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 720fd6323..4d1a94bc2 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+153 +YOSYS_VER := 0.57+157 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 2de641d051f2246f1cea94dab8a452a7afa4c8d9 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 22 Sep 2025 04:50:36 +0000 Subject: [PATCH 151/188] Don't redirect spawned ABCs' stderr to our pipe. popen() doesn't do this and we should emulate the behavior of popen() as much as possible. --- passes/techmap/abc.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c17f85afd..06b30b9b3 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -244,10 +244,6 @@ std::optional spawn_abc(const char* abc_exe, DeferredLogs &logs) { logs.log_error("posix_spawn_file_actions_adddup2 failed"); return std::nullopt; } - if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDERR_FILENO) != 0) { - logs.log_error("posix_spawn_file_actions_adddup2 failed"); - return std::nullopt; - } if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) { logs.log_error("posix_spawn_file_actions_addclose failed"); return std::nullopt; From 4fc782ef2b7212b5484c418b72b229e15a62604d Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 22 Sep 2025 04:35:48 +0000 Subject: [PATCH 152/188] Make ABC_DONE detection more robust. 1) Change token from ABC_DONE to YOSYS_ABC_DONE to be a bit more robust against false matches. 2) Emit the token from the sourced script so that we don't have to worry about it showing up in the echoing of the command as it executes. It will only appear in ABC stdout when it executes, i.e. when our script has completed. 3) `set abcout` doesn't actually switch ABC to line buffering on stdout, since HAVE_SETVBUF is not actually set in ABC builds in general. So stop using that. ABC does the necessary flushing when `source` has finished. --- passes/techmap/abc.cc | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 06b30b9b3..ff0aa2975 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1065,6 +1065,9 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name); abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name); abc_script = add_echos_to_abc_cmd(abc_script); +#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) + abc_script += "; echo \"YOSYS_ABC_DONE\"\n"; +#endif for (size_t i = 0; i+1 < abc_script.size(); i++) if (abc_script[i] == ';' && abc_script[i+1] == ' ') @@ -1147,9 +1150,7 @@ bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) { break; } line.append(start, p + 1 - start); - // ABC seems to actually print "ABC_DONE \n", but we probably shouldn't - // rely on that extra space being output. - if (line.substr(0, 8) == "ABC_DONE") { + if (line.substr(0, 14) == "YOSYS_ABC_DONE") { // Ignore any leftover output, there should only be a prompt perhaps return true; } @@ -1344,12 +1345,8 @@ void RunAbcState::run(ConcurrentStack &process_pool) return; } std::string cmd = stringf( - // This makes ABC switch stdout to line buffering, which we need - // to see our ABC_DONE message. - "set abcout /dev/stdout\n" "empty\n" - "source %s\n" - "echo \"ABC_DONE\"\n", tmp_script_name); + "source %s\n", tmp_script_name); int ret = write(process.to_child_pipe, cmd.c_str(), cmd.size()); if (ret != static_cast(cmd.size())) { logs.log_error("write failed"); From 7f6fae1f666b2891d1649aa37a07f06df010f9d9 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Fri, 19 Sep 2025 04:01:52 +0000 Subject: [PATCH 153/188] Extract ABC results in the order of `assigned_cells`. Currently the order of extraction can vary based on which ABC runs finish first. That's nondeterministic, therefore bad. Instead, force the processing to happen in the same order as `assigned_cells`, i.e. the same order we use when not using parallelism. This should make everything deterministic. Note that we still allow ABC runs to complete out of order. Out-of-order results are just not extracted until all the previous runs have completed and their results extracted. --- passes/techmap/abc.cc | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c17f85afd..e3426df17 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -293,6 +293,7 @@ struct RunAbcState { struct AbcModuleState { RunAbcState run_abc; + int state_index; int map_autoidx = 0; std::vector signal_bits; dict signal_map; @@ -307,8 +308,8 @@ struct AbcModuleState { int undef_bits_lost = 0; - AbcModuleState(const AbcConfig &config, FfInitVals &initvals) - : run_abc(config), initvals(initvals) {} + AbcModuleState(const AbcConfig &config, FfInitVals &initvals, int state_index) + : run_abc(config), state_index(state_index), initvals(initvals) {} AbcModuleState(AbcModuleState&&) = delete; int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1); @@ -2382,7 +2383,7 @@ struct AbcPass : public Pass { std::vector cells = mod->selected_cells(); assign_cell_connection_ports(mod, {&cells}, assign_map); - AbcModuleState state(config, initvals); + AbcModuleState state(config, initvals, 0); state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str); ConcurrentStack process_pool; state.run_abc.run(process_pool); @@ -2558,7 +2559,6 @@ struct AbcPass : public Pass { int num_worker_threads = ThreadPool::pool_size(1, max_threads); ConcurrentQueue> work_queue(num_worker_threads); ConcurrentQueue> work_finished_queue; - int work_finished_count = 0; ConcurrentStack process_pool; ThreadPool worker_threads(num_worker_threads, [&](int){ while (std::optional> work = @@ -2568,15 +2568,25 @@ struct AbcPass : public Pass { work_finished_queue.push_back(std::move(*work)); } }); + int state_index = 0; + int next_state_index_to_process = 0; + std::vector> work_finished_by_index; + work_finished_by_index.resize(assigned_cells.size()); + int work_finished_count = 0; for (auto &it : assigned_cells) { - // Process ABC results that have already finished before queueing another ABC. - // This should keep our memory usage down. + // Make sure we process the results in the order we expect. When we can + // process results before the next ABC run, do so, to keep memory usage low(er). while (std::optional> work = work_finished_queue.try_pop_front()) { - (*work)->extract(assign_map, design, mod); + work_finished_by_index[(*work)->state_index] = std::move(*work); ++work_finished_count; } - std::unique_ptr state = std::make_unique(config, initvals); + while (work_finished_by_index[next_state_index_to_process] != nullptr) { + work_finished_by_index[next_state_index_to_process]->extract(assign_map, design, mod); + work_finished_by_index[next_state_index_to_process] = nullptr; + ++next_state_index_to_process; + } + std::unique_ptr state = std::make_unique(config, initvals, state_index++); state->clk_polarity = std::get<0>(it.first); state->clk_sig = assign_map(std::get<1>(it.first)); state->en_polarity = std::get<2>(it.first); @@ -2595,12 +2605,17 @@ struct AbcPass : public Pass { } } work_queue.close(); - while (work_finished_count < static_cast(assigned_cells.size())) { + while (work_finished_count < GetSize(assigned_cells)) { std::optional> work = work_finished_queue.pop_front(); - (*work)->extract(assign_map, design, mod); + work_finished_by_index[(*work)->state_index] = std::move(*work); ++work_finished_count; } + while (next_state_index_to_process < GetSize(work_finished_by_index)) { + work_finished_by_index[next_state_index_to_process]->extract(assign_map, design, mod); + work_finished_by_index[next_state_index_to_process] = nullptr; + ++next_state_index_to_process; + } } if (config.cleanup) { From 93dca50b91ab78b98215216825f58870ddd344a2 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 23 Sep 2025 00:22:45 +0000 Subject: [PATCH 154/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1a5d8a093..02f8fa0e9 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+157 +YOSYS_VER := 0.57+178 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 6f7cd637cb36ccecf7d2928ffef7c5a285fa7df1 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 23 Sep 2025 15:02:45 +1200 Subject: [PATCH 155/188] CI: Check repo for YosysHQ specific jobs Prevents unintended bumps on the flake.lock and Yosys version on forks (provided the forks synchronize their main after this gets merged). Update version.yml to use the same style of `if` on the job, rather than on specific actions. Wheels will still build as a cron job, but won't try to upload if it's a fork. --- .github/workflows/update-flake-lock.yml | 1 + .github/workflows/version.yml | 8 +++----- .github/workflows/wheels.yml | 1 + 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/update-flake-lock.yml b/.github/workflows/update-flake-lock.yml index de7ef04d6..b32498baf 100644 --- a/.github/workflows/update-flake-lock.yml +++ b/.github/workflows/update-flake-lock.yml @@ -6,6 +6,7 @@ on: jobs: lockfile: + if: github.repository == 'YosysHQ/Yosys' runs-on: ubuntu-latest steps: - name: Checkout repository diff --git a/.github/workflows/version.yml b/.github/workflows/version.yml index 26dcba4a4..78d34db46 100644 --- a/.github/workflows/version.yml +++ b/.github/workflows/version.yml @@ -7,6 +7,7 @@ on: jobs: bump-version: + if: github.repository == 'YosysHQ/Yosys' runs-on: ubuntu-latest steps: - name: Checkout @@ -18,11 +19,8 @@ jobs: - name: Take last commit id: log run: echo "message=$(git log --no-merges -1 --oneline)" >> $GITHUB_OUTPUT - - name: Take repository - id: repo - run: echo "message=$GITHUB_REPOSITORY" >> $GITHUB_OUTPUT - name: Bump version - if: "!contains(steps.log.outputs.message, 'Bump version') && contains(steps.repo.outputs.message, 'YosysHQ/yosys')" + if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} run: | make bumpversion git config --local user.email "41898282+github-actions[bot]@users.noreply.github.com" @@ -30,7 +28,7 @@ jobs: git add Makefile git commit -m "Bump version" - name: Push changes # push the output folder to your repo - if: "!contains(steps.log.outputs.message, 'Bump version') && contains(steps.repo.outputs.message, 'YosysHQ/yosys')" + if: ${{ !contains(steps.log.outputs.message, 'Bump version') }} uses: ad-m/github-push-action@master with: github_token: ${{ secrets.GITHUB_TOKEN }} diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 41d9183fc..2a5b7e024 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -124,6 +124,7 @@ jobs: path: ./wheelhouse/*.whl upload_wheels: name: Upload Wheels + if: github.repository == 'YosysHQ/Yosys' runs-on: ubuntu-latest # Specifying a GitHub environment is optional, but strongly encouraged environment: pypi From effc52fedccca3659f225f3c72f07abc19eeec44 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 23 Sep 2025 03:25:16 +0000 Subject: [PATCH 156/188] Make `ID::` constants be `StaticIdString`s for better optimization. Their internal indexes will be known at compile time, like we already support for the `ID()` macro. --- kernel/rtlil.cc | 2 +- kernel/rtlil.h | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d53fdd32..35776746d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -46,7 +46,7 @@ int RTLIL::IdString::last_created_idx_[8]; int RTLIL::IdString::last_created_idx_ptr_; #endif -#define X(N) const RTLIL::IdString RTLIL::ID::N(RTLIL::StaticId::N); +#define X(_id) const RTLIL::IdString RTLIL::IDInternal::_id(RTLIL::StaticId::_id); #include "kernel/constids.inc" #undef X diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 096d1dfcf..88594859a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -495,9 +495,14 @@ inline bool RTLIL::IdString::operator!=(const RTLIL::StaticIdString &rhs) const } namespace RTLIL { - namespace ID { + namespace IDInternal { #define X(_id) extern const IdString _id; #include "kernel/constids.inc" +#undef X + } + namespace ID { +#define X(_id) constexpr StaticIdString _id(StaticId::_id, IDInternal::_id); +#include "kernel/constids.inc" #undef X } } @@ -508,7 +513,7 @@ struct IdTableEntry { }; constexpr IdTableEntry IdTable[] = { -#define X(_id) {#_id, RTLIL::StaticIdString(RTLIL::StaticId::_id, RTLIL::ID::_id)}, +#define X(_id) {#_id, ID::_id}, #include "kernel/constids.inc" #undef X }; From 1e5f920dbddd94a762d07b5dc94a16a3e8c38f89 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Mon, 22 Sep 2025 22:04:17 +0000 Subject: [PATCH 157/188] Remove .c_str() from parameters to log_debug() --- backends/aiger2/aiger.cc | 2 +- frontends/aiger/aigerparse.cc | 2 +- frontends/rpc/rpc_frontend.cc | 4 ++-- kernel/cost.cc | 20 ++++++++++---------- kernel/fstdata.cc | 4 ++-- passes/cmds/abstract.cc | 4 ++-- passes/cmds/box_derive.cc | 2 +- passes/cmds/linecoverage.cc | 4 ++-- passes/memory/memory_libmap.cc | 26 +++++++++++++------------- passes/opt/opt_clean.cc | 8 ++++---- passes/opt/opt_lut.cc | 14 +++++++------- passes/opt/opt_merge.cc | 6 +++--- passes/techmap/clockgate.cc | 8 ++++---- passes/techmap/dfflibmap.cc | 12 ++++++------ passes/techmap/techmap.cc | 10 +++++----- passes/tests/test_cell.cc | 2 +- techlibs/quicklogic/ql_ioff.cc | 6 +++--- 17 files changed, 67 insertions(+), 67 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 05714bc2e..b63e51bde 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1017,7 +1017,7 @@ struct XAigerWriter : AigerWriter { auto &minfo = cursor.leaf_minfo(*this); for (auto box : minfo.found_blackboxes) { - log_debug(" - %s.%s (type %s): ", cursor.path().c_str(), + log_debug(" - %s.%s (type %s): ", cursor.path(), RTLIL::unescape_id(box->name), log_id(box->type)); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 70d94faff..4df37c0cd 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -476,7 +476,7 @@ void AigerReader::parse_xaiger() else if (c == 'n') { parse_xaiger_literal(f); f >> s; - log_debug("n: '%s'\n", s.c_str()); + log_debug("n: '%s'\n", s); } else if (c == 'h') { f.ignore(sizeof(uint32_t)); diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 625b2c0e8..c21867b30 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -83,11 +83,11 @@ struct RpcServer { std::string request; json_request.dump(request); request += '\n'; - log_debug("RPC frontend request: %s", request.c_str()); + log_debug("RPC frontend request: %s", request); write(request); std::string response = read(); - log_debug("RPC frontend response: %s", response.c_str()); + log_debug("RPC frontend response: %s", response); std::string error; Json json_response = Json::parse(response, error); if (json_response.is_null()) diff --git a/kernel/cost.cc b/kernel/cost.cc index 29787fa52..4942823d3 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -143,14 +143,14 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) return 1; if (design_ && design_->module(cell->type) && cell->parameters.empty()) { - log_debug("%s is a module, recurse\n", cell->name.c_str()); + log_debug("%s is a module, recurse\n", cell->name); return get(design_->module(cell->type)); } else if (cell->is_builtin_ff()) { log_assert(cell->hasPort(ID::Q) && "Weird flip flop"); - log_debug("%s is ff\n", cell->name.c_str()); + log_debug("%s is ff\n", cell->name); return cell->getParam(ID::WIDTH).as_int(); } else if (cell->type.in(ID($mem), ID($mem_v2))) { - log_debug("%s is mem\n", cell->name.c_str()); + log_debug("%s is mem\n", cell->name); return cell->getParam(ID::WIDTH).as_int() * cell->getParam(ID::SIZE).as_int(); } else if (y_coef(cell->type)) { // linear with Y_WIDTH or WIDTH @@ -159,23 +159,23 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) int width = cell->getParam(param).as_int(); if (cell->type == ID($demux)) width <<= cell->getParam(ID::S_WIDTH).as_int(); - log_debug("%s Y*coef %d * %d\n", cell->name.c_str(), width, y_coef(cell->type)); + log_debug("%s Y*coef %d * %d\n", cell->name, width, y_coef(cell->type)); return width * y_coef(cell->type); } else if (sum_coef(cell->type)) { // linear with sum of port widths unsigned int sum = port_width_sum(cell); - log_debug("%s sum*coef %d * %d\n", cell->name.c_str(), sum, sum_coef(cell->type)); + log_debug("%s sum*coef %d * %d\n", cell->name, sum, sum_coef(cell->type)); return sum * sum_coef(cell->type); } else if (max_inp_coef(cell->type)) { // linear with largest input width unsigned int max = max_inp_width(cell); - log_debug("%s max*coef %d * %d\n", cell->name.c_str(), max, max_inp_coef(cell->type)); + log_debug("%s max*coef %d * %d\n", cell->name, max, max_inp_coef(cell->type)); return max * max_inp_coef(cell->type); } else if (is_div_mod(cell->type) || cell->type == ID($mul)) { // quadratic with sum of port widths unsigned int sum = port_width_sum(cell); unsigned int coef = cell->type == ID($mul) ? 3 : 5; - log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum); + log_debug("%s coef*(sum**2) %d * %d\n", cell->name, coef, sum * sum); return coef * sum * sum; } else if (cell->type.in(ID($macc), ID($macc_v2))) { // quadratic per term @@ -196,15 +196,15 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) } else if (cell->type == ID($lut)) { int width = cell->getParam(ID::WIDTH).as_int(); unsigned int cost = 1U << (unsigned int)width; - log_debug("%s is 2**%d\n", cell->name.c_str(), width); + log_debug("%s is 2**%d\n", cell->name, width); return cost; } else if (cell->type == ID($sop)) { int width = cell->getParam(ID::WIDTH).as_int(); int depth = cell->getParam(ID::DEPTH).as_int(); - log_debug("%s is (2*%d + 1)*%d\n", cell->name.c_str(), width, depth); + log_debug("%s is (2*%d + 1)*%d\n", cell->name, width, depth); return (2 * width + 1) * depth; } else if (is_free(cell->type)) { - log_debug("%s is free\n", cell->name.c_str()); + log_debug("%s is free\n", cell->name); return 0; } // TODO: $fsm diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index cc558d418..f0f00181c 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -162,7 +162,7 @@ void FstData::extractVarNames() char *endptr; int mem_addr = strtol(addr.c_str(), &endptr, 16); if (*endptr) { - log_debug("Error parsing memory address in : %s\n", clean_name.c_str()); + log_debug("Error parsing memory address in : %s\n", clean_name); } else { memory_to_handle[var.scope+"."+mem_cell][mem_addr] = var.id; } @@ -176,7 +176,7 @@ void FstData::extractVarNames() char *endptr; int mem_addr = strtol(addr.c_str(), &endptr, 10); if (*endptr) { - log_debug("Error parsing memory address in : %s\n", clean_name.c_str()); + log_debug("Error parsing memory address in : %s\n", clean_name); } else { memory_to_handle[var.scope+"."+mem_cell][mem_addr] = var.id; } diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index 88f07a5aa..2ea71268b 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -156,9 +156,9 @@ dict> gather_selected_reps(Module* mod, const std void explain_selections(const std::vector& reasons) { for (std::variant reason : reasons) { if (Cell** cell_reason = std::get_if(&reason)) - log_debug("\tcell %s\n", (*cell_reason)->name.c_str()); + log_debug("\tcell %s\n", (*cell_reason)->name); else if (Wire** wire_reason = std::get_if(&reason)) - log_debug("\twire %s\n", (*wire_reason)->name.c_str()); + log_debug("\twire %s\n", (*wire_reason)->name); else log_assert(false && "insane reason variant\n"); } diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc index da698b04d..a0faacc9a 100644 --- a/passes/cmds/box_derive.cc +++ b/passes/cmds/box_derive.cc @@ -96,7 +96,7 @@ struct BoxDerivePass : Pass { IdString derived_type = base->derive(d, cell->parameters); Module *derived = d->module(derived_type); log_assert(derived && "Failed to derive module\n"); - log_debug("derived %s\n", derived_type.c_str()); + log_debug("derived %s\n", derived_type); if (!naming_attr.empty() && derived->has_attribute(naming_attr)) { IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr)); diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 6898f33f5..26adcce76 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -95,7 +95,7 @@ struct CoveragePass : public Pass { { log_debug("Module %s:\n", log_id(module)); for (auto wire: module->wires()) { - log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute().c_str(), log_id(wire->name)); + log_debug("%s\t%s\t%s\n", module->selected(wire) ? "*" : " ", wire->get_src_attribute(), log_id(wire->name)); for (auto src: wire->get_strpool_attribute(ID::src)) { auto filename = extract_src_filename(src); if (filename.empty()) continue; @@ -109,7 +109,7 @@ struct CoveragePass : public Pass { } } for (auto cell: module->cells()) { - log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute().c_str(), log_id(cell->name)); + log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), log_id(cell->name)); for (auto src: cell->get_strpool_attribute(ID::src)) { auto filename = extract_src_filename(src); if (filename.empty()) continue; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 0fb4608b1..c3c10363b 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -392,7 +392,7 @@ void MemMapping::dump_configs(int stage) { void MemMapping::dump_config(MemConfig &cfg) { log_debug("- %s:\n", log_id(cfg.def->id)); for (auto &it: cfg.def->options) - log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second)); + log_debug(" - option %s %s\n", it.first, log_const(it.second)); log_debug(" - emulation score: %d\n", cfg.score_emu); log_debug(" - replicates (for ports): %d\n", cfg.repl_port); log_debug(" - replicates (for data): %d\n", cfg.repl_d); @@ -403,7 +403,7 @@ void MemMapping::dump_config(MemConfig &cfg) { for (int x: cfg.def->dbits) os << " " << x; std::string dbits_s = os.str(); - log_debug(" - abits %d dbits%s\n", cfg.def->abits, dbits_s.c_str()); + log_debug(" - abits %d dbits%s\n", cfg.def->abits, dbits_s); if (cfg.def->byte != 0) log_debug(" - byte width %d\n", cfg.def->byte); log_debug(" - chosen base width %d\n", cfg.def->dbits[cfg.base_width_log2]); @@ -414,25 +414,25 @@ void MemMapping::dump_config(MemConfig &cfg) { else os << " " << x; std::string swizzle_s = os.str(); - log_debug(" - swizzle%s\n", swizzle_s.c_str()); + log_debug(" - swizzle%s\n", swizzle_s); os.str(""); for (int i = 0; (1 << i) <= cfg.hard_wide_mask; i++) if (cfg.hard_wide_mask & 1 << i) os << " " << i; std::string wide_s = os.str(); if (cfg.hard_wide_mask) - log_debug(" - hard wide bits%s\n", wide_s.c_str()); + log_debug(" - hard wide bits%s\n", wide_s); if (cfg.emu_read_first) log_debug(" - emulate read-first behavior\n"); for (int i = 0; i < GetSize(mem.wr_ports); i++) { auto &pcfg = cfg.wr_ports[i]; if (pcfg.rd_port == -1) - log_debug(" - write port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str()); + log_debug(" - write port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0]); else - log_debug(" - write port %d: port group %s (shared with read port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.rd_port); + log_debug(" - write port %d: port group %s (shared with read port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0], pcfg.rd_port); for (auto &it: pcfg.def->options) - log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second)); + log_debug(" - option %s %s\n", it.first, log_const(it.second)); if (cfg.def->width_mode == WidthMode::PerPort) { std::stringstream os; for (int i = pcfg.def->min_wr_wide_log2; i <= pcfg.def->max_wr_wide_log2; i++) @@ -441,7 +441,7 @@ void MemMapping::dump_config(MemConfig &cfg) { const char *note = ""; if (pcfg.rd_port != -1) note = pcfg.def->width_tied ? " (tied)" : " (independent)"; - log_debug(" - widths%s%s\n", widths_s.c_str(), note); + log_debug(" - widths%s%s\n", widths_s, note); } for (auto i: pcfg.emu_prio) log_debug(" - emulate priority over write port %d\n", i); @@ -449,11 +449,11 @@ void MemMapping::dump_config(MemConfig &cfg) { for (int i = 0; i < GetSize(mem.rd_ports); i++) { auto &pcfg = cfg.rd_ports[i]; if (pcfg.wr_port == -1) - log_debug(" - read port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str()); + log_debug(" - read port %d: port group %s\n", i, cfg.def->port_groups[pcfg.port_group].names[0]); else - log_debug(" - read port %d: port group %s (shared with write port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0].c_str(), pcfg.wr_port); + log_debug(" - read port %d: port group %s (shared with write port %d)\n", i, cfg.def->port_groups[pcfg.port_group].names[0], pcfg.wr_port); for (auto &it: pcfg.def->options) - log_debug(" - option %s %s\n", it.first.c_str(), log_const(it.second)); + log_debug(" - option %s %s\n", it.first, log_const(it.second)); if (cfg.def->width_mode == WidthMode::PerPort) { std::stringstream os; for (int i = pcfg.def->min_rd_wide_log2; i <= pcfg.def->max_rd_wide_log2; i++) @@ -462,7 +462,7 @@ void MemMapping::dump_config(MemConfig &cfg) { const char *note = ""; if (pcfg.wr_port != -1) note = pcfg.def->width_tied ? " (tied)" : " (independent)"; - log_debug(" - widths%s%s\n", widths_s.c_str(), note); + log_debug(" - widths%s%s\n", widths_s, note); } if (pcfg.emu_sync) log_debug(" - emulate data register\n"); @@ -2242,7 +2242,7 @@ struct MemoryLibMapPass : public Pass { if (!map.logic_ok) { if (map.cfgs.empty()) { log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module->name), log_id(mem.memid)); - log_debug("%s", map.rejected_cfg_debug_msgs.c_str()); + log_debug("%s", map.rejected_cfg_debug_msgs); log_error("no valid mapping found for memory %s.%s\n", log_id(module->name), log_id(mem.memid)); } idx = 0; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index a254dc915..dc3f015cd 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -204,7 +204,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto cell : unused) { if (verbose) - log_debug(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); + log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name); module->design->scratchpad_set_bool("opt.did_something", true); if (cell->is_builtin_ff()) ffinit.remove_init(cell->getPort(ID::Q)); @@ -215,7 +215,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto it : mem_unused) { if (verbose) - log_debug(" removing unused memory `%s'.\n", it.c_str()); + log_debug(" removing unused memory `%s'.\n", it); delete module->memories.at(it); module->memories.erase(it); } @@ -496,7 +496,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos int del_temp_wires_count = 0; for (auto wire : del_wires_queue) { if (ys_debug() || (check_public_name(wire->name) && verbose)) - log_debug(" removing unused non-port wire %s.\n", wire->name.c_str()); + log_debug(" removing unused non-port wire %s.\n", wire->name); else del_temp_wires_count++; } @@ -636,7 +636,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool } for (auto cell : delcells) { if (verbose) - log_debug(" removing buffer cell `%s': %s = %s\n", cell->name.c_str(), + log_debug(" removing buffer cell `%s': %s = %s\n", cell->name, log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A))); module->remove(cell); } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 37ae38225..c0a017748 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -162,7 +162,7 @@ struct OptLutWorker { if (lut_width <= dlogic_conn.first) { - log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second)); + log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second)); log_debug(" LUT input A[%d] not present.\n", dlogic_conn.first); legal = false; break; @@ -173,8 +173,8 @@ struct OptLutWorker if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0])) { - log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second)); - log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second))); + log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second)); + log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type, dlogic_conn.second, log_signal(lut_dlogic.second->getPort(dlogic_conn.second))); legal = false; break; } @@ -182,7 +182,7 @@ struct OptLutWorker if (legal) { - log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second)); + log_debug(" LUT has legal connection to %s cell %s.%s.\n", lut_dlogic.second->type, log_id(module), log_id(lut_dlogic.second)); lut_legal_dlogics.insert(lut_dlogic); for (auto &dlogic_conn : dlogic_map) lut_dlogic_inputs.insert(dlogic_conn.first); @@ -496,9 +496,9 @@ struct OptLutWorker lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs)); } - log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str()); - log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str()); - log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str()); + log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string()); + log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string()); + log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string()); lutM->setParam(ID::LUT, lutM_new_table); lutM->setPort(ID::A, lutM_new_inputs); diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 1cb499740..541459c27 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -300,11 +300,11 @@ struct OptMergeWorker } did_something = true; - log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), other_cell->name.c_str()); + log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name); for (auto &it : cell->connections()) { if (cell->output(it.first)) { RTLIL::SigSpec other_sig = other_cell->getPort(it.first); - log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(), + log_debug(" Redirecting output %s: %s = %s\n", it.first, log_signal(it.second), log_signal(other_sig)); Const init = initvals(other_sig); initvals.remove_init(it.second); @@ -314,7 +314,7 @@ struct OptMergeWorker initvals.set_init(other_sig, init); } } - log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); + log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); module->remove(cell); total_count++; } diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index f4e0b0f03..7c6ca5551 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -85,7 +85,7 @@ static std::pair, std::optional> continue; } - log_debug("maybe valid icg: %s\n", cell_name.c_str()); + log_debug("maybe valid icg: %s\n", cell_name); ClockGateCell icg_interface; icg_interface.name = RTLIL::escape_id(cell_name); @@ -162,9 +162,9 @@ static std::pair, std::optional> winning = cost < goal; if (winning) - log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str()); + log_debug("%s beats %s\n", icg_interface.name, icg_to_beat->name); } else { - log_debug("%s is the first of its polarity\n", icg_interface.name.c_str()); + log_debug("%s is the first of its polarity\n", icg_interface.name); winning = true; } if (winning) { @@ -395,7 +395,7 @@ struct ClockgatePass : public Pass { if (!it->second.new_net) continue; - log_debug("Fix up FF %s\n", cell->name.c_str()); + log_debug("Fix up FF %s\n", cell->name); // Now we start messing with the design ff.has_ce = false; // Construct the clock gate diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 062a63ec3..f3b96aeec 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -117,11 +117,11 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std // the next_state variable isn't just a pin name; perhaps this is an enable? auto helper = LibertyExpression::Lexer(expr); auto tree = LibertyExpression::parse(helper); - // log_debug("liberty expression:\n%s\n", tree.str().c_str()); + // log_debug("liberty expression:\n%s\n", tree.str()); if (tree.kind == LibertyExpression::Kind::EMPTY) { if (!warned_cells.count(cell_name)) { - log_debug("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr.c_str(), cell_name.c_str()); + log_debug("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr, cell_name); warned_cells.insert(cell_name); } return false; @@ -140,7 +140,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std // position that gives better diagnostics here. if (!pin_names.count(ff_output)) { if (!warned_cells.count(cell_name)) { - log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr.c_str(), cell_name.c_str(), ff_output.c_str()); + log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr, cell_name, ff_output); warned_cells.insert(cell_name); } return false; @@ -189,7 +189,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std } if (!warned_cells.count(cell_name)) { - log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr.c_str(), cell_name.c_str()); + log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr, cell_name); warned_cells.insert(cell_name); } return false; @@ -225,10 +225,10 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin For now, we'll simply produce a warning to let the user know something is up. */ if (pin_name.find_first_of("^*|&") == std::string::npos) { - log_debug("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + log_debug("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name, cell->args[0]); } else { - log_debug("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + log_debug("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name, cell->args[0]); } return false; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 281a8795a..b49a40704 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -582,7 +582,7 @@ struct TechmapWorker log_msg_cache.insert(msg); log("%s\n", msg); } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); } else { @@ -591,7 +591,7 @@ struct TechmapWorker log_msg_cache.insert(msg); log("%s\n", msg); } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), extmapper_name); if (extmapper_name == "simplemap") { if (simplemap_mappers.count(cell->type) == 0) @@ -943,7 +943,7 @@ struct TechmapWorker module_queue.insert(m); } - log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name)); + log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(m_name)); cell->type = m_name; cell->parameters.clear(); } @@ -954,7 +954,7 @@ struct TechmapWorker log_msg_cache.insert(msg); log("%s\n", msg); } - log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); + log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix, log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); cell = nullptr; } @@ -1285,7 +1285,7 @@ struct TechmapPass : public Pass { std::string maps = ""; for (auto &map : i.second) maps += stringf(" %s", log_id(map)); - log_debug(" %s:%s\n", log_id(i.first), maps.c_str()); + log_debug(" %s:%s\n", log_id(i.first), maps); } log_debug("\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 9603956a8..73af155bd 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -1185,7 +1185,7 @@ struct TestCellPass : public Pass { // Expected to run once int num_cells_estimate = costs.get(uut); if (num_cells <= num_cells_estimate) { - log_debug("Correct upper bound for %s: %d <= %d\n", cell_type.c_str(), num_cells, num_cells_estimate); + log_debug("Correct upper bound for %s: %d <= %d\n", cell_type, num_cells, num_cells_estimate); } else { failed++; if (worst_abs < num_cells - num_cells_estimate) { diff --git a/techlibs/quicklogic/ql_ioff.cc b/techlibs/quicklogic/ql_ioff.cc index 87b62e855..5574ef4a0 100644 --- a/techlibs/quicklogic/ql_ioff.cc +++ b/techlibs/quicklogic/ql_ioff.cc @@ -42,7 +42,7 @@ struct QlIoffPass : public Pass { for (auto cell : module->selected_cells()) { if (cell->type.in(ID(dffsre), ID(sdffsre))) { - log_debug("Checking cell %s.\n", cell->name.c_str()); + log_debug("Checking cell %s.\n", cell->name); bool e_const = cell->getPort(ID::E).is_fully_ones(); bool r_const = cell->getPort(ID::R).is_fully_ones(); bool s_const = cell->getPort(ID::S).is_fully_ones(); @@ -55,7 +55,7 @@ struct QlIoffPass : public Pass { SigSpec d = cell->getPort(ID::D); log_assert(GetSize(d) == 1); if (modwalker.has_inputs(d)) { - log_debug("Cell %s is potentially eligible for promotion to input IOFF.\n", cell->name.c_str()); + log_debug("Cell %s is potentially eligible for promotion to input IOFF.\n", cell->name); // check that d_sig has no other consumers pool portbits; modwalker.get_consumers(portbits, d); @@ -70,7 +70,7 @@ struct QlIoffPass : public Pass { SigSpec q = cell->getPort(ID::Q); log_assert(GetSize(q) == 1); if (modwalker.has_outputs(q) && !modwalker.has_consumers(q)) { - log_debug("Cell %s is potentially eligible for promotion to output IOFF.\n", cell->name.c_str()); + log_debug("Cell %s is potentially eligible for promotion to output IOFF.\n", cell->name); for (SigBit bit : output_bit_aliases[modwalker.sigmap(q)]) { log_assert(bit.is_wire()); output_ffs[bit.wire][bit.offset] = cell; From 398e5d4bf0b02cda6c404c5820d73ed2ce9cc84d Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 23 Sep 2025 14:34:20 +0100 Subject: [PATCH 158/188] docs typo: -dump-cmds-json --- docs/source/cmd/index_internal.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/cmd/index_internal.rst b/docs/source/cmd/index_internal.rst index bfb369dde..ab9c13aba 100644 --- a/docs/source/cmd/index_internal.rst +++ b/docs/source/cmd/index_internal.rst @@ -67,7 +67,7 @@ The ``formatted_help()`` method Dumping command help to json ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- `help -dump-cells-json cmds.json` +- `help -dump-cmds-json cmds.json` + generates a ``ContentListing`` for each command registered in Yosys + tries to parse unformatted ``Pass::help()`` output if From d30f7847d84f015f0f71895f3586fe7da4eb5520 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Apr 2025 13:16:49 +0200 Subject: [PATCH 159/188] techmap: map $alu to $fa instead of relying on extract_fa --- techlibs/common/techmap.v | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 7a9ad7693..c3364e628 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -283,9 +283,16 @@ module _90_alu (A, B, CI, BI, X, Y, CO); \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO)); + (* force_downto *) + wire [Y_WIDTH-1:0] P; + wire [Y_WIDTH-1:0] G; + wire [Y_WIDTH-1:0] Cnull; + assign Cnull = 1'b0; - assign X = AA ^ BB; + \$fa #(.WIDTH(Y_WIDTH)) fa (.A(AA), .B(BB), .C(Cnull), .X(G), .Y(P)); + \$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(P), .G(G), .CI(CI), .CO(CO)); + + assign X = P; assign Y = X ^ {CO, CI}; endmodule From fcc3d7132d39ab9e03a927b72c55ebdfbfcd270d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= Date: Tue, 23 Sep 2025 17:10:18 +0200 Subject: [PATCH 160/188] Fix building and running unit tests (#5374) * Fix building and running unit tests * Enable unit tests * Add gtest always * test-sanitizers.yml: Use makefile.conf * proper test setup * make it run on macOS * Run libyosys build only for unit tests after testing is done * Disable LTO on public CI --------- Co-authored-by: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> --- .github/actions/setup-build-env/action.yml | 2 +- .github/workflows/prepare-docs.yml | 2 +- .github/workflows/test-build.yml | 2 +- .github/workflows/test-sanitizers.yml | 9 +++-- .github/workflows/test-verific.yml | 5 +++ Brewfile | 1 + tests/unit/Makefile | 42 +++++++++++++++++----- tests/unit/kernel/rtlilTest.cc | 3 ++ 8 files changed, 53 insertions(+), 13 deletions(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 1c2386b06..e4bc8ec58 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -8,7 +8,7 @@ runs: shell: bash run: | sudo apt-get update - sudo apt-get install gperf build-essential bison flex libfl-dev libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev libbz2-dev + sudo apt-get install gperf build-essential bison flex libfl-dev libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev libbz2-dev libgtest-dev - name: Install macOS Dependencies if: runner.os == 'macOS' diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 17d37d08c..f19b1c7af 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -48,7 +48,7 @@ jobs: echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf echo "ENABLE_CCACHE := 1" >> Makefile.conf echo "ENABLE_HELP_SOURCE := 1" >> Makefile.conf - make -j$procs ENABLE_LTO=1 + make -j$procs - name: Prepare docs shell: bash diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index d7f2073fe..2d4a7a6c8 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -67,7 +67,7 @@ jobs: mkdir build cd build make -f ../Makefile config-$CC - make -f ../Makefile -j$procs ENABLE_LTO=1 + make -f ../Makefile -j$procs - name: Log yosys-config output run: | diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 2ffd2db15..9c0f6d746 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -97,7 +97,7 @@ jobs: run: | make config-$CC echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf - make -j$procs ENABLE_LTO=1 + make -j$procs - name: Log yosys-config output run: | @@ -106,10 +106,15 @@ jobs: - name: Run tests shell: bash run: | - make -j$procs test TARGETS= EXTRA_TARGETS= CONFIG=$CC + make -j$procs test TARGETS= EXTRA_TARGETS= - name: Report errors if: ${{ failure() }} shell: bash run: | find tests/**/*.err -print -exec cat {} \; + + - name: Run unit tests + shell: bash + run: | + make -j$procs unit-test ENABLE_LIBYOSYS=1 diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index c2e4228c4..503d6c31b 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -78,3 +78,8 @@ jobs: if: ${{ github.ref == 'refs/heads/main' }} run: | make -C sby run_ci + + - name: Run unit tests + shell: bash + run: | + make -j$procs unit-test ENABLE_LTO=1 ENABLE_LIBYOSYS=1 diff --git a/Brewfile b/Brewfile index 7ed3fb906..c90434e62 100644 --- a/Brewfile +++ b/Brewfile @@ -11,3 +11,4 @@ brew "bash" brew "boost-python3" brew "llvm@20" brew "lld" +brew "googletest" diff --git a/tests/unit/Makefile b/tests/unit/Makefile index 48635eb0d..eee60ef9f 100644 --- a/tests/unit/Makefile +++ b/tests/unit/Makefile @@ -1,11 +1,27 @@ -GTESTFLAG := -lgtest -lgtest_main -RPATH := -Wl,-rpath -EXTRAFLAGS := -lyosys -pthreads +UNAME_S := $(shell uname -s) + +# GoogleTest flags +GTEST_PREFIX := $(shell brew --prefix googletest 2>/dev/null) +ifeq ($(GTEST_PREFIX),) + GTEST_CXXFLAGS := + GTEST_LDFLAGS := -lgtest -lgtest_main +else + GTEST_CXXFLAGS := -I$(GTEST_PREFIX)/include + GTEST_LDFLAGS := -L$(GTEST_PREFIX)/lib -lgtest -lgtest_main +endif + +ifeq ($(UNAME_S),Darwin) + RPATH = -Wl,-rpath,$(ROOTPATH) +else + RPATH = -Wl,-rpath=$(ROOTPATH) +endif + +EXTRAFLAGS := -lyosys -pthread OBJTEST := objtest BINTEST := bintest -ALLTESTFILE := $(shell find -name '*Test.cc' -printf '%P ') +ALLTESTFILE := $(shell find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') TESTDIRS := $(sort $(dir $(ALLTESTFILE))) TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o))) @@ -15,16 +31,26 @@ TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o))) all: prepare $(TESTS) run-tests $(BINTEST)/%: $(OBJTEST)/%.o - $(CXX) -L$(ROOTPATH) $(RPATH)=$(ROOTPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \ - $(GTESTFLAG) $(EXTRAFLAGS) + $(CXX) -L$(ROOTPATH) $(RPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \ + $(GTEST_LDFLAGS) $(EXTRAFLAGS) $(OBJTEST)/%.o: $(basename $(subst $(OBJTEST),.,%)).cc - $(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $^ + $(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $(GTEST_CXXFLAGS) $^ .PHONY: prepare run-tests clean run-tests: $(TESTS) - $(subst Test ,Test&& ,$^) +ifeq ($(UNAME_S),Darwin) + @for t in $^; do \ + echo "Running $$t"; \ + DYLD_LIBRARY_PATH=$(ROOTPATH) $$t || exit 1; \ + done +else + @for t in $^; do \ + echo "Running $$t"; \ + $$t || exit 1; \ + done +endif prepare: mkdir -p $(addprefix $(BINTEST)/,$(TESTDIRS)) diff --git a/tests/unit/kernel/rtlilTest.cc b/tests/unit/kernel/rtlilTest.cc index 97cc936de..557355ed9 100644 --- a/tests/unit/kernel/rtlilTest.cc +++ b/tests/unit/kernel/rtlilTest.cc @@ -20,6 +20,9 @@ namespace RTLIL { KernelRtlilTest() { if (log_files.empty()) log_files.emplace_back(stdout); } + virtual void SetUp() override { + IdString::ensure_prepopulated(); + } }; TEST_F(KernelRtlilTest, ConstAssignCompare) From 9409a11be46ae1d582c0c92b7b50fd2ea2092278 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= Date: Tue, 23 Sep 2025 19:25:55 +0200 Subject: [PATCH 161/188] CONTRIBUTING: don't mention dead slack, add link to dev jf doc --- CONTRIBUTING.md | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 74f9ab10d..6e7b8f221 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -61,13 +61,10 @@ merge; please do not use these labels if you are not a maintainer. # Asking questions If you have a question about how to use Yosys, please ask on our [discussions -page](https://github.com/YosysHQ/yosys/discussions) or in our [community -slack](https://join.slack.com/t/yosyshq/shared_invite/zt-1aopkns2q-EiQ97BeQDt_pwvE41sGSuA). -The slack is also a great place to ask questions about developing or +page](https://github.com/YosysHQ/yosys/discussions) or in our [Discourse forum](https://yosyshq.discourse.group/). +The Discourse is also a great place to ask questions about developing or contributing to Yosys. -We have open dev 'jour fixe' (JF) meetings where developers from YosysHQ and the +We have open [dev 'jour fixe' (JF) meetings](https://docs.google.com/document/d/1SapA6QAsJcsgwsdKJDgnGR2mr97pJjV4eeXg_TVJhRU/edit?usp=sharing) where developers from YosysHQ and the community come together to discuss open issues and PRs. This is also a good -place to talk to us about how to implement larger PRs. Please join the -community slack if you would like to join the next meeting, the link is -available in the description of the #devel-discuss channel. +place to talk to us about how to implement larger PRs. From 6527cc2134c818b0084a47c82e664c8d198725dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= Date: Tue, 23 Sep 2025 20:03:50 +0200 Subject: [PATCH 162/188] gowin: fix test --- tests/arch/gowin/mux.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index d5978f4ea..2ca973520 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -32,8 +32,8 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT1 -select -assert-count 10 t:LUT3 +select -assert-count 3 t:LUT1 +select -assert-count 2 t:LUT3 select -assert-count 1 t:LUT4 select -assert-count 5 t:MUX2_LUT5 select -assert-count 2 t:MUX2_LUT6 From 3f4b6dc5d31d8f790ad4d5fb7696f10f77d3362e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 23 Sep 2025 20:34:08 +0200 Subject: [PATCH 163/188] Support multiple lib files in abc9_exe --- passes/techmap/abc9_exe.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index ac723fdbb..4449065f8 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -181,8 +181,10 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe for (std::string dont_use_cell : dont_use_cells) { dont_use_args += stringf("-X \"%s\" ", dont_use_cell); } + bool first_lib = true; for (std::string liberty_file : liberty_files) { - abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args, liberty_file); + abc9_script += stringf("read_lib %s %s -w \"%s\" ; ", dont_use_args, first_lib ? "" : "-m", liberty_file); + first_lib = false; } if (!constr_file.empty()) abc9_script += stringf("read_constr -v \"%s\"; ", constr_file); From 0a17205a955eb9eb95c2e89764d354b82bfc22f4 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 17 Sep 2025 22:27:16 +0000 Subject: [PATCH 164/188] Fix off-by-one error in bounds check --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 7d53fdd32..3c6843aaa 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -4399,7 +4399,7 @@ RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const RTLIL::SigBit RTLIL::SigChunk::operator[](int offset) const { log_assert(offset >= 0); - log_assert(offset <= width); + log_assert(offset < width); RTLIL::SigBit ret; if (wire) { ret.wire = wire; From e9aacd8a0593009b469a1933873bedd49caacaef Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 23 Sep 2025 23:26:47 +0000 Subject: [PATCH 165/188] Move `OptMerge` cell filtering logic to happen while building the cell vector. This code is quite confusing because there are two "is the cell known" filters applied, one while building the cell vector and one after building the cell vector, and they're subtly different. I'm preserving the actual behaviour here but it looks like there is, or was, a bug here. --- passes/opt/opt_merge.cc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 1cb499740..a59807be1 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -249,10 +249,15 @@ struct OptMergeWorker // mem can have an excessively large parameter holding the init data continue; } + if (cell->type == ID($scopeinfo)) + continue; if (mode_keepdc && has_dont_care_initval(cell)) continue; - if (ct.cell_known(cell->type) || (mode_share_all && cell->known())) - cells.push_back(cell); + if (!cell->known()) + continue; + if (!mode_share_all && !ct.cell_known(cell->type)) + continue; + cells.push_back(cell); } did_something = false; @@ -281,12 +286,6 @@ struct OptMergeWorker for (auto cell : cells) { - if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) - continue; - - if (cell->type == ID($scopeinfo)) - continue; - auto [cell_in_map, inserted] = known_cells.insert(cell); if (!inserted) { // We've failed to insert since we already have an equivalent cell From ef22c6ee735ee22f50a1bd6c6430c618cc8afc51 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 24 Sep 2025 00:22:58 +0000 Subject: [PATCH 166/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 02f8fa0e9..406a6d196 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+178 +YOSYS_VER := 0.57+198 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 6de21a8999bb44e3b845a0aafeca3e672408577b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= Date: Wed, 24 Sep 2025 11:07:26 +0200 Subject: [PATCH 167/188] CONTRIBUTING: prefer Discourse over GitHub Discussions --- CONTRIBUTING.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 6e7b8f221..403292b0b 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -60,8 +60,8 @@ merge; please do not use these labels if you are not a maintainer. # Asking questions -If you have a question about how to use Yosys, please ask on our [discussions -page](https://github.com/YosysHQ/yosys/discussions) or in our [Discourse forum](https://yosyshq.discourse.group/). +If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/) or in our [discussions +page](https://github.com/YosysHQ/yosys/discussions). The Discourse is also a great place to ask questions about developing or contributing to Yosys. From 904d49c6d818897bb4c854e64c6c395861146e0d Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:38:15 +0200 Subject: [PATCH 168/188] abc9_ops: Remove temporary debug log message I missed this when adding the -replace_zbufs option. --- passes/techmap/abc9_ops.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index ecba519bf..2e762d7b9 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1600,7 +1600,6 @@ static void replace_zbufs(Design *design) sig[i] = w; } } - log("XXX %s -> %s\n", log_signal(cell->getPort(ID::A)), log_signal(sig)); cell->setPort(ID::A, sig); } From 71882debe78cda10a963b89404ac4decbedca8f2 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 24 Sep 2025 13:15:36 +0200 Subject: [PATCH 169/188] simplemap: Remove leftover debug output --- passes/techmap/simplemap.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 86ff5c149..938ed5355 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -18,7 +18,6 @@ */ #include "simplemap.h" -#include "backends/rtlil/rtlil_backend.h" #include "kernel/sigtools.h" #include "kernel/ff.h" #include @@ -156,14 +155,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - log("huh\n"); - RTLIL_BACKEND::dump_cell(std::cout, "", cell); transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); last_output_cell = gate; - RTLIL_BACKEND::dump_cell(std::cout, "", gate); } sig_a = sig_t; From 86a46b9e5c122a4f6463390e8e9bbac8f48f4bea Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:19:30 +0200 Subject: [PATCH 170/188] log: Flush stdout before printing a fatal error to stderr This hasn't been an issue when using -l to redirect or when stdout is line buffered, explaining how we didn't notice this earlier, but for `yosys ... > log` that extra flush is required to ensure all messages preceding the fatal error are flushed. --- kernel/log.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/log.cc b/kernel/log.cc index 0085980b1..af083860a 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -331,10 +331,12 @@ static void log_error_with_prefix(std::string_view prefix, std::string str) if (log_errfile != NULL) log_files.push_back(log_errfile); - if (log_error_stderr) + if (log_error_stderr) { + log_flush(); // Make sure we flush stdout before replacing it with stderr for (auto &f : log_files) if (f == stdout) f = stderr; + } log_last_error = std::move(str); log("%s%s", prefix, log_last_error); From 2dce50516b218b28a34b838810709fa0ee24d256 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:26:53 +0200 Subject: [PATCH 171/188] log: Print static message as fatal error for YOSYS_ABORT --- kernel/log.cc | 5 +++++ kernel/yosys_common.h | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/kernel/log.cc b/kernel/log.cc index af083860a..34e56f8ac 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -407,6 +407,11 @@ void log_abort_internal(const char *file, int line) log_error("Abort in %s:%d.\n", file, line); } +void log_yosys_abort_message(std::string_view file, int line, std::string_view func, std::string_view message) +{ + log_error("Abort in %s:%d (%s): %s\n", file, line, func, message); +} + void log_formatted_cmd_error(std::string str) { if (log_cmd_error_throw) { diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index fd84dd74e..d69e02a59 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -142,7 +142,12 @@ #define YOSYS_CONSTEVAL constexpr #endif -#define YOSYS_ABORT(s) abort() +#define YOSYS_ABORT(s) YOSYS_NAMESPACE_PREFIX log_yosys_abort_message(__FILE__, __LINE__, __FUNCTION__, s) + +// This has to precede including "kernel/io.h" +YOSYS_NAMESPACE_BEGIN +[[noreturn]] void log_yosys_abort_message(std::string_view file, int line, std::string_view func, std::string_view message); +YOSYS_NAMESPACE_END #include "kernel/io.h" From 83dd99efb7971d212b3538bf05d92140393aed7d Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 24 Sep 2025 18:47:54 +0200 Subject: [PATCH 172/188] verific: New `-sva-continue-on-error` import option This option allows you to process a design that includes unsupported SVA. Unsupported SVA gets imported as formal cells using 'x inputs and with the `unsupported_sva` attribute set. This allows you to get a complete list of defined properties or to check only a supported subset of properties. To ensure no properties are unintentionally skipped for actual verification, even in cases where `-sva-continue-on-error` is used by default to read and inspect a design, `hierarchy -simcheck` and `hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva` property cells remain in the design. --- frontends/verific/verific.cc | 26 ++++++++++--- frontends/verific/verific.h | 6 ++- frontends/verific/verificsva.cc | 51 ++++++++++++++++--------- passes/hierarchy/hierarchy.cc | 19 +++++++++ tests/verific/sva_continue_on_err.ys | 38 ++++++++++++++++++ tests/verific/sva_no_continue_on_err.ys | 9 +++++ 6 files changed, 124 insertions(+), 25 deletions(-) create mode 100644 tests/verific/sva_continue_on_err.ys create mode 100644 tests/verific/sva_no_continue_on_err.ys diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 279b0dd52..b2b85641f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -200,8 +200,8 @@ YosysStreamCallBackHandler verific_read_cb; // ================================================================== -VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) : - mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva), +VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_sva_continue, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit) : + mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva), mode_sva_continue(mode_sva_continue), mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover), mode_fullinit(mode_fullinit) { @@ -2316,6 +2316,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->attributes.erase(ID::init); } } + + if (num_sva_continue) { + log_warning("Encountered %d items containing unsupported SVA!\n", num_sva_continue); + log_warning("Unsupported SVA imported as 'x and marked using the `unsupported_sva' attribute due to -sva-continue-on-err.\n"); + } + num_sva_continue = 0; } // ================================================================== @@ -3051,7 +3057,7 @@ std::string verific_import(Design *design, const std::mapsecond; if (nl_done.count(it->first) == 0) { - VerificImporter importer(false, false, false, false, false, false, false); + VerificImporter importer(false, false, false, false, false, false, false, false); nl_done[it->first] = it->second; importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName())); } @@ -3288,6 +3294,11 @@ struct VerificPass : public Pass { log(" -nosva\n"); log(" Ignore SVA properties, do not infer checker logic.\n"); log("\n"); + log(" -sva-continue-on-err\n"); + log(" Turns unsupported SVA from an error into a warning. Properties are imported\n"); + log(" with their trigger condition replaced with 'x and with an `unsupported_sva'\n"); + log(" attribute to produce a later error in SBY if they remain in the design.\n"); + log("\n"); log(" -L \n"); log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n"); log("\n"); @@ -4033,7 +4044,8 @@ struct VerificPass : public Pass { { std::map nl_todo, nl_done; bool mode_all = false, mode_gates = false, mode_keep = false; - bool mode_nosva = false, mode_names = false, mode_verific = false; + bool mode_nosva = false, mode_sva_continue = false; + bool mode_names = false, mode_verific = false; bool mode_autocover = false, mode_fullinit = false; bool flatten = false, extnets = false, mode_cells = false; bool split_complex_ports = true; @@ -4071,6 +4083,10 @@ struct VerificPass : public Pass { mode_nosva = true; continue; } + if (args[argidx] == "-sva-continue-on-err") { + mode_sva_continue = true; + continue; + } if (args[argidx] == "-L" && argidx+1 < GetSize(args)) { verific_sva_fsm_limit = atoi(args[++argidx].c_str()); continue; @@ -4201,7 +4217,7 @@ struct VerificPass : public Pass { auto it = nl_todo.begin(); Netlist *nl = it->second; if (nl_done.count(it->first) == 0) { - VerificImporter importer(mode_gates, mode_keep, mode_nosva, + VerificImporter importer(mode_gates, mode_keep, mode_nosva, mode_sva_continue, mode_names, mode_verific, mode_autocover, mode_fullinit); nl_done[it->first] = it->second; importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName())); diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 4e9c7a305..f33a380f7 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -73,10 +73,12 @@ struct VerificImporter std::map sva_posedge_map; pool any_all_nets; - bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific; + bool mode_gates, mode_keep, mode_nosva, mode_sva_continue, mode_names, mode_verific; bool mode_autocover, mode_fullinit; - VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit); + int num_sva_continue = 0; + + VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_sva_continue, bool mode_names, bool mode_verific, bool mode_autocover, bool mode_fullinit); RTLIL::SigBit net_map_at(Verific::Net *net); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 3908947eb..9757f07f2 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1023,7 +1023,7 @@ struct VerificSvaImporter [[noreturn]] void parser_error(std::string errmsg) { - if (!importer->mode_keep) + if (!importer->mode_keep && !importer->mode_sva_continue) log_error("%s", errmsg); log_warning("%s", errmsg); throw ParserErrorException(); @@ -1710,30 +1710,30 @@ struct VerificSvaImporter void import() { - try - { - module = importer->module; - netlist = root->Owner(); + module = importer->module; + netlist = root->Owner(); - if (verific_verbose) - log(" importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(), - LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile())); + if (verific_verbose) + log(" importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(), + LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile())); - bool is_user_declared = root->IsUserDeclared(); + bool is_user_declared = root->IsUserDeclared(); - // FIXME - if (!is_user_declared) { - const char *name = root->Name(); - for (int i = 0; name[i]; i++) { - if (i ? (name[i] < '0' || name[i] > '9') : (name[i] != 'i')) { - is_user_declared = true; - break; - } + // FIXME + if (!is_user_declared) { + const char *name = root->Name(); + for (int i = 0; name[i]; i++) { + if (i ? (name[i] < '0' || name[i] > '9') : (name[i] != 'i')) { + is_user_declared = true; + break; } } + } - RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID); + RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID); + try + { // parse SVA sequence into trigger signal clocking = VerificClocking(importer, root->GetInput(), true); @@ -1836,6 +1836,21 @@ struct VerificSvaImporter } catch (ParserErrorException) { + if (importer->mode_sva_continue) { + + RTLIL::Cell *c = nullptr; + + if (mode_assert) c = module->addAssert(root_name, State::Sx, State::Sx); + if (mode_assume) c = module->addAssume(root_name, State::Sx, State::Sx); + if (mode_cover) c = module->addCover(root_name, State::Sx, State::Sx); + + if (c) { + importer->import_attributes(c->attributes, root); + c->set_bool_attribute(ID(unsupported_sva)); + } + + importer->num_sva_continue++; + } } } }; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a7f86c3f0..b3edcef94 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1149,6 +1149,25 @@ struct HierarchyPass : public Pass { } } + if (flag_simcheck || flag_smtcheck) { + for (auto mod : design->modules()) { + for (auto cell : mod->cells()) { + if (!cell->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) + continue; + if (!cell->has_attribute(ID(unsupported_sva))) + continue; + + auto src = cell->get_src_attribute(); + + if (!src.empty()) + src += ": "; + + log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `delete */a:unsupported_sva' to ignore.\n", + src, log_id(cell->name), log_id(mod->name)); + } + } + } + if (!keep_positionals) { std::set pos_mods; diff --git a/tests/verific/sva_continue_on_err.ys b/tests/verific/sva_continue_on_err.ys new file mode 100644 index 000000000..4cd603f74 --- /dev/null +++ b/tests/verific/sva_continue_on_err.ys @@ -0,0 +1,38 @@ +verific -sv < b); + prop_unsupported1: assert property (@(posedge clk) a ##1 b #=# b); + prop_unsupported2: assert property (@(posedge clk) a ##1 @(posedge b) ##1 a); + + sequence local_var_seq; + logic v; + (1, v = a) ##1 b ##1 (v == a); + endsequence + + prop_unsupported3: assert property (@(posedge clk) local_var_seq); + +endmodule +EOF + +logger -expect warning "Mixed clocking is currently not supported" 1 +logger -expect warning "Verific SVA primitive sva_non_overlapped_followed_by .* is currently unsupported in this context" 1 +logger -expect warning "SVA sequences with local variable assignments are currently not supported" 1 +logger -expect warning "Encountered 3 items containing unsupported SVA" 1 +verific -import -sva-continue-on-err top +logger -check-expected + +select -assert-count 4 top/t:$assert +select -assert-count 4 top/a:unsupported_sva top/prop_supported %% top/t:$assert %i + +select -assert-count 3 top/a:unsupported_sva +select -assert-count 3 top/a:unsupported_sva top/prop_unsupported* %i +select -assert-count 1 top/a:unsupported_sva top/prop_unsupported1 %i +select -assert-count 1 top/a:unsupported_sva top/prop_unsupported2 %i +select -assert-count 1 top/a:unsupported_sva top/prop_unsupported3 %i +select -assert-count 0 top/a:unsupported_sva top/prop_supported %i +select -assert-count 1 top/prop_supported + +logger -expect error "uses unsupported SVA constructs." 1 +hierarchy -smtcheck -top top +logger -check-expected diff --git a/tests/verific/sva_no_continue_on_err.ys b/tests/verific/sva_no_continue_on_err.ys new file mode 100644 index 000000000..5a0a59a81 --- /dev/null +++ b/tests/verific/sva_no_continue_on_err.ys @@ -0,0 +1,9 @@ + +verific -sv < Date: Thu, 25 Sep 2025 00:22:44 +0000 Subject: [PATCH 173/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 406a6d196..45b3a09f3 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+198 +YOSYS_VER := 0.57+212 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 1c73011e7e8236c88157d37bd22a456b47c459d1 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 25 Sep 2025 03:04:17 +0000 Subject: [PATCH 174/188] Swap SigSpecs using std::swap with moves --- kernel/rtlil.h | 6 +++++- passes/opt/opt_merge.cc | 9 +++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 88594859a..e240cf885 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1244,7 +1244,8 @@ private: public: SigSpec() : width_(0), hash_(0) {} SigSpec(std::initializer_list parts); - + SigSpec(const SigSpec &) = default; + SigSpec(SigSpec &&) = default; SigSpec(const RTLIL::Const &value); SigSpec(RTLIL::Const &&value); SigSpec(const RTLIL::SigChunk &chunk); @@ -1261,6 +1262,9 @@ public: SigSpec(const std::set &bits); explicit SigSpec(bool bit); + SigSpec &operator=(const SigSpec &rhs) = default; + SigSpec &operator=(SigSpec &&rhs) = default; + inline const std::vector &chunks() const { pack(); return chunks_; } inline const std::vector &bits() const { inline_unpack(); return bits_; } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 541459c27..e1c3f0269 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -25,6 +25,7 @@ #include "libs/sha1/sha1.h" #include #include +#include #include #include #include @@ -173,14 +174,10 @@ struct OptMergeWorker if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) || cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) { if (conn1.at(ID::A) < conn1.at(ID::B)) { - RTLIL::SigSpec tmp = conn1[ID::A]; - conn1[ID::A] = conn1[ID::B]; - conn1[ID::B] = tmp; + std::swap(conn1[ID::A], conn1[ID::B]); } if (conn2.at(ID::A) < conn2.at(ID::B)) { - RTLIL::SigSpec tmp = conn2[ID::A]; - conn2[ID::A] = conn2[ID::B]; - conn2[ID::B] = tmp; + std::swap(conn2[ID::A], conn2[ID::B]); } } else if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) { From 4d209c187d02cb858701a1b4777d73c90cb80592 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Wed, 17 Sep 2025 02:52:30 +0000 Subject: [PATCH 175/188] Switch OptMergeWorker cell type switching to use IdString::in() --- passes/opt/opt_merge.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index e1c3f0269..13b1cb293 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -171,8 +171,8 @@ struct OptMergeWorker } } - if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) || - cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) { + if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), + ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) { if (conn1.at(ID::A) < conn1.at(ID::B)) { std::swap(conn1[ID::A], conn1[ID::B]); } @@ -180,11 +180,11 @@ struct OptMergeWorker std::swap(conn2[ID::A], conn2[ID::B]); } } else - if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) { + if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) { conn1[ID::A].sort(); conn2[ID::A].sort(); } else - if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) { + if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) { conn1[ID::A].sort_and_unify(); conn2[ID::A].sort_and_unify(); } else From fef6bdae6cda277a022381c2f325ba374a94f377 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 26 Sep 2025 11:05:50 +1200 Subject: [PATCH 176/188] autoname.cc: Return number of renames Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects. Check counts in `tests/various/autoname.ys`. --- passes/cmds/autoname.cc | 5 ++++- tests/various/autoname.ys | 6 ++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index d2ff568c3..1ad2eab3c 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -81,6 +81,7 @@ int autoname_worker(Module *module, const dict& wire_score) } } + int count = 0; // compare against double best score for following comparisons so we don't // pre-empt a future iteration best_name.score *= 2; @@ -91,6 +92,7 @@ int autoname_worker(Module *module, const dict& wire_score) IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); + count++; } for (auto &it : proposed_wire_names) { @@ -99,9 +101,10 @@ int autoname_worker(Module *module, const dict& wire_score) IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); + count++; } - return proposed_cell_names.size() + proposed_wire_names.size(); + return count; } struct AutonamePass : public Pass { diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index 29ca81bbe..fccecb1c2 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -18,6 +18,7 @@ module \top end EOT logger -expect log "Rename cell .name in top to y_.and_Y" 1 +logger -expect log "Renamed 1 objects" 1 debug autoname logger -check-expected @@ -42,6 +43,7 @@ module \top end EOT logger -expect log "Rename cell .name in top to ab_.or_A" 1 +logger -expect log "Renamed 1 objects" 1 debug autoname logger -check-expected @@ -78,6 +80,7 @@ end EOT logger -expect log "Rename cell .name in top to bcd_.and_B" 1 logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname logger -check-expected @@ -113,6 +116,7 @@ end EOT logger -expect log "Rename cell .name in top to y_.and_Y" 1 logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname logger -check-expected @@ -174,6 +178,7 @@ EOT # wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname t:$or logger -check-expected @@ -186,5 +191,6 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 # $c gets shortest name, since the cell driving it doesn't have known port # directions logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 +logger -expect log "Renamed 4 objects" 1 debug autoname logger -check-expected From 941ba3b7454a2f2ccaf8fdf70489e5c3f4136195 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 26 Sep 2025 11:27:17 +1200 Subject: [PATCH 177/188] autoname.ys: Extra check for rename order Disabling comparison with best score will cause this check to fail. Preferred names will not be possible if $name2 has not yet been renamed. --- tests/various/autoname.ys | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index fccecb1c2..7df1571b2 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -175,6 +175,8 @@ module \top end end EOT +design -save order_test + # wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 @@ -186,11 +188,18 @@ logger -check-expected logger -expect log "Rename cell .name in top to a_.__unknown_A" 1 # another output wire logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1 -# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) -logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 -# $c gets shortest name, since the cell driving it doesn't have known port -# directions -logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 logger -expect log "Renamed 4 objects" 1 debug autoname logger -check-expected + +# don't rename prematurely (some objects should be named after $name2) +design -load order_test + +# $c gets shortest name, since the cell driving it doesn't have known port +# directions (otherwise a_$__unknown_A_Y) +logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 +# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) +logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 +logger -expect log "Renamed 6 objects" 1 +debug autoname +logger -check-expected From 6a5d9567472363019065410d05f47bc6169c8598 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 26 Sep 2025 00:22:24 +0000 Subject: [PATCH 178/188] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 45b3a09f3..7a2e8419b 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.57+212 +YOSYS_VER := 0.57+218 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From ce5d04a42f865bc45612260d16ec994f20b626ad Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 26 Sep 2025 18:39:32 +0200 Subject: [PATCH 179/188] hierarchy: Suggest more specific command to skip unsupported SVA --- passes/hierarchy/hierarchy.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index b3edcef94..ea68add18 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1162,7 +1162,7 @@ struct HierarchyPass : public Pass { if (!src.empty()) src += ": "; - log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `delete */a:unsupported_sva' to ignore.\n", + log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `chformal -remove a:unsupported_sva' to ignore.\n", src, log_id(cell->name), log_id(mod->name)); } } From 4bb4b6c66288b463bd551068a89eded3fc2ae264 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 26 Sep 2025 18:42:00 +0200 Subject: [PATCH 180/188] verific: Extend -sva-continue-on-err to handle FSM explosion This also rolls back any added cells and wires, since we might have added a lot of helper logic by the point we detect this. --- frontends/verific/verificsva.cc | 34 +++++++++++++++++-- .../verific/sva_continue_on_err_explosion.ys | 31 +++++++++++++++++ 2 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 tests/verific/sva_continue_on_err_explosion.ys diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 9757f07f2..50e0049ae 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -124,6 +124,7 @@ struct SvaFsm { Module *module; VerificClocking clocking; + std::function parser_error; SigBit trigger_sig = State::S1, disable_sig; SigBit throughout_sig = State::S1; @@ -148,6 +149,7 @@ struct SvaFsm module = clking.module; clocking = clking; trigger_sig = trig; + parser_error = [](std::string msg){ log_error("%s", msg); }; startNode = createNode(); acceptNode = createNode(); @@ -475,8 +477,8 @@ struct SvaFsm dump(); log(" ctrl signal: %s\n", log_signal(dnode.ctrl)); } - log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n", - GetSize(dnode.ctrl), verific_sva_fsm_limit); + parser_error(stringf("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n", + GetSize(dnode.ctrl), verific_sva_fsm_limit)); } for (unsigned long long i = 0; i < (1ull << GetSize(dnode.ctrl)); i++) @@ -1260,6 +1262,7 @@ struct VerificSvaImporter if (inst->Type() == PRIM_SVA_FIRST_MATCH) { SvaFsm match_fsm(clocking); + match_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; match_fsm.createLink(parse_sequence(match_fsm, match_fsm.createStartNode(), inst->GetInput()), match_fsm.acceptNode); int node = fsm.createNode(); @@ -1426,12 +1429,15 @@ struct VerificSvaImporter if (inst->Type() == PRIM_SVA_SEQ_AND || inst->Type() == PRIM_SVA_AND) { SvaFsm fsm1(clocking); + fsm1.parser_error = [&](std::string msg) { this->parser_error(msg); }; fsm1.createLink(parse_sequence(fsm1, fsm1.createStartNode(), inst->GetInput1()), fsm1.acceptNode); SvaFsm fsm2(clocking); + fsm2.parser_error = [&](std::string msg) { this->parser_error(msg); }; fsm2.createLink(parse_sequence(fsm2, fsm2.createStartNode(), inst->GetInput2()), fsm2.acceptNode); SvaFsm combined_fsm(clocking); + combined_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; fsm1.getDFsm(combined_fsm, combined_fsm.createStartNode(), -1, combined_fsm.acceptNode); fsm2.getDFsm(combined_fsm, combined_fsm.createStartNode(), -1, combined_fsm.acceptNode); @@ -1456,6 +1462,7 @@ struct VerificSvaImporter if (inst->Type() == PRIM_SVA_INTERSECT || inst->Type() == PRIM_SVA_WITHIN) { SvaFsm intersect_fsm(clocking); + intersect_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; if (inst->Type() == PRIM_SVA_INTERSECT) { @@ -1562,6 +1569,7 @@ struct VerificSvaImporter int node; SvaFsm antecedent_fsm(clocking, trig); + antecedent_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) { int next_node = antecedent_fsm.createNode(); @@ -1623,6 +1631,7 @@ struct VerificSvaImporter int node; SvaFsm antecedent_fsm(clocking, trig); + antecedent_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY) { int next_node = antecedent_fsm.createNode(); @@ -1677,6 +1686,7 @@ struct VerificSvaImporter } SvaFsm consequent_fsm(clocking, antecedent_match); + consequent_fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; node = parse_sequence(consequent_fsm, consequent_fsm.createStartNode(), consequent_net); consequent_fsm.createLink(node, consequent_fsm.acceptNode); @@ -1696,6 +1706,7 @@ struct VerificSvaImporter } SvaFsm fsm(clocking, trig); + fsm.parser_error = [&](std::string msg) { this->parser_error(msg); }; int node = parse_sequence(fsm, fsm.createStartNode(), net); fsm.createLink(node, fsm.acceptNode); @@ -1713,6 +1724,10 @@ struct VerificSvaImporter module = importer->module; netlist = root->Owner(); + int initial_cell_count = GetSize(module->cells_); + int initial_wire_count = GetSize(module->wires_); + int initial_connection_count = GetSize(module->connections_); + if (verific_verbose) log(" importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(), LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile())); @@ -1838,6 +1853,21 @@ struct VerificSvaImporter { if (importer->mode_sva_continue) { + std::vector remove_cells; + pool remove_wires; + + for (int i = 0, end = GetSize(module->cells_) - initial_cell_count; i != end; ++i) + remove_cells.push_back(module->cells_.element(i)->second); + + for (int i = 0, end = GetSize(module->wires_) - initial_wire_count; i != end; ++i) + remove_wires.emplace(module->wires_.element(i)->second); + + for (auto cell : remove_cells) + module->remove(cell); + module->remove(remove_wires); + + module->connections_.resize(initial_connection_count); + RTLIL::Cell *c = nullptr; if (mode_assert) c = module->addAssert(root_name, State::Sx, State::Sx); diff --git a/tests/verific/sva_continue_on_err_explosion.ys b/tests/verific/sva_continue_on_err_explosion.ys new file mode 100644 index 000000000..c96ad0140 --- /dev/null +++ b/tests/verific/sva_continue_on_err_explosion.ys @@ -0,0 +1,31 @@ +verific -sv < b); + + prop_exploding: assert property (@(posedge clk) + ((a [*7] ##1 b) [*11]) and + ((a [*11] ##1 b) [*7]) and + ((a [*13] ##1 b) [*5]) and + ((a [*5] ##1 b) [*13]) + ); + + prop_supported2: assert property (@(posedge clk) a [*5] ##1 b |=> b); + +endmodule +EOF + +logger -expect warning "Stopping to prevent exponential design size explosion." 1 +verific -import -sva-continue-on-err top +logger -check-expected + +select -assert-count 3 top/t:$assert +select -assert-count 1 top/a:unsupported_sva top/prop_exploding %% top/t:$assert %i + +select -assert-count 0 top/a:unsupported_sva top/prop_supported1 %i +select -assert-count 0 top/a:unsupported_sva top/prop_supported2 %i +select -assert-count 2 top/prop_supported* + +logger -expect error "uses unsupported SVA constructs." 1 +hierarchy -smtcheck -top top +logger -check-expected From 4b6b254e314cf0bd1191706900a2358e8503e2db Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 28 Sep 2025 01:37:30 -0700 Subject: [PATCH 181/188] pyosys cannot parse header with omitted function args --- kernel/rtlil.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e240cf885..5271a3111 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1244,8 +1244,8 @@ private: public: SigSpec() : width_(0), hash_(0) {} SigSpec(std::initializer_list parts); - SigSpec(const SigSpec &) = default; - SigSpec(SigSpec &&) = default; + SigSpec(const SigSpec &value) = default; + SigSpec(SigSpec &&value) = default; SigSpec(const RTLIL::Const &value); SigSpec(RTLIL::Const &&value); SigSpec(const RTLIL::SigChunk &chunk); From 9396e5e5fe40f90e44498597ae4df4cc391561e1 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:40:22 +0200 Subject: [PATCH 182/188] portarcs: Ignore all bufnorm helper cells The `portarcs` pass was already ignoring `$buf` cells when loading timing data, but now bufnorm will also emit `$input_port` and `$connect` helper cells, which need to be ignored as well. --- passes/cmds/portarcs.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 36870489a..8cc5d1236 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -124,7 +124,8 @@ struct PortarcsPass : Pass { TopoSort sort; for (auto cell : m->cells()) - if (cell->type != ID($buf)) { + // Ignore all bufnorm helper cells + if (!cell->type.in(ID($buf), ID($input_port), ID($connect))) { auto tdata = tinfo.find(cell->type); if (tdata == tinfo.end()) log_cmd_error("Missing timing data for module '%s'.\n", log_id(cell->type)); From 90669ab4eba25878ee592b80bc4ba5f79386b81c Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:44:13 +0200 Subject: [PATCH 183/188] aiger2: Only fail for reachable undirected bufnorm helper cells The aiger2 backend checks for unsupported cells during indexing. This causes it to fail when `$connect` or `$tribuf` (as workaround for missing 'z-$buf support) cells are present in the module. Since bufnorm adds these cells automatically, it is very easy to end up with them due to unconnected wires or e.g. `$specify` cells, which do not pose an actual problem for the backend, since it will never encounter those during a traversal. With this, we ignore them during indexing and only produce an actual error message if we reach such a cell during the traversal. --- backends/aiger2/aiger.cc | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index b63e51bde..41e1b91c1 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -105,6 +105,13 @@ struct Index { if (allow_blackboxes) { info.found_blackboxes.insert(cell); } else { + // Even if we don't allow blackboxes these might still be + // present outside of any traversed input cones, so we + // can't bail at this point. If they are hit by a traversal + // (which can only really happen with $tribuf not + // $connect), we can still detect this as an error later. + if (cell->type == ID($connect) || (cell->type == ID($tribuf) && cell->has_attribute(ID(aiger2_zbuf)))) + continue; if (!submodule || submodule->get_blackbox_attribute()) log_error("Unsupported cell type: %s (%s in %s)\n", log_id(cell->type), log_id(cell), log_id(m)); @@ -483,7 +490,8 @@ struct Index { { Design *design = index.design; auto &minfo = leaf_minfo(index); - log_assert(minfo.suboffsets.count(cell)); + if (!minfo.suboffsets.count(cell)) + log_error("Reached unsupport cell %s (%s in %s)\n", log_id(cell->type), log_id(cell), log_id(cell->module)); Module *def = design->module(cell->type); log_assert(def); levels.push_back(Level(index.modules.at(def), cell)); From cbc1055517b6936de34332c480da9e7a9aae658f Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 21:54:55 +0200 Subject: [PATCH 184/188] opt_clean: Fix debug output when cleaning up bufnorm cells --- passes/opt/opt_clean.cc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index dc3f015cd..996a9b3c9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -635,9 +635,17 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool } } for (auto cell : delcells) { - if (verbose) - log_debug(" removing buffer cell `%s': %s = %s\n", cell->name, - log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A))); + if (verbose) { + if (cell->type == ID($connect)) + log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name, + log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B))); + else if (cell->type == ID($input_port)) + log_debug(" removing input port marker cell `%s': %s\n", cell->name, + log_signal(cell->getPort(ID::Y))); + else + log_debug(" removing buffer cell `%s': %s = %s\n", cell->name, + log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A))); + } module->remove(cell); } if (!delcells.empty()) From 86fb2f16f7863634e1df9e692520656fa55a36a7 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 23 Sep 2025 14:28:10 +0200 Subject: [PATCH 185/188] bufnorm: Refactor and fix incremental bufNormalize This fixes some edge cases the previous version didn't handle properly by simplifying the logic of determining directly driven wires and representatives to use as buffer inputs. --- kernel/rtlil.cc | 7 + kernel/rtlil_bufnorm.cc | 224 ++++++++++++++--------------- tests/various/bufnorm_opt_clean.ys | 154 ++++++++++++++++++++ 3 files changed, 270 insertions(+), 115 deletions(-) create mode 100644 tests/various/bufnorm_opt_clean.ys diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index e9d051de8..8daf2c821 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2829,6 +2829,13 @@ void RTLIL::Module::remove(const pool &wires) delete_wire_worker.wires_p = &wires; rewrite_sigspecs2(delete_wire_worker); + if (design->flagBufferedNormalized) { + for (auto wire : wires) { + buf_norm_wire_queue.erase(wire); + buf_norm_connect_index.erase(wire); + } + } + for (auto &it : wires) { log_assert(wires_.count(it->name) != 0); wires_.erase(it->name); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index 6d619d9e6..d0561f880 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -43,6 +43,7 @@ void RTLIL::Design::bufNormalize(bool enable) wire->driverCell_ = nullptr; wire->driverPort_ = IdString(); } + module->buf_norm_connect_index.clear(); } flagBufferedNormalized = false; @@ -126,15 +127,19 @@ void RTLIL::Module::bufNormalize() idict wire_queue_entries; // Ordered queue of wires to process int wire_queue_pos = 0; // Index up to which we processed the wires - // Wires with their unique driving cell port. If we know a wire is - // driven by multiple (potential) drivers, this is indicated by a - // nullptr as cell. + // Wires with their unique driving cell port. We pick the first driver + // we encounter, with the exception that we ensure that a module input + // port can only get $input_port drivers and that $input_port drivers + // cannot drive any other modules. If we reject an $input_port driver + // because it's not driving an input port or because there already is + // another $input_port driver for the same port, we also delete that + // $input_port cell. dict> direct_driven_wires; - // Set of non-unique or driving cell ports for each processed wire. - dict>> direct_driven_wires_conflicts; - - // Set of cell ports that need a fresh intermediate wire. + // Set of cell ports that need a fresh intermediate wire. These are all + // cell ports that drive non-full-wire sigspecs, cell ports driving + // module input ports, and cell ports driving wires that are already + // driven. pool> pending_ports; // This helper will be called for every output/inout cell port that is @@ -149,27 +154,14 @@ void RTLIL::Module::bufNormalize() SigSpec const &sig = cell->getPort(port); - if (cell->type == ID($input_port)) { - // If an `$input_port` cell isn't fully connected to a full - // input port wire, we remove it since the wires are still the - // canonical source of module ports and the `$input_port` cells - // are just helpers to simplfiy the bufnorm invariant. - log_assert(port == ID::Y); - if (!sig.is_wire()) { - buf_norm_cell_queue.insert(cell); - remove(cell); - return; - } - Wire *w = sig.as_wire(); - if (!w->port_input || w->port_output) { - buf_norm_cell_queue.insert(cell); - remove(cell); - return; - } - w->driverCell_ = cell; - w->driverPort_ = ID::Y; - } else if (cell->type == ID($buf) && cell->attributes.empty() && !cell->name.isPublic()) { + // Make sure all wires of the cell port are enqueued, ensuring we + // detect other connected drivers (output and inout). + for (auto chunk : sig.chunks()) + if (chunk.is_wire()) + wire_queue_entries(chunk.wire); + + if (cell->type == ID($buf) && cell->attributes.empty() && !cell->name.isPublic()) { // For a plain `$buf` cell, we enqueue all wires on its input // side, bypass it using module level connections (skipping 'z // bits) and then remove the cell. Eventually the module level @@ -206,47 +198,40 @@ void RTLIL::Module::bufNormalize() if (!sig_y.empty()) connect(sig_y, sig_a); + remove(cell); + log_assert(GetSize(buf_norm_wire_queue) <= 1); + buf_norm_wire_queue.clear(); + return; + } else if (cell->type == ID($input_port)) { + log_assert(port == ID::Y); + if (sig.is_wire()) { + Wire *w = sig.as_wire(); + if (w->port_input && !w->port_output) { + // An $input_port cell can only drive a full wire module input port + auto [found, inserted] = direct_driven_wires.emplace(w, {cell, port}); + if (!inserted || (found->second.first == cell && found->second.second == port)) + return; + } + } + + // If an `$input_port` cell isn't driving a full + // input port wire, we remove it since the wires are still the + // canonical source of module ports + buf_norm_cell_queue.insert(cell); remove(cell); + log_assert(GetSize(buf_norm_wire_queue) <= 1); + buf_norm_wire_queue.clear(); return; } - // Make sure all wires of the cell port are enqueued, ensuring we - // detect other connected drivers (output and inout). - for (auto const &chunk : sig.chunks()) - if (chunk.wire) - wire_queue_entries(chunk.wire); - if (sig.is_wire()) { - // If the full cell port is connected to a full wire, we might be - // able to keep that connection if this is a unique output port driving that wire Wire *w = sig.as_wire(); - - // We try to store the current port as unique driver, if this - // succeeds we're done with the port. - auto [found, inserted] = direct_driven_wires.emplace(w, {cell, port}); - if (inserted || (found->second.first == cell && found->second.second == port)) - return; - - // When this failed, we store this port as a conflict. If we - // had already stored a candidate for a unique driver, we also - // move it to the conflicts, leaving a nullptr marker. - - auto &conflicts = direct_driven_wires_conflicts[w]; - if (Cell *other_cell = found->second.first) { - if (other_cell->type == ID($input_port)) { - // Multiple input port cells - log_assert(cell->type != ID($input_port)); - } else { - pending_ports.insert(found->second); - conflicts.emplace(found->second); - found->second = {nullptr, {}}; - } - } - if (cell->type == ID($input_port)) { - found->second = {cell, port}; - } else { - conflicts.emplace(cell, port); + if (!w->port_input || w->port_output) { + // If the full cell port is connected to a full non-input-port wire, pick it as driver + auto [found, inserted] = direct_driven_wires.emplace(w, {cell, port}); + if (inserted || (found->second.first == cell && found->second.second == port)) + return; } } @@ -256,16 +241,22 @@ void RTLIL::Module::bufNormalize() pending_ports.emplace(cell, port); }; + // We enqueue all enqueued wires for `$buf`/`$connect` processing (clearing the module level queue). + for (auto wire : buf_norm_wire_queue) + wire_queue_entries(wire); + buf_norm_wire_queue.clear(); + + // Only after clearing the `buf_norm_wire_queue` are we allowed to call + // enqueue_cell_port, since we're using assertions to check against + // unintended wires being enqueued into `buf_norm_wire_queue` that + // would prevent us from restoring the bufnorm invariants in a single + // pass. + // We process all explicitly enqueued cell ports (clearing the module level queue). for (auto const &[cell, port_name] : buf_norm_cell_port_queue) enqueue_cell_port(cell, port_name); buf_norm_cell_port_queue.clear(); - // And enqueue all wires for `$buf`/`$connect` processing (clearing the module level queue). - for (auto wire : buf_norm_wire_queue) - wire_queue_entries(wire); - buf_norm_wire_queue.clear(); - // We also enqueue all wires that saw newly added module level connections. for (auto &[a, b] : connections_) for (auto &sig : {a, b}) @@ -302,8 +293,11 @@ void RTLIL::Module::bufNormalize() if (chunk.wire) wire_queue_entries(chunk.wire); connect(sig_a, sig_b); + buf_norm_cell_queue.insert(connect_cell); remove(connect_cell); + log_assert(GetSize(buf_norm_wire_queue) <= 2); + buf_norm_wire_queue.clear(); } } } @@ -315,6 +309,9 @@ void RTLIL::Module::bufNormalize() // As a first step for re-normalization we add all require intermediate // wires for cell output and inout ports. for (auto &[cell, port] : pending_ports) { + log_assert(cell->type != ID($input_port)); + log_assert(!cell->type.empty()); + log_assert(!pending_deleted_cells.count(cell)); SigSpec const &sig = cell->getPort(port); Wire *w = addWire(NEW_ID, GetSize(sig)); @@ -323,16 +320,9 @@ void RTLIL::Module::bufNormalize() // correspond to what you would get if the intermediate wires had // been in place from the beginning. connect(sig, w); - auto port_dir = cell->port_dir(port); - if (port_dir == RTLIL::PD_INOUT || port_dir == RTLIL::PD_UNKNOWN) { - direct_driven_wires.emplace(w, {nullptr, {}}); - direct_driven_wires_conflicts[w].emplace(cell, port); - } else { - direct_driven_wires.emplace(w, {cell, port}); - } - - cell->setPort(port, w); - wire_queue_entries(w); + direct_driven_wires.emplace(w, {cell, port}); + cell->setPort(port, w); // Hits the fast path that doesn't enqueue w + wire_queue_entries(w); // Needed so we pick up the sig <-> w connection } // At this point we're done with creating wires and know which ones are @@ -346,7 +336,7 @@ void RTLIL::Module::bufNormalize() wire->driverPort_.clear(); } - // For the unique output cell ports fully connected to a full wire, we + // For the unique driving cell ports fully connected to a full wire, we // can update the bufnorm data right away. For all other wires we will // have to create new `$buf` cells. for (auto const &[wire, cellport] : direct_driven_wires) { @@ -373,54 +363,55 @@ void RTLIL::Module::bufNormalize() SigMap sigmap(this); new_connections({}); - pool conflicted; - pool driven; - - // We iterate over all direct driven wires and try to make that wire's - // sigbits the representative sigbit for the net. We do a second pass - // to detect conflicts to then remove the conflicts from `driven`. - for (bool check : {false, true}) { + // We pick SigMap representatives by prioritizing input ports over + // driven wires over other/unknown wires. + for (bool input_ports : {false, true}) { for (auto const &[wire, cellport] : direct_driven_wires) { - if (cellport.first == nullptr) - continue; - auto const &[cell, port] = cellport; - - SigSpec z_mask; - if (cell->type == ID($buf)) - z_mask = cell->getPort(ID::A); - - for (int i = 0; i != GetSize(wire); ++i) { - SigBit driver = SigBit(wire, i); - if (!z_mask.empty() && z_mask[i] == State::Sz) - continue; - if (check) { - SigBit repr = sigmap(driver); - if (repr != driver) - conflicted.insert(repr); - else - driven.insert(repr); - } else { + if ((wire->port_input && !wire->port_output) == input_ports) { + for (int i = 0; i != GetSize(wire); ++i) { + SigBit driver = SigBit(wire, i); sigmap.database.promote(driver); } } } } - // Ensure that module level inout ports are directly driven or - // connected using `$connect` cells and never `$buf`fered. - for (auto wire : wire_queue_entries) { - if (!wire->port_input || !wire->port_output) - continue; + // All three pool below are in terms of sigmapped bits + // Bits that are known to have a unique driver that is an unconditional driver or one or more inout drivers + pool driven; + // Bits that have multiple unconditional drivers, this forces the use of `$connect` + pool conflicted; + // Bits that are driven by an inout driver + pool weakly_driven; + + for (auto const &[wire, cellport] : direct_driven_wires) { + auto const &[cell, port] = cellport; for (int i = 0; i != GetSize(wire); ++i) { - SigBit driver = SigBit(wire, i); - SigBit repr = sigmap(driver); - if (driver != repr) - driven.erase(repr); + SigBit driver = sigmap(SigBit(wire, i)); + if (cell->type == ID($tribuf) || cell->port_dir(port) == RTLIL::PD_INOUT) { + // We add inout drivers to `driven` in a separate loop below + weakly_driven.insert(driver); + } else { + // We remove driver conflicts from `driven` in a separate loop below + bool inserted = driven.insert(driver).second; + if (!inserted) + conflicted.insert(driver); + } } } - for (auto &bit : conflicted) - driven.erase(bit); + // If a wire has one or more inout drivers and an unconditional driver, that's still a conflict + for (auto driver : weakly_driven) + if (!driven.insert(driver).second) + conflicted.insert(driver); + + // This only leaves the drivers matching `driven`'s definition above + for (auto driver : conflicted) + driven.erase(driver); + + // Having picked representatives and checked whether they are unique + // drivers, we can turn the connecitivty of our sigmap back into $buf + // and $connect cells. // Module level bitwise connections not representable by `$buf` cells pool> undirected_connections; @@ -561,6 +552,8 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) w->driverCell_ = nullptr; w->driverPort_ = IdString(); module->buf_norm_wire_queue.insert(w); + } else if (w->driverCell_) { + log_assert(w->driverCell_->getPort(w->driverPort_) == w); } } @@ -630,7 +623,8 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal // bufNormalize call if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) { Wire *w = signal.as_wire(); - if (w->driverCell_ == nullptr) { + if (w->driverCell_ == nullptr && ( + (w->port_input && !w->port_output) == (type == ID($input_port)))) { w->driverCell_ = this; w->driverPort_ = portname; diff --git a/tests/various/bufnorm_opt_clean.ys b/tests/various/bufnorm_opt_clean.ys new file mode 100644 index 000000000..e1036f920 --- /dev/null +++ b/tests/various/bufnorm_opt_clean.ys @@ -0,0 +1,154 @@ + +read_aiger < Date: Mon, 29 Sep 2025 12:26:43 +0200 Subject: [PATCH 186/188] opt_hier: Fix two optimizations conflicting Fix a conflict between the following two: * propagation of tied-together inputs in * propagation of unused inputs out --- passes/opt/opt_hier.cc | 19 ++++++++++++++----- tests/opt/bug5398.ys | 23 +++++++++++++++++++++++ 2 files changed, 37 insertions(+), 5 deletions(-) create mode 100644 tests/opt/bug5398.ys diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index a8df78dc1..06103b4be 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -310,7 +310,7 @@ struct UsageData { refine_tie_togethers(inputs); } - bool apply_changes() { + bool apply_changes(ModuleIndex &index) { bool did_something = false; if (module->get_blackbox_attribute()) { @@ -374,8 +374,16 @@ struct UsageData { // Propagate tied-together inputs dict ties; for (auto group : tie_together_inputs) { - for (int i = 1; i < group.size(); i++) - ties[group[i]] = group[0]; + // Only consider used inputs for a tie-together group. + // ModuleIndex::apply_changes might have disconnected + // unused inputs. + SigSpec filtered_group; + for (auto bit : group) { + if (index.used.check(bit)) + filtered_group.append(bit); + } + for (int i = 1; i < filtered_group.size(); i++) + ties[filtered_group[i]] = filtered_group[0]; } SigPool applied_ties; auto ties_rewrite = [&](SigSpec &signal) { @@ -449,12 +457,13 @@ struct OptHierPass : Pass { bool did_something = false; for (auto module : d->selected_modules(RTLIL::SELECT_WHOLE_ONLY, RTLIL::SB_UNBOXED_CMDERR)) { + ModuleIndex &parent_index = indices.at(module->name); + if (usage_datas.count(module->name)) { log_debug("Applying usage data changes to %s\n", log_id(module)); - did_something |= usage_datas.at(module->name).apply_changes(); + did_something |= usage_datas.at(module->name).apply_changes(parent_index); } - ModuleIndex &parent_index = indices.at(module->name); for (auto cell : module->cells()) { if (indices.count(cell->type)) { log_debug("Applying changes to instance %s of %s in %s\n", log_id(cell), log_id(cell->type), log_id(module)); diff --git a/tests/opt/bug5398.ys b/tests/opt/bug5398.ys new file mode 100644 index 000000000..93c5a2d52 --- /dev/null +++ b/tests/opt/bug5398.ys @@ -0,0 +1,23 @@ +read_verilog < Date: Mon, 29 Sep 2025 12:26:54 +0200 Subject: [PATCH 187/188] opt_hier: Adjust messages --- passes/opt/opt_hier.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index 06103b4be..5c3b09b31 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -144,12 +144,12 @@ struct ModuleIndex { } if (nunused > 0) { - log("Disconnected %d input bits of instance '%s' of '%s' in '%s'\n", + log("Disconnected %d input bits of instance '%s' (type '%s') in '%s'\n", nunused, log_id(instantiation), log_id(instantiation->type), log_id(parent.module)); changed = true; } if (nconstants > 0) { - log("Substituting constant for %d output bits of instance '%s' of '%s' in '%s'\n", + log("Substituting constant for %d output bits of instance '%s' (type '%s') in '%s'\n", nconstants, log_id(instantiation), log_id(instantiation->type), log_id(parent.module)); changed = true; } From acf3a6606ffef050f903c5c9e2d0cfcd2709fdac Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 28 Sep 2025 07:25:25 -0700 Subject: [PATCH 188/188] Small gitignore fixes --- .gitignore | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/.gitignore b/.gitignore index cac630d7c..47f758a9b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,9 @@ ## user config /Makefile.conf +## homebrew +/Brewfile.lock.json + ## build artifacts # compiler intermediate files *.o @@ -11,6 +14,12 @@ *.gcno *.so.dSYM/ +## test artifacts +**/run-test.mk +*.err +*.log +*.tmp + # compiler output files /kernel/version_*.cc /share