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Added "rename -top new_name"

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This commit is contained in:
Clifford Wolf 2015-06-17 09:38:56 +02:00
parent 9f7a5b4ef9
commit 99100f367d
3 changed files with 43 additions and 0 deletions
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27
passes/cmds/rename.cc
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@ -76,12 +76,17 @@ struct RenamePass : public Pass {
log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
log("with public names. This ignores all selected ports.\n");
log("\n");
log(" rename -top new_name\n");
log("\n");
log("Rename top module.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_enumerate = false;
bool flag_hide = false;
bool flag_top = false;
bool got_mode = false;
size_t argidx;
@ -98,6 +103,11 @@ struct RenamePass : public Pass {
got_mode = true;
continue;
}
if (arg == "-top" && !got_mode) {
flag_top = true;
got_mode = true;
continue;
}
if (arg == "-pattern" && argidx+1 < args.size() && args[argidx+1].find('%') != std::string::npos) {
int pos = args[++argidx].find('%');
pattern_prefix = args[argidx].substr(0, pos);
@ -171,6 +181,23 @@ struct RenamePass : public Pass {
}
}
else
if (flag_top)
{
if (argidx+1 != args.size())
log_cmd_error("Invalid number of arguments!\n");
IdString new_name = RTLIL::escape_id(args[argidx]);
RTLIL::Module *module = design->top_module();
if (module == NULL)
log_cmd_error("No top module found!\n");
log("Renaming module %s to %s.\n", log_id(module), log_id(new_name));
design->modules_.erase(module->name);
module->name = new_name;
design->modules_[module->name] = module;
}
else
{
if (argidx+2 != args.size())
log_cmd_error("Invalid number of arguments!\n");