mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

flatten: accept processes.

Browse source
This commit is contained in:
whitequark 2020-06-09 09:56:23 +00:00
parent 483a1081e7
commit 98e1080345
1 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

16
passes/techmap/flatten.cc
View file

@ -79,14 +79,6 @@ struct FlattenWorker
void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells)
{
if (tpl->processes.size() != 0) {
log("Flattening yielded processes:");
for (auto &it : tpl->processes)
log(" %s",log_id(it.first));
log("\n");
log_error("Flattening yielded processes -> this is not supported.\n");
}
// Copy the contents of the flattened cell
dict<IdString, IdString> memory_map;
@ -127,6 +119,14 @@ struct FlattenWorker
design->select(module, new_wire);
}
for (auto &tpl_proc_it : tpl->processes) {
RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
map_attributes(cell, new_proc, tpl_proc_it.second->name);
auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
new_proc->rewrite_sigspecs(rewriter);
design->select(module, new_proc);
}
for (auto tpl_cell : tpl->cells()) {
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell);
map_attributes(cell, new_cell, tpl_cell->name);