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Add check of begin/end labels for genblock

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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2021-02-04 12:12:59 +01:00
parent baf1875307
commit 98c4feb72f
2 changed files with 28 additions and 0 deletions
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26
tests/verilog/block_labels.ys Normal file
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read_verilog <<EOT
module foo;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : a
endmodule
EOT
read_verilog <<EOT
module foo2;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end
endmodule
EOT
logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
read_verilog <<EOT
module foo3;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : b
endmodule
EOT