3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-09 23:52:03 +00:00
This commit is contained in:
KrystalDelusion 2025-10-30 09:36:47 +01:00 committed by GitHub
commit 98bb5f0edd
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
4 changed files with 99 additions and 30 deletions

View file

@ -0,0 +1,33 @@
read_verilog -sv << EOF
interface simple_if;
logic receiver;
logic driver;
endinterface
module driver_mod(simple_if intf, input in);
assign intf.driver = in;
endmodule
module receiver_mod(simple_if intf);
assign intf.receiver = intf.driver;
endmodule
module top(
input logic [1:0] inputs,
output logic [1:0] outputs
);
simple_if intf0();
simple_if intf1();
driver_mod d0(intf0, inputs[0]);
driver_mod d1(intf1, inputs[1]);
receiver_mod r0(intf0);
receiver_mod r1(intf1);
assign outputs = {intf0.receiver, intf1.receiver};
endmodule
EOF
logger -expect error "Unable to connect.* with positional interface" 1
hierarchy -top top

View file

@ -5,3 +5,4 @@
./run_simple.sh load_and_derive
./run_simple.sh resolve_types
./run_simple.sh positional_args