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Progress in presentation

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This commit is contained in:
Clifford Wolf 2014-02-20 12:46:29 +01:00
parent 772330608a
commit 98940260e1
10 changed files with 152 additions and 10 deletions
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10
manual/PRESENTATION_ExAdv/Makefile
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@ -1,8 +1,9 @@
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
macc_simple_xmap.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
select.pdf: select.v select.ys
../../yosys select.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys
@ -19,3 +20,6 @@ mulshift.pdf: mulshift_*
addshift.pdf: addshift_*
../../yosys addshift_test.ys
macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
../../yosys macc_simple_test.ys

6
manual/PRESENTATION_ExAdv/macc_simple_test.v Normal file
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module test(a, b, c, d, y);
input [15:0] a, b;
input [31:0] c, d;
output [31:0] y;
assign y = a * b + c + d;
endmodule

36
manual/PRESENTATION_ExAdv/macc_simple_test.ys Normal file
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read_verilog macc_simple_test.v
hierarchy -check -top test;;
show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
extract -constports -map macc_simple_xmap.v;;
show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
read_verilog macc_simple_test_01.v
hierarchy -check -top test;;
show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_02.v
hierarchy -check -top test;;
show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
extract -map macc_simple_xmap.v;;
show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_xmap.v
hierarchy -check -top macc_16_16_32;;
show -prefix macc_simple_xmap -format pdf -notitle

6
manual/PRESENTATION_ExAdv/macc_simple_test_01.v Normal file
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module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + c*d + x;
endmodule

6
manual/PRESENTATION_ExAdv/macc_simple_test_02.v Normal file
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@ -0,0 +1,6 @@
module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + (c*d + x);
endmodule

6
manual/PRESENTATION_ExAdv/macc_simple_xmap.v Normal file
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@ -0,0 +1,6 @@
module macc_16_16_32(a, b, c, y);
input [15:0] a, b;
input [31:0] c;
output [31:0] y;
assign y = a*b + c;
endmodule

0
manual/PRESENTATION_ExAdv/select_01.v → manual/PRESENTATION_ExAdv/select.v
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4
manual/PRESENTATION_ExAdv/select_01.ys → manual/PRESENTATION_ExAdv/select.ys
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@ -1,10 +1,10 @@
read_verilog select_01.v
read_verilog select.v
hierarchy -check -top test
proc; opt
cd test
select -set cone_a state_a %ci*:-$dff
select -set cone_b state_b %ci*:-$dff
select -set cone_ab @cone_a @cone_b %i
show -prefix select_01 -format pdf -notitle \
show -prefix select -format pdf -notitle \
-color red @cone_ab -color magenta @cone_a \
-color blue @cone_b