Docs: tidying

- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples.  Formatted `:file:` text with link
  to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
  intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.

docs/source/yosys_internals/extending_yosys/abc_flow.rst

@@ -22,7 +22,7 @@ guide to the syntax:
 
 By convention, all delays in ``specify`` blocks are in integer picoseconds.
 Files containing ``specify`` blocks should be read with the ``-specify`` option
-to ``read_verilog`` so that they aren't skipped.
+to :cmd:ref:`read_verilog` so that they aren't skipped.
 
 LUTs
 ^^^^
@@ -41,9 +41,9 @@ DFFs
 
 DFFs should be annotated with an ``(* abc9_flop *)`` attribute, however ABC9 has
 some specific requirements for this to be valid: - the DFF must initialise to
-zero (consider using ``dfflegalize`` to ensure this). - the DFF cannot have any
-asynchronous resets/sets (see the simplification idiom and the Boxes section for
-what to do here).
+zero (consider using :cmd:ref:`dfflegalize` to ensure this). - the DFF cannot
+have any asynchronous resets/sets (see the simplification idiom and the Boxes
+section for what to do here).
 
 It is worth noting that in pure ``abc9`` mode, only the setup and arrival times
 are passed to ABC9 (specifically, they are modelled as buffers with the given
@@ -59,7 +59,7 @@ mapped back to the original flop. This is used in :cmd:ref:`synth_intel_alm` and
 :cmd:ref:`synth_quicklogic` for the PolarPro3.
 
 DFFs are usually specified to have setup constraints against the clock on the
-input signals, and an arrival time for the Q output.
+input signals, and an arrival time for the ``Q`` output.
 
 Boxes
 ^^^^^

docs/source/yosys_internals/extending_yosys/extensions.rst

@@ -6,7 +6,7 @@ Writing extensions
 
 .. todo:: check text is coherent
 
-.. todo:: update to use ``/code_examples/extensions/test*.log``
+.. todo:: update to use :file:`/code_examples/extensions/test*.log`
 
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
@@ -21,7 +21,11 @@ Quick guide
 -----------
 
 Code examples from this section are included in the
-``docs/code_examples/extensions/`` directory of the Yosys source code.
+|code_examples/extensions|_ directory of the Yosys source code.
+
+.. |code_examples/extensions| replace:: :file:`docs/source/code_examples/extensions`
+.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/extensions
+
 
 Program components and data formats
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -31,7 +35,7 @@ about the internal data storage format used in Yosys and the classes that it
 provides.
 
 This document will focus on the much simpler version of RTLIL left after the
-commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
+commands :cmd:ref:`proc` and :cmd:ref:`memory` (or :yoscrypt:`memory -nomap`):
 
 .. figure:: /_images/internals/simplified_rtlil.*
     :class: width-helper
@@ -41,6 +45,8 @@ commands :cmd:ref:`proc` and :cmd:ref:`memory` (or ``memory -nomap``):
 
 It is possible to only work on this simpler version:
 
+.. todo:: consider replacing inline code
+
 .. code:: c++
 
     for (RTLIL::Module *module : design->selected_modules() {
@@ -66,10 +72,10 @@ with, and lists off the current design's modules.
 .. literalinclude:: /code_examples/extensions/my_cmd.cc
    :language: c++
    :lines: 1, 4, 6, 7-20
-   :caption: Example command :yoscrypt:`my_cmd` from ``my_cmd.cc``
+   :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc`
    
 Note that we are making a global instance of a class derived from
-``Yosys::Pass``, which we get by including ``kernel/yosys.h``.
+``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`.
 
 Compiling to a plugin
 ~~~~~~~~~~~~~~~~~~~~~
@@ -80,6 +86,8 @@ to create plugins.
 
 The following command compiles our example :yoscrypt:`my_cmd` to a Yosys plugin:
 
+.. todo:: replace inline code
+
 .. code:: shell
 
    yosys-config --exec --cxx --cxxflags --ldflags \
@@ -120,7 +128,7 @@ We'll do the same as before and format it as a a ``Yosys::Pass``.
 .. literalinclude:: /code_examples/extensions/my_cmd.cc
    :language: c++
    :lines: 23-47
-   :caption: :yoscrypt:`test1` - creating the absval module, from ``my_cmd.cc``
+   :caption: :yoscrypt:`test1` - creating the absval module, from :file:`my_cmd.cc`
 
 .. code:: shell-session
 
@@ -160,7 +168,7 @@ Consider the following module:
 
 .. literalinclude:: /code_examples/extensions/sigmap_test.v
    :language: Verilog
-   :caption: sigmap_test.v
+   :caption: :file:`sigmap_test.v`
 
 In this case ``a``, ``x``, and ``y`` are all different names for the same
 signal. However:
@@ -204,7 +212,10 @@ Use ``log_id()`` to create a C-string for an ``RTLIL::IdString``:
 
     log("Name of this module: %s\n", log_id(module->name));
 
-Use ``log_header()`` and ``log_push()``/``log_pop()`` to structure log messages:
+Use ``log_header()`` and ``log_push()``/\ ``log_pop()`` to structure log
+messages:
+
+.. todo:: replace inline code
 
 .. code:: C++
 
@@ -219,6 +230,8 @@ Error handling
 
 Use ``log_error()`` to report a non-recoverable error:
 
+.. todo:: replace inline code
+
 .. code:: C++
 
     if (design->modules.count(module->name) != 0)
@@ -238,20 +251,22 @@ The "stubnets" example module
 ------------------------------
 
 The following is the complete code of the "stubnets" example module. It is
-included in the Yosys source distribution as
-``docs/source/code_examples/stubnets/stubnets.cc``.
+included in the Yosys source distribution under |code_examples/stubnets|_.
+
+.. |code_examples/stubnets| replace:: :file:`docs/source/code_examples/stubnets`
+.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/stubnets
 
 .. literalinclude:: /code_examples/stubnets/stubnets.cc
     :language: c++
     :linenos:
-    :caption: docs/source/code_examples/stubnets/stubnets.cc
+    :caption: :file:`stubnets.cc`
 
 .. literalinclude:: /code_examples/stubnets/Makefile
     :language: makefile
     :linenos:
-    :caption: docs/source/code_examples/stubnets/Makefile
+    :caption: :file:`Makefile`
 
 .. literalinclude:: /code_examples/stubnets/test.v
     :language: verilog
     :linenos:
-    :caption: docs/source/code_examples/stubnets/test.v
+    :caption: :file:`test.v`