Docs: tidying

- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples.  Formatted `:file:` text with link
  to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
  intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -7,16 +7,16 @@ Mapping to cell libraries
 While much of this documentation focuses on the use of Yosys with FPGAs, it is
 also possible to map to cell libraries which can be used in designing ASICs.
 This section will cover a brief `example project`_, available in the Yosys
-source code as ``docs/source/code_examples/intro/*``.  The project contains a
-simple ASIC synthesis script (``counter.ys``), a digital design written in
-Verilog (``counter.v``), and a simple CMOS cell library (``mycells.lib``).  Many
-of the early steps here are already covered in more detail in the
-:doc:`/getting_started/example_synth` document.
+source code under :file:`docs/source/code_examples/intro/`.  The project
+contains a simple ASIC synthesis script (:file:`counter.ys`), a digital design
+written in Verilog (:file:`counter.v`), and a simple CMOS cell library
+(:file:`mycells.lib`).  Many of the early steps here are already covered in more
+detail in the :doc:`/getting_started/example_synth` document.
 
 .. note::
 
-   The ``counter.ys`` script includes the commands used to generate the images
-   in this document.  Code snippets in this document skip these commands;
+   The :file:`counter.ys` script includes the commands used to generate the
+   images in this document.  Code snippets in this document skip these commands;
    including line numbers to allow the reader to follow along with the source.
    
    To learn more about these commands, check out :ref:`interactive_show`.
@@ -32,7 +32,7 @@ First, let's quickly look at the design:
    :language: Verilog
    :linenos:
    :name: counter-v
-   :caption: ``counter.v``
+   :caption: :file:`counter.v`
 
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
@@ -46,7 +46,7 @@ Loading the design
    :language: yoscrypt
    :lines: 1-3
    :lineno-match:
-   :caption: ``counter.ys`` - read design
+   :caption: :file:`counter.ys` - read design
 
 Our circuit now looks like this:
 
@@ -63,7 +63,7 @@ Coarse-grain representation
    :language: yoscrypt
    :lines: 7-10
    :lineno-match:
-   :caption: ``counter.ys`` - the high-level stuff
+   :caption: :file:`counter.ys` - the high-level stuff
 
 .. figure:: /_images/code_examples/intro/counter_01.*
    :class: width-helper
@@ -77,7 +77,7 @@ Logic gate mapping
    :language: yoscrypt
    :lines: 14-15
    :lineno-match:
-   :caption: ``counter.ys`` - mapping to internal cell library
+   :caption: :file:`counter.ys` - mapping to internal cell library
 
 .. figure:: /_images/code_examples/intro/counter_02.*
    :class: width-helper
@@ -94,7 +94,7 @@ our internal cell library will be mapped to:
    :language: Liberty
    :linenos:
    :name: mycells-lib
-   :caption: ``mycells.lib``
+   :caption: :file:`mycells.lib`
 
 Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
 ``$_OR_``, ``$_XOR_``, and ``$_MUX_`` with an assortment of dff memory types.
@@ -106,7 +106,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
    :language: yoscrypt
    :lines: 20-27
    :lineno-match:
-   :caption: ``counter.ys`` - mapping to hardware
+   :caption: :file:`counter.ys` - mapping to hardware
 
 The final version of our ``counter`` module looks like this:
 
@@ -122,4 +122,4 @@ which can then be loaded into another tool:
    :language: yoscrypt
    :lines: 30-31
    :lineno-match:
-   :caption: ``counter.ys`` - write synthesized design
+   :caption: :file:`counter.ys` - write synthesized design