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Docs: tidying

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- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples.  Formatted `:file:` text with link
  to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
  intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.
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Krystine Sherwin 2024-01-30 13:31:00 +13:00
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28
docs/source/using_yosys/synthesis/cell_libs.rst
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@ -7,16 +7,16 @@ Mapping to cell libraries
While much of this documentation focuses on the use of Yosys with FPGAs, it is
also possible to map to cell libraries which can be used in designing ASICs.
This section will cover a brief `example project`_, available in the Yosys
source code as ``docs/source/code_examples/intro/*``. The project contains a
simple ASIC synthesis script (``counter.ys``), a digital design written in
Verilog (``counter.v``), and a simple CMOS cell library (``mycells.lib``). Many
of the early steps here are already covered in more detail in the
:doc:`/getting_started/example_synth` document.
source code under :file:`docs/source/code_examples/intro/`. The project
contains a simple ASIC synthesis script (:file:`counter.ys`), a digital design
written in Verilog (:file:`counter.v`), and a simple CMOS cell library
(:file:`mycells.lib`). Many of the early steps here are already covered in more
detail in the :doc:`/getting_started/example_synth` document.
.. note::
The ``counter.ys`` script includes the commands used to generate the images
in this document. Code snippets in this document skip these commands;
The :file:`counter.ys` script includes the commands used to generate the
images in this document. Code snippets in this document skip these commands;
including line numbers to allow the reader to follow along with the source.
To learn more about these commands, check out :ref:`interactive_show`.
@ -32,7 +32,7 @@ First, let's quickly look at the design:
:language: Verilog
:linenos:
:name: counter-v
:caption: ``counter.v``
:caption: :file:`counter.v`
This is a simple counter with reset and enable. If the reset signal, ``rst``,
is high then the counter will reset to 0. Otherwise, if the enable signal,
@ -46,7 +46,7 @@ Loading the design
:language: yoscrypt
:lines: 1-3
:lineno-match:
:caption: ``counter.ys`` - read design
:caption: :file:`counter.ys` - read design
Our circuit now looks like this:
@ -63,7 +63,7 @@ Coarse-grain representation
:language: yoscrypt
:lines: 7-10
:lineno-match:
:caption: ``counter.ys`` - the high-level stuff
:caption: :file:`counter.ys` - the high-level stuff
.. figure:: /_images/code_examples/intro/counter_01.*
:class: width-helper
@ -77,7 +77,7 @@ Logic gate mapping
:language: yoscrypt
:lines: 14-15
:lineno-match:
:caption: ``counter.ys`` - mapping to internal cell library
:caption: :file:`counter.ys` - mapping to internal cell library
.. figure:: /_images/code_examples/intro/counter_02.*
:class: width-helper
@ -94,7 +94,7 @@ our internal cell library will be mapped to:
:language: Liberty
:linenos:
:name: mycells-lib
:caption: ``mycells.lib``
:caption: :file:`mycells.lib`
Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
``$_OR_``, ``$_XOR_``, and ``$_MUX_`` with an assortment of dff memory types.
@ -106,7 +106,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
:language: yoscrypt
:lines: 20-27
:lineno-match:
:caption: ``counter.ys`` - mapping to hardware
:caption: :file:`counter.ys` - mapping to hardware
The final version of our ``counter`` module looks like this:
@ -122,4 +122,4 @@ which can then be loaded into another tool:
:language: yoscrypt
:lines: 30-31
:lineno-match:
:caption: ``counter.ys`` - write synthesized design
:caption: :file:`counter.ys` - write synthesized design

45
docs/source/using_yosys/synthesis/extract.rst
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@ -12,7 +12,11 @@ The extract pass
.. todo:: add/expand supporting text, also mention custom pattern matching and
pmgen
Example code can be found in ``docs/source/code_examples/macc/``.
Example code can be found in |code_examples/macc|_.
.. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc`
.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/macc
.. literalinclude:: /code_examples/macc/macc_simple_test.ys
:language: yoscrypt
@ -34,15 +38,15 @@ Example code can be found in ``docs/source/code_examples/macc/``.
.. literalinclude:: /code_examples/macc/macc_simple_test.v
:language: verilog
:caption: ``macc_simple_test.v``
:caption: :file:`macc_simple_test.v`
.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
:language: verilog
:caption: ``macc_simple_xmap.v``
:caption: :file:`macc_simple_xmap.v`
.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
:language: verilog
:caption: ``macc_simple_test_01.v``
:caption: :file:`macc_simple_test_01.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
:class: width-helper
@ -52,7 +56,7 @@ Example code can be found in ``docs/source/code_examples/macc/``.
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
:language: verilog
:caption: ``macc_simple_test_02.v``
:caption: :file:`macc_simple_test_02.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
:class: width-helper
@ -90,10 +94,9 @@ Example: DSP48_MACC
This section details an example that shows how to map MACC operations of
arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder
(such as the Xilinx DSP48 cells). Source code can be found in
``docs/source/code_examples/macc/``.
(such as the Xilinx DSP48 cells).
Preconditioning: ``macc_xilinx_swap_map.v``
Preconditioning: :file:`macc_xilinx_swap_map.v`
Make sure ``A`` is the smaller port on all multipliers
@ -101,49 +104,49 @@ Make sure ``A`` is the smaller port on all multipliers
.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
:language: verilog
:caption: ``macc_xilinx_swap_map.v``
:caption: :file:`macc_xilinx_swap_map.v`
Wrapping multipliers: ``macc_xilinx_wrap_map.v``
Wrapping multipliers: :file:`macc_xilinx_wrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 1-46
:caption: ``macc_xilinx_wrap_map.v``
:caption: :file:`macc_xilinx_wrap_map.v`
Wrapping adders: ``macc_xilinx_wrap_map.v``
Wrapping adders: :file:`macc_xilinx_wrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 48-89
:caption: ``macc_xilinx_wrap_map.v``
:caption: :file:`macc_xilinx_wrap_map.v`
Extract: ``macc_xilinx_xmap.v``
Extract: :file:`macc_xilinx_xmap.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
:language: verilog
:caption: ``macc_xilinx_xmap.v``
:caption: :file:`macc_xilinx_xmap.v`
... simply use the same wrapping commands on this module as on the design to
create a template for the :cmd:ref:`extract` command.
Unwrapping multipliers: ``macc_xilinx_unwrap_map.v``
Unwrapping multipliers: :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 1-30
:caption: ``$__mul_wrapper`` module in ``macc_xilinx_unwrap_map.v``
:caption: ``$__mul_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
Unwrapping adders: ``macc_xilinx_unwrap_map.v``
Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 32-61
:caption: ``$__add_wrapper`` module in ``macc_xilinx_unwrap_map.v``
:caption: ``$__add_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 1-6
:caption: ``test1`` of ``macc_xilinx_test.v``
:caption: ``test1`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
:class: width-helper
@ -154,7 +157,7 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 8-13
:caption: ``test2`` of ``macc_xilinx_test.v``
:caption: ``test2`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
:class: width-helper

15
docs/source/using_yosys/synthesis/memory.rst
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@ -33,27 +33,32 @@ Example
.. todo:: describe ``memory`` images
|code_examples/synth_flow|_.
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/synth_flow
.. figure:: /_images/code_examples/synth_flow/memory_01.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
:caption: :file:`memory_01.ys`
.. literalinclude:: /code_examples/synth_flow/memory_01.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/memory_01.v``
:caption: :file:`memory_01.v`
.. figure:: /_images/code_examples/synth_flow/memory_02.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/memory_02.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/memory_02.v``
:caption: :file:`memory_02.v`
.. literalinclude:: /code_examples/synth_flow/memory_02.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
:caption: :file:`memory_02.ys`
.. _memory_map:
@ -71,7 +76,7 @@ For example:
memory_map
:cmd:ref:`memory_libmap` attempts to convert memory cells (``$mem_v2`` etc) into
hardware supported memory using a provided library (``my_memory_map.txt`` in the
hardware supported memory using a provided library (:file:`my_memory_map.txt` in the
example above). Where necessary, emulation logic is added to ensure functional
equivalence before and after this conversion. :yoscrypt:`techmap -map
my_memory_map.v` then uses :cmd:ref:`techmap` to map to hardware primitives. Any

17
docs/source/using_yosys/synthesis/proc.rst
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@ -28,13 +28,18 @@ Example
.. todo:: describe ``proc`` images
|code_examples/synth_flow|_.
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/synth_flow
.. literalinclude:: /code_examples/synth_flow/proc_01.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_01.v``
:caption: :file:`proc_01.v`
.. literalinclude:: /code_examples/synth_flow/proc_01.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
:caption: :file:`proc_01.ys`
.. figure:: /_images/code_examples/synth_flow/proc_01.*
:class: width-helper
@ -44,19 +49,19 @@ Example
.. literalinclude:: /code_examples/synth_flow/proc_02.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_02.v``
:caption: :file:`proc_02.v`
.. literalinclude:: /code_examples/synth_flow/proc_02.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
:caption: :file:`proc_02.ys`
.. figure:: /_images/code_examples/synth_flow/proc_03.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
:caption: :file:`proc_03.ys`
.. literalinclude:: /code_examples/synth_flow/proc_03.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_03.v``
:caption: :file:`proc_03.v`