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- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples.  Formatted `:file:` text with link
  to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
  intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.
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109
docs/source/using_yosys/more_scripting/interactive_investigation.rst
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@ -1,6 +1,8 @@
Interactive design investigation
--------------------------------
.. todo:: interactive design opening text
.. role:: yoscrypt(code)
:language: yoscrypt
@ -9,22 +11,24 @@ Interactive design investigation
A look at the show command
~~~~~~~~~~~~~~~~~~~~~~~~~~
.. TODO:: merge into :doc:`/getting_started/scripting_intro` show section
This section explores the :cmd:ref:`show` command and explains the symbols used
in the circuit diagrams generated by it.
in the circuit diagrams generated by it. The code used is included in the Yosys
code base under |code_examples/show|_.
.. |code_examples/show| replace:: :file:`docs/source/code_examples/show`
.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/show
A simple circuit
^^^^^^^^^^^^^^^^
:ref:`example_v` below provides the Verilog code for a simple circuit which we
will use to demonstrate the usage of :cmd:ref:`show` in a simple setting. The
code used is included in the Yosys code base under
`docs/source/code_examples/show`_.
.. _docs/source/code_examples/show: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/show
will use to demonstrate the usage of :cmd:ref:`show` in a simple setting.
.. literalinclude:: /code_examples/show/example.v
:language: Verilog
:caption: ``example.v``
:caption: :file:`example.v`
:name: example_v
The Yosys synthesis script we will be running is included as
@ -36,7 +40,7 @@ synthesis.
.. literalinclude:: /code_examples/show/example_show.ys
:language: yoscrypt
:caption: ``example_show.ys``
:caption: :file:`example_show.ys`
:name: example_ys
This script, when executed, will show the design after each of the three
@ -45,11 +49,11 @@ is shown.
.. note::
The images uses in this document are generated from the ``example.ys`` file,
rather than ``example_show.ys``. ``example.ys`` outputs the schematics as
``.dot`` files rather than displaying them directly. You can view these
images yourself by running ``yosys example.ys`` and then ``xdot
example_first.dot`` etc.
The images uses in this document are generated from the :file:`example.ys`
file, rather than :file:`example_show.ys`. :file:`example.ys` outputs the
schematics as :file:`.dot` files rather than displaying them directly. You
can view these images yourself by running :file:`yosys example.ys` and then
``xdot example_first.dot`` etc.
.. figure:: /_images/code_examples/show/example_first.*
:class: width-helper
@ -122,7 +126,7 @@ The code listing below shows a simple circuit which uses a lot of spliced signal
accesses.
.. literalinclude:: /code_examples/show/splice.v
:caption: ``docs/source/code_examples/show/splice.v``
:caption: :file:`splice.v`
:name: splice_src
Notice how the output for this circuit from the :cmd:ref:`show` command
@ -199,15 +203,15 @@ library as Verilog file containing blackbox modules. There are two ways to load
cell descriptions into Yosys: First the Verilog file for the cell library can be
passed directly to the :cmd:ref:`show` command using the ``-lib <filename>``
option. Secondly it is possible to load cell libraries into the design with the
``read_verilog -lib <filename>`` command. The second method has the great
advantage that the library only needs to be loaded once and can then be used in
all subsequent calls to the :cmd:ref:`show` command.
:yoscrypt:`read_verilog -lib <filename>` command. The second method has the
great advantage that the library only needs to be loaded once and can then be
used in all subsequent calls to the :cmd:ref:`show` command.
In addition to that, :numref:`second_pitfall` was generated after ``splitnet
-ports`` was run on the design. This command splits all signal vectors into
individual signal bits, which is often desirable when looking at gate-level
circuits. The ``-ports`` option is required to also split module ports. Per
default the command only operates on interior signals.
In addition to that, :numref:`second_pitfall` was generated after
:yoscrypt:`splitnet -ports` was run on the design. This command splits all
signal vectors into individual signal bits, which is often desirable when
looking at gate-level circuits. The ``-ports`` option is required to also split
module ports. Per default the command only operates on interior signals.
Miscellaneous notes
^^^^^^^^^^^^^^^^^^^
@ -225,16 +229,16 @@ colors to the nets. The integer (> 0) is used as seed value for the random color
assignments. Sometimes it is necessary it try some values to find an assignment
of colors that looks good.
The command ``help show`` prints a complete listing of all options supported by
the :cmd:ref:`show` command.
The command :yoscrypt:`help show` prints a complete listing of all options
supported by the :cmd:ref:`show` command.
Navigating the design
~~~~~~~~~~~~~~~~~~~~~
Plotting circuit diagrams for entire modules in the design brings us
only helps in simple cases. For complex modules the generated circuit
diagrams are just stupidly big and are no help at all. In such cases one
first has to select the relevant portions of the circuit.
Plotting circuit diagrams for entire modules in the design brings us only helps
in simple cases. For complex modules the generated circuit diagrams are just
stupidly big and are no help at all. In such cases one first has to select the
relevant portions of the circuit.
In addition to *what* to display one also needs to carefully decide *when* to
display it, with respect to the synthesis flow. In general it is a good idea to
@ -244,10 +248,12 @@ reproduced. So if, for example, the internal state before calling the
the coarse-grain version of the circuit before :cmd:ref:`techmap` than the
gate-level circuit after :cmd:ref:`techmap`.
.. Note:: It is generally recommended to verify the internal state of a
design by writing it to a Verilog file using ``write_verilog -noexpr``
and using the simulation models from ``simlib.v`` and ``simcells.v``
from the Yosys data directory (as printed by ``yosys-config --datdir``).
.. Note::
It is generally recommended to verify the internal state of a design by
writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
using the simulation models from :file:`simlib.v` and :file:`simcells.v` from
the Yosys data directory (as printed by ``yosys-config --datdir``).
Interactive navigation
^^^^^^^^^^^^^^^^^^^^^^
@ -263,13 +269,14 @@ the synthesis script does not already narrow the selection). The command
:cmd:ref:`ls` can now be used to create a list of all modules. The command
:cmd:ref:`cd` can be used to switch to one of the modules (type ``cd ..`` to
switch back). Now the :cmd:ref:`ls` command lists the objects within that
module. This is demonstrated below using ``example.v`` from `A simple circuit`_:
module. This is demonstrated below using :file:`example.v` from `A simple
circuit`_:
.. literalinclude:: /code_examples/show/example.out
:language: doscon
:start-at: yosys> ls
:end-before: yosys [example]> dump
:caption: Output of :cmd:ref:`ls` and :cmd:ref:`cd` after running ``yosys example.v``
:caption: Output of :cmd:ref:`ls` and :cmd:ref:`cd` after running :file:`yosys example.v`
:name: lscd
When a module is selected using the :cmd:ref:`cd` command, all commands (with a
@ -324,6 +331,12 @@ tools).
- :doc:`/cmd/dump`.
- :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
design dynamically.
The code used is included in the Yosys code base under
|code_examples/scrambler|_.
.. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler`
.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/scrambler
Changing design hierarchy
^^^^^^^^^^^^^^^^^^^^^^^^^
@ -336,11 +349,11 @@ reorganizing a module in Yosys and checking the resulting circuit.
.. literalinclude:: /code_examples/scrambler/scrambler.v
:language: verilog
:caption: ``docs/source/code_examples/scrambler/scrambler.v``
:caption: :file:`scrambler.v`
.. literalinclude:: /code_examples/scrambler/scrambler.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/scrambler/scrambler.ys``
:caption: :file:`scrambler.ys`
:end-before: cd ..
.. figure:: /_images/code_examples/scrambler/scrambler_p01.*
@ -351,6 +364,8 @@ reorganizing a module in Yosys and checking the resulting circuit.
Analyzing the resulting circuit with :doc:`/cmd/eval`:
.. todo:: replace inline code
.. code:: text
> cd xorshift32
@ -381,6 +396,8 @@ The following techmap map file replaces all positive-edge async reset flip-flops
with positive-edge sync reset flip-flops. The code is taken from the example
Yosys script for ASIC synthesis of the Amber ARMv2 CPU.
.. todo:: replace inline code
.. code:: verilog
(* techmap_celltype = "$adff" *)
@ -435,7 +452,7 @@ sections: ``outstage``, ``selstage``, and ``scramble``.
.. literalinclude:: /code_examples/selections/submod.ys
:language: yoscrypt
:caption: Using :cmd:ref:`submod` to break up the circuit from ``memdemo.v``
:caption: Using :cmd:ref:`submod` to break up the circuit from :file:`memdemo.v`
:start-after: cd memdemo
:end-before: cd ..
:name: submod
@ -467,6 +484,8 @@ The :cmd:ref:`eval` command can be used to evaluate combinatorial circuits. As
an example, we will use the ``selstage`` subnet of ``memdemo`` which we found
above and is shown in :numref:`selstage`.
.. todo:: replace inline code
::
yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
@ -535,6 +554,8 @@ The :cmd:ref:`sat` command works very similar to the :cmd:ref:`eval` command.
The main difference is that it is now also possible to set output values and
find the corresponding input values. For Example:
.. todo:: replace inline code
::
yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
@ -569,7 +590,7 @@ circuit.)
.. literalinclude:: /code_examples/primetest.v
:language: verilog
:caption: ``primetest.v``, a simple miter circuit for testing if a number is
:caption: :file:`primetest.v`, a simple miter circuit for testing if a number is
prime. But it has a problem.
:name: primetest
@ -577,8 +598,10 @@ circuit.)
number test. If ``ok`` is 1 for all input values ``a`` and ``b`` for a given
``p``, then ``p`` is prime, or at least that is the idea.
.. todo:: replace inline code
.. code-block::
:caption: Experiments with the miter circuit from ``primetest.v``.
:caption: Experiments with the miter circuit from :file:`primetest.v`.
:name: prime_shell
yosys [primetest]> sat -prove ok 1 -set p 31
@ -621,8 +644,10 @@ purpose of this document is to show off Yosys features) we can also simply force
the upper 8 bits of ``a`` and ``b`` to zero for the :cmd:ref:`sat` call, as is
done below.
.. todo:: replace inline code
.. code-block::
:caption: Miter circuit from ``primetest.v``, with the upper 8 bits of ``a``
:caption: Miter circuit from :file:`primetest.v`, with the upper 8 bits of ``a``
and ``b`` constrained to prevent overflow.
:name: prime_fixed
@ -672,6 +697,8 @@ want to know which sequence of input values for ``d`` will cause the output y to
produce the sequence 1, 2, 3 from any initial state. Let's use the following
command:
.. todo:: replace inline code?
.. code-block:: yoscrypt
sat -seq 6 -show y -show d -set-init-undef \
@ -695,6 +722,8 @@ play the 1, 2, 3 sequence, starting with time step 4.
This produces the following output:
.. todo:: replace inline code
.. code-block::
:caption: Solving a sequential SAT problem in the ``memdemo`` module.
:name: memdemo_sat

32
docs/source/using_yosys/more_scripting/model_checking.rst
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@ -25,23 +25,27 @@ Checking techmap
.. todo:: add/expand supporting text
Let's look at the following example:
Let's take a look at an example included in the Yosys code base under
|code_examples/synth_flow|_:
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/synth_flow
.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
:caption: :file:`techmap_01_map.v`
.. literalinclude:: /code_examples/synth_flow/techmap_01.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
:caption: :file:`techmap_01.v`
.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
:caption: :file:`techmap_01.ys`
To see if it is correct we can use the following code:
.. todo:: replace inline yosys script code
.. todo:: replace inline code
.. code:: yoscrypt
@ -73,6 +77,12 @@ Result:
AXI4 Stream Master
~~~~~~~~~~~~~~~~~~
The code used in this section is included in the Yosys code base under
|code_examples/axis|_.
.. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/axis
The following AXI4 Stream Master has a bug. But the bug is not exposed if the
slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
@ -83,24 +93,26 @@ values for ``tready`` that yield the incorrect behavior.
.. literalinclude:: /code_examples/axis/axis_master.v
:language: verilog
:caption: ``docs/source/code_examples/axis/axis_master.v``
:caption: :file:`axis_master.v`
.. literalinclude:: /code_examples/axis/axis_test.v
:language: verilog
:caption: ``docs/source/code_examples/axis/axis_test.v``
:caption: :file:`axis_test.v`
.. literalinclude:: /code_examples/axis/axis_test.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/axis/test.ys``
:caption: :file:`test.ys`
Result with unmodified ``axis_master.v``:
Result with unmodified :file:`axis_master.v`:
.. todo:: replace inline code
.. code::
Solving problem with 159344 variables and 442126 clauses..
SAT proof finished - model found: FAIL!
Result with fixed ``axis_master.v``:
Result with fixed :file:`axis_master.v`:
.. code::

28
docs/source/using_yosys/more_scripting/selections.rst
View file

@ -7,6 +7,8 @@ Selections
The selection framework
~~~~~~~~~~~~~~~~~~~~~~~
.. todo:: reduce overlap with :doc:`/getting_started/scripting_intro` select section
The :cmd:ref:`select` command can be used to create a selection for subsequent
commands. For example:
@ -56,7 +58,7 @@ in synthesis scripts that are hand-tailored for a specific design.
Module and design context
^^^^^^^^^^^^^^^^^^^^^^^^^
Commands can be executed in *module/* or *design/* context. Until now all
Commands can be executed in *module/* or *design/* context. Until now, all
commands have been executed in design context. The :cmd:ref:`cd` command can be
used to switch to module context.
@ -83,9 +85,12 @@ Selecting by object property or type
Special patterns can be used to select by object property or type. For example:
- select all wires whose names start with ``reg_``: :yoscrypt:`select w:reg_*`
- select all objects with the attribute ``foobar`` set: :yoscrypt:`select a:foobar`
- select all objects with the attribute ``foobar`` set to 42: :yoscrypt:`select a:foobar=42`
- select all modules with the attribute ``blabla`` set: :yoscrypt:`select A:blabla`
- select all objects with the attribute ``foobar`` set: :yoscrypt:`select
a:foobar`
- select all objects with the attribute ``foobar`` set to 42: :yoscrypt:`select
a:foobar=42`
- select all modules with the attribute ``blabla`` set: :yoscrypt:`select
A:blabla`
- select all $add cells from the module foo: :yoscrypt:`select foo/t:$add`
A complete list of pattern expressions can be found in :doc:`/cmd/select`.
@ -255,11 +260,11 @@ code is available in ``docs/source/code_examples/selections`` of the Yosys
source repository.
.. literalinclude:: /code_examples/selections/memdemo.v
:caption: ``memdemo.v``
:caption: :file:`memdemo.v`
:name: memdemo_src
:language: verilog
The script ``memdemo.ys`` is used to generate the images included here. Let's
The script :file:`memdemo.ys` is used to generate the images included here. Let's
look at the first section:
.. literalinclude:: /code_examples/selections/memdemo.ys
@ -270,7 +275,7 @@ look at the first section:
This loads :numref:`memdemo_src` and synthesizes the included module. Note that
this code can be copied and run directly in a Yosys command line session,
provided ``memdemo.v`` is in the same directory. We can now change to the
provided :file:`memdemo.v` is in the same directory. We can now change to the
``memdemo`` module with ``cd memdemo``, and call :cmd:ref:`show` to see the
diagram in :numref:`memdemo_00`.
@ -397,15 +402,18 @@ Remember that select expressions can also be used directly as arguments to most
commands. Some commands also accept a single select argument to some options. In
those cases selection variables must be used to capture more complex selections.
Example:
Example code from |code_examples/selections|_:
.. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections`
.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/selections
.. literalinclude:: /code_examples/selections/select.v
:language: verilog
:caption: ``docs/source/code_examples/selections/select.v``
:caption: :file:`select.v`
.. literalinclude:: /code_examples/selections/select.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/selections/select.ys``
:caption: :file:`select.ys`
:name: select_ys
.. figure:: /_images/code_examples/selections/select.*

28
docs/source/using_yosys/synthesis/cell_libs.rst
View file

@ -7,16 +7,16 @@ Mapping to cell libraries
While much of this documentation focuses on the use of Yosys with FPGAs, it is
also possible to map to cell libraries which can be used in designing ASICs.
This section will cover a brief `example project`_, available in the Yosys
source code as ``docs/source/code_examples/intro/*``. The project contains a
simple ASIC synthesis script (``counter.ys``), a digital design written in
Verilog (``counter.v``), and a simple CMOS cell library (``mycells.lib``). Many
of the early steps here are already covered in more detail in the
:doc:`/getting_started/example_synth` document.
source code under :file:`docs/source/code_examples/intro/`. The project
contains a simple ASIC synthesis script (:file:`counter.ys`), a digital design
written in Verilog (:file:`counter.v`), and a simple CMOS cell library
(:file:`mycells.lib`). Many of the early steps here are already covered in more
detail in the :doc:`/getting_started/example_synth` document.
.. note::
The ``counter.ys`` script includes the commands used to generate the images
in this document. Code snippets in this document skip these commands;
The :file:`counter.ys` script includes the commands used to generate the
images in this document. Code snippets in this document skip these commands;
including line numbers to allow the reader to follow along with the source.
To learn more about these commands, check out :ref:`interactive_show`.
@ -32,7 +32,7 @@ First, let's quickly look at the design:
:language: Verilog
:linenos:
:name: counter-v
:caption: ``counter.v``
:caption: :file:`counter.v`
This is a simple counter with reset and enable. If the reset signal, ``rst``,
is high then the counter will reset to 0. Otherwise, if the enable signal,
@ -46,7 +46,7 @@ Loading the design
:language: yoscrypt
:lines: 1-3
:lineno-match:
:caption: ``counter.ys`` - read design
:caption: :file:`counter.ys` - read design
Our circuit now looks like this:
@ -63,7 +63,7 @@ Coarse-grain representation
:language: yoscrypt
:lines: 7-10
:lineno-match:
:caption: ``counter.ys`` - the high-level stuff
:caption: :file:`counter.ys` - the high-level stuff
.. figure:: /_images/code_examples/intro/counter_01.*
:class: width-helper
@ -77,7 +77,7 @@ Logic gate mapping
:language: yoscrypt
:lines: 14-15
:lineno-match:
:caption: ``counter.ys`` - mapping to internal cell library
:caption: :file:`counter.ys` - mapping to internal cell library
.. figure:: /_images/code_examples/intro/counter_02.*
:class: width-helper
@ -94,7 +94,7 @@ our internal cell library will be mapped to:
:language: Liberty
:linenos:
:name: mycells-lib
:caption: ``mycells.lib``
:caption: :file:`mycells.lib`
Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
``$_OR_``, ``$_XOR_``, and ``$_MUX_`` with an assortment of dff memory types.
@ -106,7 +106,7 @@ Recall that the Yosys built-in logic gate types are ``$_NOT_``, ``$_AND_``,
:language: yoscrypt
:lines: 20-27
:lineno-match:
:caption: ``counter.ys`` - mapping to hardware
:caption: :file:`counter.ys` - mapping to hardware
The final version of our ``counter`` module looks like this:
@ -122,4 +122,4 @@ which can then be loaded into another tool:
:language: yoscrypt
:lines: 30-31
:lineno-match:
:caption: ``counter.ys`` - write synthesized design
:caption: :file:`counter.ys` - write synthesized design

45
docs/source/using_yosys/synthesis/extract.rst
View file

@ -12,7 +12,11 @@ The extract pass
.. todo:: add/expand supporting text, also mention custom pattern matching and
pmgen
Example code can be found in ``docs/source/code_examples/macc/``.
Example code can be found in |code_examples/macc|_.
.. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc`
.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/macc
.. literalinclude:: /code_examples/macc/macc_simple_test.ys
:language: yoscrypt
@ -34,15 +38,15 @@ Example code can be found in ``docs/source/code_examples/macc/``.
.. literalinclude:: /code_examples/macc/macc_simple_test.v
:language: verilog
:caption: ``macc_simple_test.v``
:caption: :file:`macc_simple_test.v`
.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
:language: verilog
:caption: ``macc_simple_xmap.v``
:caption: :file:`macc_simple_xmap.v`
.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
:language: verilog
:caption: ``macc_simple_test_01.v``
:caption: :file:`macc_simple_test_01.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_01a.*
:class: width-helper
@ -52,7 +56,7 @@ Example code can be found in ``docs/source/code_examples/macc/``.
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
:language: verilog
:caption: ``macc_simple_test_02.v``
:caption: :file:`macc_simple_test_02.v`
.. figure:: /_images/code_examples/macc/macc_simple_test_02a.*
:class: width-helper
@ -90,10 +94,9 @@ Example: DSP48_MACC
This section details an example that shows how to map MACC operations of
arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder
(such as the Xilinx DSP48 cells). Source code can be found in
``docs/source/code_examples/macc/``.
(such as the Xilinx DSP48 cells).
Preconditioning: ``macc_xilinx_swap_map.v``
Preconditioning: :file:`macc_xilinx_swap_map.v`
Make sure ``A`` is the smaller port on all multipliers
@ -101,49 +104,49 @@ Make sure ``A`` is the smaller port on all multipliers
.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
:language: verilog
:caption: ``macc_xilinx_swap_map.v``
:caption: :file:`macc_xilinx_swap_map.v`
Wrapping multipliers: ``macc_xilinx_wrap_map.v``
Wrapping multipliers: :file:`macc_xilinx_wrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 1-46
:caption: ``macc_xilinx_wrap_map.v``
:caption: :file:`macc_xilinx_wrap_map.v`
Wrapping adders: ``macc_xilinx_wrap_map.v``
Wrapping adders: :file:`macc_xilinx_wrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 48-89
:caption: ``macc_xilinx_wrap_map.v``
:caption: :file:`macc_xilinx_wrap_map.v`
Extract: ``macc_xilinx_xmap.v``
Extract: :file:`macc_xilinx_xmap.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
:language: verilog
:caption: ``macc_xilinx_xmap.v``
:caption: :file:`macc_xilinx_xmap.v`
... simply use the same wrapping commands on this module as on the design to
create a template for the :cmd:ref:`extract` command.
Unwrapping multipliers: ``macc_xilinx_unwrap_map.v``
Unwrapping multipliers: :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 1-30
:caption: ``$__mul_wrapper`` module in ``macc_xilinx_unwrap_map.v``
:caption: ``$__mul_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
Unwrapping adders: ``macc_xilinx_unwrap_map.v``
Unwrapping adders: :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 32-61
:caption: ``$__add_wrapper`` module in ``macc_xilinx_unwrap_map.v``
:caption: ``$__add_wrapper`` module in :file:`macc_xilinx_unwrap_map.v`
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 1-6
:caption: ``test1`` of ``macc_xilinx_test.v``
:caption: ``test1`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test1a.*
:class: width-helper
@ -154,7 +157,7 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 8-13
:caption: ``test2`` of ``macc_xilinx_test.v``
:caption: ``test2`` of :file:`macc_xilinx_test.v`
.. figure:: /_images/code_examples/macc/macc_xilinx_test2a.*
:class: width-helper

15
docs/source/using_yosys/synthesis/memory.rst
View file

@ -33,27 +33,32 @@ Example
.. todo:: describe ``memory`` images
|code_examples/synth_flow|_.
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/synth_flow
.. figure:: /_images/code_examples/synth_flow/memory_01.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
:caption: :file:`memory_01.ys`
.. literalinclude:: /code_examples/synth_flow/memory_01.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/memory_01.v``
:caption: :file:`memory_01.v`
.. figure:: /_images/code_examples/synth_flow/memory_02.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/memory_02.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/memory_02.v``
:caption: :file:`memory_02.v`
.. literalinclude:: /code_examples/synth_flow/memory_02.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
:caption: :file:`memory_02.ys`
.. _memory_map:
@ -71,7 +76,7 @@ For example:
memory_map
:cmd:ref:`memory_libmap` attempts to convert memory cells (``$mem_v2`` etc) into
hardware supported memory using a provided library (``my_memory_map.txt`` in the
hardware supported memory using a provided library (:file:`my_memory_map.txt` in the
example above). Where necessary, emulation logic is added to ensure functional
equivalence before and after this conversion. :yoscrypt:`techmap -map
my_memory_map.v` then uses :cmd:ref:`techmap` to map to hardware primitives. Any

17
docs/source/using_yosys/synthesis/proc.rst
View file

@ -28,13 +28,18 @@ Example
.. todo:: describe ``proc`` images
|code_examples/synth_flow|_.
.. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/synth_flow
.. literalinclude:: /code_examples/synth_flow/proc_01.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_01.v``
:caption: :file:`proc_01.v`
.. literalinclude:: /code_examples/synth_flow/proc_01.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
:caption: :file:`proc_01.ys`
.. figure:: /_images/code_examples/synth_flow/proc_01.*
:class: width-helper
@ -44,19 +49,19 @@ Example
.. literalinclude:: /code_examples/synth_flow/proc_02.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_02.v``
:caption: :file:`proc_02.v`
.. literalinclude:: /code_examples/synth_flow/proc_02.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
:caption: :file:`proc_02.ys`
.. figure:: /_images/code_examples/synth_flow/proc_03.*
:class: width-helper
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
:caption: :file:`proc_03.ys`
.. literalinclude:: /code_examples/synth_flow/proc_03.v
:language: verilog
:caption: ``docs/source/code_examples/synth_flow/proc_03.v``
:caption: :file:`proc_03.v`