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Docs: tidying
- Use `:file:` role for file names, as well as `:makevar:` and `:program:`. - Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets. - Add link to ABC. - More (and better) links to code examples. Formatted `:file:` text with link to source on github. - Includes a few extra todos (mostly picking up inline code blocks and a couple intro reminders). - Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags. - Reflowing some paragraphs for spacing/width.
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@ -26,7 +26,7 @@ First, let's quickly look at the design we'll be synthesizing:
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.. literalinclude:: /code_examples/fifo/fifo.v
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:language: Verilog
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:linenos:
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:caption: ``fifo.v``
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:caption: :file:`fifo.v`
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:name: fifo-v
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.. todo:: fifo.v description
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@ -36,7 +36,7 @@ Loading the design
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Let's load the design into Yosys. From the command line, we can call ``yosys
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fifo.v``. This will open an interactive Yosys shell session and immediately
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parse the code from ``fifo.v`` and convert it into an Abstract Syntax Tree
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parse the code from :ref:`fifo-v` and convert it into an Abstract Syntax Tree
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(AST). If you are interested in how this happens, there is more information in
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the document, :doc:`/yosys_internals/flow/verilog_frontend`. For now, suffice
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it to say that we do this to simplify further processing of the design. You
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@ -214,7 +214,7 @@ could restart our shell session, but instead let's use two new commands:
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:language: doscon
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:start-at: design -reset
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:end-before: yosys> proc
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:caption: reloading ``fifo.v`` and running :yoscrypt:`hierarchy -check -top fifo`
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:caption: reloading :file:`fifo.v` and running :yoscrypt:`hierarchy -check -top fifo`
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Notice how this time we didn't see any of those `$abstract` modules? That's
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because when we ran ``yosys fifo.v``, the first command Yosys called was
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@ -234,7 +234,7 @@ design. If we know that our design won't run into this issue, we can skip the
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The number before a command's output increments with each command run. Don't
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worry if your numbers don't match ours! The output you are seeing comes from
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the same script that was used to generate the images in this document,
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included in the source as ``fifo.ys``. There are extra commands being run
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included in the source as :file:`fifo.ys`. There are extra commands being run
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which you don't see, but feel free to try them yourself, or play around with
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different commands. You can always start over with a clean slate by calling
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``exit`` or hitting ``ctrl+c`` (i.e. SIGINT) and re-launching the Yosys
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@ -305,8 +305,8 @@ optimizations between modules which would otherwise be missed. Let's run
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The pieces have moved around a bit, but we can see :ref:`addr_gen_proc` from
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earlier has replaced the ``fifo_reader`` block in :ref:`rdata_proc`. We can
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also see that the ``addr`` output has been renamed to ``fifo_reader.addr`` and
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merged with the ``raddr`` wire feeding into the ``$memrd`` cell. This wire
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also see that the ``addr`` output has been renamed to :file:`fifo_reader.addr`
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and merged with the ``raddr`` wire feeding into the ``$memrd`` cell. This wire
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merging happened during the call to :cmd:ref:`clean` which we can see in the
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:ref:`flat_clean`. Note that in an interactive terminal the outputs of
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:cmd:ref:`flatten` and :cmd:ref:`clean` will be combined into a single
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@ -803,11 +803,11 @@ The iCE40 synthesis flow has the following output modes available:
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- :doc:`/cmd/write_json`.
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As an example, if we called :yoscrypt:`synth_ice40 -top fifo -json fifo.json`,
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our synthesized ``fifo`` design will be output as ``fifo.json``. We can then
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read the design back into Yosys with :cmd:ref:`read_json`, but make sure you use
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:yoscrypt:`design -reset` or open a new interactive terminal first. The JSON
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output we get can also be loaded into `nextpnr`_ to do place and route; but that
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is beyond the scope of this documentation.
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our synthesized ``fifo`` design will be output as :file:`fifo.json`. We can
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then read the design back into Yosys with :cmd:ref:`read_json`, but make sure
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you use :yoscrypt:`design -reset` or open a new interactive terminal first. The
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JSON output we get can also be loaded into `nextpnr`_ to do place and route; but
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that is beyond the scope of this documentation.
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.. _nextpnr: https://github.com/YosysHQ/nextpnr
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