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synth_quicklogic: rearrange files to prepare for adding more architectures

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This commit is contained in:
N. Engelhardt 2023-07-07 15:27:21 +02:00 • committed by Martin Povišer
parent 8bd681acfc
commit 98769010af
20 changed files with 139 additions and 113 deletions
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53
techlibs/quicklogic/pp3/lut_map.v Normal file
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@ -0,0 +1,53 @@
module \$lut (
A, Y
);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0])
);
end else if (WIDTH == 2) begin
LUT2 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1])
);
end else if (WIDTH == 3) begin
LUT3 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2])
);
end else if (WIDTH == 4) begin
LUT4 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2]),
.I3(A[3])
);
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule