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gowin: infer DSP multipliers for the GW5A family

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synth_gowin guarded the mul2dsp + dsp_map path to gw1n/gw2a, so GW5A
multiplies expanded to LUTs. Add a gw5a branch mapping the GW5A's three
multiplier widths: $__MUL27X18 (M0 27x18) for larger multiplies, $__MUL12X12
(M1 12x12) for <=12x12 (which pack two-per-block via M0+M1), and $__MUL27X36
(27x36) for wide (B>18) multiplies.

The blocks are signed-only (no per-operand sign control), so DSP_SIGNEDONLY
is mandatory without it a 32x16 -1*-1 mapping yields 0x08000001 instead of 1.
This commit is contained in:
Johan Olby 2026-07-12 21:00:21 +02:00
parent 0e82bbefe5
commit 98656e284b
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tests/arch/gowin/mul_gw5a.v Normal file
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// Signed multiply for GW5A DSP boundary tests (the GW5A multipliers are
// signed-only, so signed operands exercise the routing boundaries cleanly).
module top
#(parameter X_WIDTH=8, Y_WIDTH=8, A_WIDTH=16)
(
input signed [X_WIDTH-1:0] x,
input signed [Y_WIDTH-1:0] y,
output signed [A_WIDTH-1:0] A
);
assign A = x * y;
endmodule

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tests/arch/gowin/mul_gw5a.ys Normal file
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# GW5A DSP multiply boundary tests. Probes each routing edge:
# 12x12 small-cell max (fits MULT12X12)
# 13x13 MINWIDTH=13 cutoff (-> MULTALU27X18)
# 27x18 large-cell exact fit (B<=18 -> MULTALU27X18)
# 27x19 B overflows 18 -> MULT27X36 cascade
# 28x18 A overflows 27 -> decomposition
# 12x12 -> 1 MULT12X12 (small cell, below MINWIDTH=13)
read_verilog mul_gw5a.v
chparam -set X_WIDTH 12 -set Y_WIDTH 12 -set A_WIDTH 24
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULT12X12
# 13x13 -> 1 MULTALU27X18 (MINWIDTH=13 cutoff routes to the large cell)
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 13 -set Y_WIDTH 13 -set A_WIDTH 26
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULTALU27X18
# 27x18 -> 1 MULTALU27X18 (exact fit of the large cell)
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set A_WIDTH 45
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULTALU27X18
# 28x18 -> A overflows 27: 1 MULTALU27X18 + MULT12X12 partials
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 28 -set Y_WIDTH 18 -set A_WIDTH 46
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULTALU27X18
select -assert-count 2 t:MULT12X12
# 27x19 -> B overflows 18: routes to MULT27X36 (2 cascaded DSPs)
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 27 -set Y_WIDTH 19 -set A_WIDTH 46
hierarchy -top top
proc
synth_gowin -family gw5a
cd top
select -assert-count 1 t:MULT27X36
# Make sure that DSPs are not inferred with -nodsp option
design -reset
read_verilog mul_gw5a.v
chparam -set X_WIDTH 27 -set Y_WIDTH 18 -set A_WIDTH 45
hierarchy -top top
proc
synth_gowin -family gw5a -nodsp
cd top
select -assert-none t:MULTALU27X18
select -assert-none t:MULT12X12