mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-20 12:53:39 +00:00
rename: format vector slices consistently with HDL upto/downto direction
This commit is contained in:
parent
fa6968d2ee
commit
983ff1be1e
1 changed files with 0 additions and 2 deletions
|
@ -94,8 +94,6 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, strin
|
|||
if (chunk.wire->width != chunk.width) {
|
||||
int lhs = chunk.wire->to_hdl_index(chunk.offset + chunk.width - 1);
|
||||
int rhs = chunk.wire->to_hdl_index(chunk.offset);
|
||||
if (chunk.wire->upto)
|
||||
std::swap(lhs, rhs);
|
||||
|
||||
if (lhs != rhs)
|
||||
name += stringf("[%d:%d]", lhs, rhs);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue