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presentation progress

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Clifford Wolf 2014-02-02 22:26:26 +01:00
parent 9d0b69edaa
commit 982c9da011
19 changed files with 199 additions and 45 deletions
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19
manual/PRESENTATION_ExSyn/opt_04.v Normal file
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module test(input CLK, ARST,
output [7:0] Q1, Q2, Q3);
wire NO_CLK = 0;
always @(posedge CLK, posedge ARST)
if (ARST)
Q1 <= 42;
always @(posedge NO_CLK, posedge ARST)
if (ARST)
Q2 <= 42;
else
Q2 <= 23;
always @(posedge CLK)
Q3 <= 42;
endmodule