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presentation progress

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Clifford Wolf 2014-02-02 22:26:26 +01:00
parent 9d0b69edaa
commit 982c9da011
19 changed files with 199 additions and 45 deletions
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manual/PRESENTATION_ExSyn/memory_02.ys Normal file
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read_verilog memory_02.v
hierarchy -check -top test
proc;; memory -nomap
opt -mux_undef -mux_bool