presentation progress

manual/PRESENTATION_ExSyn/Makefile

@@ -1,12 +1,18 @@
 
-all: proc_00.pdf proc_01.pdf proc_02.pdf
+TARGETS += proc_01 proc_02 proc_03
+TARGETS += opt_01 opt_02 opt_03 opt_04
+TARGETS += memory_01 memory_02
 
-proc_00.pdf: proc_00.v proc_00.ys
-	../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf'
+all: $(addsuffix .pdf,$(TARGETS))
 
-proc_01.pdf: proc_01.v proc_01.ys
-	../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf'
+define make_pdf_template
+$(1).pdf: $(1).v $(1).ys
+	../../yosys -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
+endef
 
-proc_02.pdf: proc_02.v proc_02.ys
-	../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf'
+$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
+
+clean:
+	rm -f $(addsuffix .pdf,$(TARGETS))
+	rm -f $(addsuffix .dot,$(TARGETS))
 

manual/PRESENTATION_ExSyn/memory_01.v

@@ -0,0 +1,9 @@
+module test(input      CLK, ADDR,
+            input      [7:0] DIN,
+	    output reg [7:0] DOUT);
+    reg [7:0] mem [0:1];
+    always @(posedge CLK) begin
+        mem[ADDR] <= DIN;
+	DOUT <= mem[ADDR];
+    end
+endmodule

manual/PRESENTATION_ExSyn/memory_01.ys

@@ -0,0 +1,3 @@
+read_verilog memory_01.v
+hierarchy -check -top test
+proc;; memory; opt

manual/PRESENTATION_ExSyn/memory_02.v

@@ -0,0 +1,27 @@
+module test(
+    input             WR1_CLK,  WR2_CLK,
+    input             WR1_WEN,  WR2_WEN,
+    input      [7:0]  WR1_ADDR, WR2_ADDR,
+    input      [7:0]  WR1_DATA, WR2_DATA,
+    input             RD1_CLK,  RD2_CLK,
+    input      [7:0]  RD1_ADDR, RD2_ADDR,
+    output reg [7:0]  RD1_DATA, RD2_DATA
+);
+
+reg [7:0] memory [0:255];
+
+always @(posedge WR1_CLK)
+    if (WR1_WEN)
+        memory[WR1_ADDR] <= WR1_DATA;
+
+always @(posedge WR2_CLK)
+    if (WR2_WEN)
+        memory[WR2_ADDR] <= WR2_DATA;
+
+always @(posedge RD1_CLK)
+    RD1_DATA <= memory[RD1_ADDR];
+
+always @(posedge RD2_CLK)
+    RD2_DATA <= memory[RD2_ADDR];
+
+endmodule

manual/PRESENTATION_ExSyn/memory_02.ys

@@ -0,0 +1,4 @@
+read_verilog memory_02.v
+hierarchy -check -top test
+proc;; memory -nomap
+opt -mux_undef -mux_bool

manual/PRESENTATION_ExSyn/opt_01.v

@@ -0,0 +1,3 @@
+module test(input A, B, output Y);
+assign Y = A ? A ? B : 1'b1 : B;
+endmodule

manual/PRESENTATION_ExSyn/opt_01.ys

@@ -0,0 +1,3 @@
+read_verilog opt_01.v
+hierarchy -check -top test
+opt

manual/PRESENTATION_ExSyn/opt_02.v

@@ -0,0 +1,3 @@
+module test(input A, output Y, Z);
+assign Y = A == A, Z = A != A;
+endmodule

manual/PRESENTATION_ExSyn/opt_02.ys

@@ -0,0 +1,3 @@
+read_verilog opt_02.v
+hierarchy -check -top test
+opt

manual/PRESENTATION_ExSyn/opt_03.v

@@ -0,0 +1,4 @@
+module test(input  [3:0] A, B,
+            output [3:0] Y, Z);
+assign Y = A + B, Z = B + A;
+endmodule

manual/PRESENTATION_ExSyn/opt_03.ys

@@ -0,0 +1,3 @@
+read_verilog opt_03.v
+hierarchy -check -top test
+opt

manual/PRESENTATION_ExSyn/opt_04.v

@@ -0,0 +1,19 @@
+module test(input CLK, ARST,
+            output [7:0] Q1, Q2, Q3);
+
+wire NO_CLK = 0;
+
+always @(posedge CLK, posedge ARST)
+	if (ARST)
+		Q1 <= 42;
+
+always @(posedge NO_CLK, posedge ARST)
+	if (ARST)
+		Q2 <= 42;
+	else
+		Q2 <= 23;
+
+always @(posedge CLK)
+	Q3 <= 42;
+
+endmodule

manual/PRESENTATION_ExSyn/opt_04.ys

@@ -0,0 +1,3 @@
+read_verilog opt_04.v
+hierarchy -check -top test
+proc; opt

manual/PRESENTATION_ExSyn/proc_00.v

@@ -1,7 +0,0 @@
-module test(input D, C, R, output reg Q);
-    always @(posedge C, posedge R)
-        if (R)
-	    Q <= 0;
-	else
-	    Q <= D;
-endmodule

manual/PRESENTATION_ExSyn/proc_01.v

@@ -1,8 +1,7 @@
-module test(input D, C, R, RV,
-            output reg Q);
+module test(input D, C, R, output reg Q);
     always @(posedge C, posedge R)
         if (R)
-	    Q <= RV;
+	    Q <= 0;
 	else
 	    Q <= D;
 endmodule

manual/PRESENTATION_ExSyn/proc_02.v

@@ -1,10 +1,8 @@
-module test(input A, B, C, D, E,
-            output reg Y);
-    always @* begin
-	Y <= A;
-	if (B)
-	    Y <= C;
-	if (D)
-	    Y <= E;
-    end
+module test(input D, C, R, RV,
+            output reg Q);
+    always @(posedge C, posedge R)
+        if (R)
+	    Q <= RV;
+	else
+	    Q <= D;
 endmodule

manual/PRESENTATION_ExSyn/proc_03.v

@@ -0,0 +1,10 @@
+module test(input A, B, C, D, E,
+            output reg Y);
+    always @* begin
+	Y <= A;
+	if (B)
+	    Y <= C;
+	if (D)
+	    Y <= E;
+    end
+endmodule

manual/PRESENTATION_ExSyn/proc_03.ys

@@ -1,3 +1,3 @@
-read_verilog proc_00.v
+read_verilog proc_03.v
 hierarchy -check -top test
 proc;;