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Add memory_libmap tests.

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Marcelina Kościelnicka 2022-05-06 16:30:56 +02:00
parent 2a2dc12eb6
commit 982a11c709
22 changed files with 1500 additions and 0 deletions
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13
tests/memlib/memlib_wide_write.txt Normal file
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ram block \RAM_WIDE_WRITE {
cost 2;
abits 6;
widths 1 2 4 8 per_port;
byte 4;
init any;
port srsw "A" {
width rd 2 wr 8;
clock posedge;
rden;
rdwr old;
}
}