mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-22 02:57:51 +00:00
Code Activity

Add memory_libmap tests.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2022-05-06 16:30:56 +02:00
parent 2a2dc12eb6
commit 982a11c709
22 changed files with 1500 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

30
tests/memlib/memlib_lut.v Normal file
View file

@ -0,0 +1,30 @@
module RAM_LUT(
input [3:0] PORT_R_ADDR,
input [3:0] PORT_RW_ADDR,
input PORT_RW_CLK,
input PORT_RW_WR_EN,
input [3:0] PORT_RW_WR_DATA,
output [3:0] PORT_R_RD_DATA,
output [3:0] PORT_RW_RD_DATA
);
parameter INIT = 0;
parameter PORT_RW_CLK_POL = 1;
reg [3:0] mem [0:15];
integer i;
initial
for (i = 0; i < 16; i += 1)
mem[i] = INIT[i*4+:4];
assign PORT_R_RD_DATA = mem[PORT_R_ADDR];
assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR];
wire CLK = PORT_RW_CLK ~^ PORT_RW_CLK_POL;
always @(posedge CLK)
if (PORT_RW_WR_EN)
mem[PORT_RW_ADDR] <= PORT_RW_WR_DATA;
endmodule