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Add memory_libmap tests.
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10
tests/memlib/memlib_block_tdp.txt
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10
tests/memlib/memlib_block_tdp.txt
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ram block \RAM_BLOCK_TDP {
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cost 64;
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abits 10;
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widths 1 2 4 8 16 per_port;
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init any;
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port srsw "A" "B" {
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clock anyedge;
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rdwr no_change;
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}
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}
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