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Add memory_libmap tests.

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Marcelina Kościelnicka 2022-05-06 16:30:56 +02:00
parent 2a2dc12eb6
commit 982a11c709
22 changed files with 1500 additions and 0 deletions
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22
tests/memlib/memlib_block_sdp_1clk.txt Normal file
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ram block \RAM_BLOCK_SDP_1CLK {
cost 64;
abits 10;
widths 1 2 4 8 16 per_port;
init any;
port sw "W" {
clock anyedge "C";
ifdef TRANS_OLD {
option "TRANS" 0 {
wrtrans "R" old;
}
}
ifdef TRANS_NEW {
option "TRANS" 1 {
wrtrans "R" new;
}
}
}
port sr "R" {
clock anyedge "C";
}
}