mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-02 16:20:51 +00:00
Code Activity

Revert "Add tests for ecp5 architecture."

Browse source 
This reverts commit 134d3fea90.
This commit is contained in:
SergeyDegtyar 2019-08-27 18:28:05 +03:00
parent 134d3fea90
commit 980830f7b8
31 changed files with 0 additions and 865 deletions
Download patch file Download diff file Expand all files Collapse all files

22
tests/ecp5/memory.ys
View file

@ -1,22 +0,0 @@
read_verilog memory.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 24 t:L6MUX21
select -assert-count 71 t:LUT4
select -assert-count 32 t:PFUMX
select -assert-count 8 t:TRELLIS_DPR16X4
select -assert-count 35 t:TRELLIS_FF
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
write_verilog memory_synth.v