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Revert "Add tests for ecp5 architecture."

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This reverts commit 134d3fea90.
This commit is contained in:
SergeyDegtyar 2019-08-27 18:28:05 +03:00
parent 134d3fea90
commit 980830f7b8
31 changed files with 0 additions and 865 deletions
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8
tests/ecp5/add_sub.ys
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read_verilog add_sub.v
hierarchy -top top
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4
select -assert-none t:LUT4 %% t:* %D