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Add approximate support for SV "var" keyword, fixes #987

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-05-04 07:52:51 +02:00
parent c2e29ab809
commit 9804c86e87
2 changed files with 5 additions and 1 deletions
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frontends/verilog/verilog_lexer.l
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@ -207,6 +207,7 @@ YOSYS_NAMESPACE_END
"checker" { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
"endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"var" { SV_KEYWORD(TOK_VAR); }
"bit" { SV_KEYWORD(TOK_REG); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }