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https://github.com/YosysHQ/yosys
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Merge 620f510479
into e046e3cdbf
This commit is contained in:
commit
97fa2585e9
1 changed files with 18 additions and 2 deletions
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@ -44,6 +44,7 @@ struct BlifDumperConfig
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bool iattr_mode;
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bool iattr_mode;
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bool blackbox_mode;
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bool blackbox_mode;
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bool noalias_mode;
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bool noalias_mode;
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bool gatesi_mode;
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std::string buf_type, buf_in, buf_out;
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std::string buf_type, buf_in, buf_out;
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std::map<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> unbuf_types;
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std::map<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> unbuf_types;
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@ -51,7 +52,7 @@ struct BlifDumperConfig
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BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
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BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
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cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
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cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
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blackbox_mode(false), noalias_mode(false) { }
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blackbox_mode(false), noalias_mode(false), gatesi_mode(false) { }
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};
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};
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struct BlifDumper
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struct BlifDumper
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@ -229,6 +230,8 @@ struct BlifDumper
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if (cell->type == ID($scopeinfo))
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if (cell->type == ID($scopeinfo))
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continue;
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continue;
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auto gate_init = cell->hasPort(ID::Q) ? str_init(cell->getPort(ID::Q)) : std::string("");
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if (config->unbuf_types.count(cell->type)) {
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if (config->unbuf_types.count(cell->type)) {
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auto portnames = config->unbuf_types.at(cell->type);
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auto portnames = config->unbuf_types.at(cell->type);
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f << stringf(".names %s %s\n1 1\n",
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f << stringf(".names %s %s\n1 1\n",
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@ -410,7 +413,13 @@ struct BlifDumper
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goto internal_cell;
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goto internal_cell;
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}
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}
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f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type).c_str());
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if (config->gatesi_mode && config->gates_mode) {
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f << stringf(".%s %s%s", subckt_or_gate(cell->type.str()), str(cell->type).c_str(), gate_init.c_str());
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}
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else {
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f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type).c_str());
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}
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for (auto &conn : cell->connections())
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for (auto &conn : cell->connections())
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{
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{
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if (conn.second.size() == 1) {
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if (conn.second.size() == 1) {
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@ -550,6 +559,9 @@ struct BlifBackend : public Backend {
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log(" -impltf\n");
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log(" -impltf\n");
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log(" do not write definitions for the $true, $false and $undef wires.\n");
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log(" do not write definitions for the $true, $false and $undef wires.\n");
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log("\n");
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log("\n");
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log(" -gatesi\n");
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log(" append initial bit(s) for gates that needs to be initialized.\n");
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log("\n");
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}
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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{
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@ -640,6 +652,10 @@ struct BlifBackend : public Backend {
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config.noalias_mode = true;
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config.noalias_mode = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-gatesi") {
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config.gatesi_mode = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(f, filename, args, argidx);
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extra_args(f, filename, args, argidx);
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