From 97a804ac128b2a5b9e945a44a467aa5a73ec50cf Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Fri, 25 Oct 2024 15:52:19 -0700
Subject: [PATCH] Split large constants onto new lines in verilog backend

---
 backends/verilog/verilog_backend.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ae8d035e2..ad3b74ed4 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -363,6 +363,19 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 		f << "{0{1'b0}}";
 		return;
 	}
+	if (sig.is_fully_const() && GetSize(sig) > 8192) {
+		f << stringf("{ ");
+		int i = 0;
+		for (auto it = sig.bits().rbegin(); it != sig.bits().rend(); ++it) {
+			dump_const(f, it->data, 1, 0);
+			if (it != sig.bits().rend() - 1)
+				f << stringf(", ");
+			if (i++ % 20 == 19)
+				f << stringf("\n");
+		}
+		f << stringf(" }");
+		return;
+	}
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
 	} else {