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Added RTLIL::Cell::has(portname)

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This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions
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4
passes/sat/expose.cc
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@ -83,7 +83,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
SigPool dffsignals;
for (auto &it : module->cells) {
if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q"))
if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
dffsignals.add(sigmap(it.second->get("\\Q")));
}
@ -628,7 +628,7 @@ struct ExposePass : public Pass {
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
RTLIL::SigSpec sig;
if (cell->connections().count(p->name) != 0)
if (cell->has(p->name))
sig = cell->connections().at(p->name);
sig.extend(w->width);
if (w->port_input)