mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-14 23:05:28 +00:00
Code Activity

Added RTLIL::Cell::has(portname)

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/fsm/fsm_detect.cc
View file

@ -80,7 +80,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
continue;
if (cellport.second != "\\A" && cellport.second != "\\B")
return false;
if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0)
if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y"))
return false;
for (auto &port_it : cell->connections())
if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")