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Added RTLIL::Cell::has(portname)

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This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions
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2
passes/cmds/add.cc
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@ -75,7 +75,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
if (mod->get_bool_attribute("\\blackbox"))
continue;
if (it.second->connections().count(name) > 0)
if (it.second->has(name))
continue;
it.second->set(name, wire);