3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 23:43:16 +00:00

Added RTLIL::Cell::has(portname)

This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions

View file

@ -488,6 +488,7 @@ public:
RTLIL_ATTRIBUTE_MEMBERS
// access cell ports
bool has(RTLIL::IdString portname);
void unset(RTLIL::IdString portname);
void set(RTLIL::IdString portname, RTLIL::SigSpec signal);
const RTLIL::SigSpec &get(RTLIL::IdString portname) const;