mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-04 06:53:59 +00:00
abc9_ops/xaiger: further reducing Module::derive() calls by ...
replacing _all_ (* abc9_box *) instantiations with their derived types
This commit is contained in:
parent
e79127fceb
commit
97a0a04314
4 changed files with 122 additions and 136 deletions
|
@ -3,10 +3,10 @@
|
|||
module $_DFF_x_(input C, D, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
parameter _TECHMAP_CELLTYPE_ = "";
|
||||
wire D_;
|
||||
(* init=_TECHMAP_WIREINIT_Q_ *) wire D_;
|
||||
generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
|
||||
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
|
||||
$__DFF_N__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
|
||||
$__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
|
||||
$_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
|
||||
end
|
||||
else
|
||||
|
@ -14,7 +14,7 @@ module $_DFF_x_(input C, D, output Q);
|
|||
end
|
||||
else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
|
||||
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
|
||||
$__DFF_P__$abc9_flop #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
|
||||
$__DFF_P__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
|
||||
$_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
|
||||
end
|
||||
else
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue