mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
This commit is contained in:
parent
94f15f023c
commit
979bf36fb0
6 changed files with 60 additions and 41 deletions
|
@ -20,7 +20,8 @@
|
|||
|
||||
// ============================================================================
|
||||
|
||||
module \$__ABC9_ASYNC (input A, S, output Y);
|
||||
(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
|
||||
module \$__ABC9_ASYNC01 (input A, S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue