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Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t

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Eddie Hung 2019-12-19 11:23:41 -08:00
parent 94f15f023c
commit 979bf36fb0
6 changed files with 60 additions and 41 deletions
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14
techlibs/xilinx/abc9_model.v
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@ -33,11 +33,19 @@ endmodule
module \$__ABC9_FF_ (input D, output Q);
endmodule
// Box to emulate async behaviour of FDC*
(* abc_box_id = 1000 *)
module \$__ABC9_ASYNC (input A, S, output Y);
module \$__ABC9_ASYNC0 (input A, S, output Y);
assign Y = S ? 1'b0 : A;
endmodule
// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
// Box to emulate async behaviour of FDP*
(* abc_box_id = 1001 *)
module \$__ABC9_ASYNC1 (input A, S, output Y);
assign Y = S ? 1'b0 : A;
endmodule
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
// Necessary since RAMD* and SRL* have both combinatorial (i.e.
// same-cycle read operation) and sequential (write operation
// is only committed on the next clock edge).
@ -46,7 +54,7 @@ endmodule
(* abc9_box_id=2000 *)
module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
endmodule
// Box to emulate comb/seq behaviour of RAMD128
// Box to emulate comb/seq behaviour of RAM128
(* abc9_box_id=2001 *)
module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
endmodule