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Update simple_abc9 tests

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This commit is contained in:
Eddie Hung 2020-02-13 12:13:12 -08:00
parent e22fee6cdd
commit 977262c803
3 changed files with 8 additions and 5 deletions
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7
tests/simple_abc9/abc9.v
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@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
input rst;
endmodule
(* abc9_box_id=1, whitebox *)
(* abc9_box, blackbox *)
module MUXF8(input I0, I1, S, output O);
specify
(I0 => O) = 0;
(I1 => O) = 0;
(S => O) = 0;
endspecify
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet