Accept (and ignore) SystemVerilog unique/priority if.

Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.

docs/source/yosys_internals/verilog.rst

@@ -375,3 +375,9 @@ from SystemVerilog:
   ports are inputs or outputs are supported.
 
 - Assignments within expressions are supported.
+
+- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
+  accepted on ``if`` and ``case`` conditionals.  (Those keywords are currently
+  handled in the same way as their equivalent ``full_case`` and
+  ``parallel_case`` attributes on ``case`` statements, and checked
+  for syntactic validity but otherwise ignored on ``if`` statements.)