diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc
index cce5d2c4f..1af6a8987 100644
--- a/techlibs/gatemate/gatemate_foldinv.cc
+++ b/techlibs/gatemate/gatemate_foldinv.cc
@@ -82,7 +82,7 @@ struct FoldInvWorker {
         Const result(State::S0, GetSize(lut));
         for (int i = 0; i < GetSize(lut); i++) {
             int j = i ^ (1 << bit);
-            result.bits()[j] = lut[i];
+            result.set(j, lut[i]);
         }
         return result;
     }
@@ -91,7 +91,7 @@ struct FoldInvWorker {
     {
         Const result(State::S0, GetSize(lut));
         for (int i = 0; i < GetSize(lut); i++)
-            result.bits()[i] = (lut[i] == State::S1) ? State::S0 : State::S1;
+            result.set(i, (lut[i] == State::S1) ? State::S0 : State::S1);
         return result;
     }
 
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index 37f6d8d9b..4f60a5c37 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -36,9 +36,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 		Const initval = cell->getParam(ID::INIT);
 		if (GetSize(initval) >= 1) {
 			if (initval[0] == State::S0)
-				initval.bits()[0] = State::S1;
+				initval.set(0, State::S1);
 			else if (initval[0] == State::S1)
-				initval.bits()[0] = State::S0;
+				initval.set(0, State::S0);
 			cell->setParam(ID::INIT, initval);
 		}
 
@@ -47,9 +47,9 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 			Const srmode = cell->getParam(ID(SRMODE));
 			if (GetSize(srmode) >= 1) {
 				if (srmode[0] == State::S0)
-					srmode.bits()[0] = State::S1;
+					srmode.set(0, State::S1);
 				else if (srmode[0] == State::S1)
-					srmode.bits()[0] = State::S0;
+					srmode.set(0, State::S0);
 				cell->setParam(ID(SRMODE), srmode);
 			}
 		}
diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc
index cbd05cb3e..326a3d07e 100644
--- a/techlibs/microchip/microchip_dffopt.cc
+++ b/techlibs/microchip/microchip_dffopt.cc
@@ -93,7 +93,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
 			int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
 			new_bit = data.first[lut_idx] == State::S1;
 		}
-		result.first.bits()[i] = new_bit ? State::S1 : State::S0;
+		result.first.set(i, new_bit ? State::S1 : State::S0);
 	}
 	return true;
 }
diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc
index 3dfcb8905..df7093bc5 100644
--- a/techlibs/microchip/microchip_dsp.cc
+++ b/techlibs/microchip/microchip_dsp.cc
@@ -128,7 +128,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
 					continue;
 				for (int i = c.offset; i < c.offset + c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
-					it->second.bits()[i] = State::Sx;
+					it->second.set(i, State::Sx);
 				}
 			}
 		};
@@ -244,7 +244,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
 					continue;
 				for (int i = c.offset; i < c.offset + c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
-					it->second.bits()[i] = State::Sx;
+					it->second.set(i, State::Sx);
 				}
 			}
 		};
diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc
index fdd2de406..cd509ce7f 100644
--- a/techlibs/quicklogic/ql_dsp_simd.cc
+++ b/techlibs/quicklogic/ql_dsp_simd.cc
@@ -200,10 +200,8 @@ struct QlDspSimdPass : public Pass {
 						auto val_a = dsp_a->getParam(it);
 						auto val_b = dsp_b->getParam(it);
 
-						mode_bits.bits().insert(mode_bits.bits().end(),
-							val_a.begin(), val_a.end());
-						mode_bits.bits().insert(mode_bits.bits().end(),
-							val_b.begin(), val_b.end());
+						mode_bits.append(val_a);
+						mode_bits.append(val_b);
 					}
 
 					// Enable the fractured mode by connecting the control
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index edd906048..89518913d 100644
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -92,7 +92,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
 			int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
 			new_bit = data.first[lut_idx] == State::S1;
 		}
-		result.first.bits()[i] = new_bit ? State::S1 : State::S0;
+		result.first.set(i, new_bit ? State::S1 : State::S0);
 	}
 	return true;
 }
@@ -211,8 +211,8 @@ lut_sigin_done:
 				Cell *cell_d = it_D->second.second;
 				if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
 					// Flip all bits in the LUT.
-					for (int i = 0; i < GetSize(lut_d.first); i++)
-						lut_d.first.bits()[i] = (lut_d.first[i] == State::S1) ? State::S0 : State::S1;
+					for (auto bit : lut_d.first)
+						bit = (bit == State::S1) ? State::S0 : State::S1;
 				}
 
 				LutData lut_d_post_ce;
diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc
index f95930a90..22e6bce5b 100644
--- a/techlibs/xilinx/xilinx_dsp.cc
+++ b/techlibs/xilinx/xilinx_dsp.cc
@@ -343,7 +343,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 			// Since B is an exact power of 2, subtract 1
 			//   by inverting all bits up until hitting
 			//   that one hi bit
-			for (auto &b : B.bits())
+			for (auto b : B)
 				if (b == State::S0) b = State::S1;
 				else if (b == State::S1) {
 					b = State::S0;
@@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
-					it->second.bits()[i] = State::Sx;
+					it->second.set(i, State::Sx);
 				}
 			}
 		};
@@ -579,7 +579,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
-					it->second.bits()[i] = State::Sx;
+					it->second.set(i, State::Sx);
 				}
 			}
 		};
@@ -702,7 +702,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 					continue;
 				for (int i = c.offset; i < c.offset+c.width; i++) {
 					log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
-					it->second.bits()[i] = State::Sx;
+					it->second.set(i, State::Sx);
 				}
 			}
 		};
diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc
index 32a0064a6..2c23f8f42 100644
--- a/techlibs/xilinx/xilinx_srl.cc
+++ b/techlibs/xilinx/xilinx_srl.cc
@@ -40,9 +40,8 @@ void run_fixed(xilinx_srl_pm &pm)
 			log_assert(Q.wire);
 			auto it = Q.wire->attributes.find(ID::init);
 			if (it != Q.wire->attributes.end()) {
-				auto &i = it->second.bits()[Q.offset];
-				initval.append(i);
-				i = State::Sx;
+				initval.append(it->second[Q.offset]);
+				it->second.set(Q.offset, State::Sx);
 			}
 			else
 				initval.append(State::Sx);
@@ -121,9 +120,8 @@ void run_variable(xilinx_srl_pm &pm)
 			log_assert(Q.wire);
 			auto it = Q.wire->attributes.find(ID::init);
 			if (it != Q.wire->attributes.end()) {
-				auto &i = it->second.bits()[Q.offset];
-				initval.append(i);
-				i = State::Sx;
+				initval.append(it->second[Q.offset]);
+				it->second.set(Q.offset, State::Sx);
 			}
 			else
 				initval.append(State::Sx);