mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 15:24:57 +00:00
Code Activity

Add xilinx_srl test

Browse source
This commit is contained in:
Eddie Hung 2019-08-28 09:24:19 -07:00
parent ba5d81c7f1
commit 975aaf190f
3 changed files with 127 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

67
tests/xilinx/xilinx_srl.ys Normal file
View file

@ -0,0 +1,67 @@
read_verilog xilinx_srl.v
design -save read
design -copy-to model $__XILINX_SHREG_
hierarchy -top xilinx_srl_static_test
prep
design -save gold
techmap
xilinx_srl -fixed
opt
# stat
# show -width
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
dump gate
sat -verify -prove-asserts -show-ports -seq 5 miter
#design -load gold
#stat
#design -load gate
#stat
##########
design -load read
design -copy-to model $__XILINX_SHREG_
hierarchy -top xilinx_srl_variable_test
prep
design -save gold
simplemap t:$dff t:$dffe
xilinx_srl -variable
opt
#stat
# show -width
# write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
design -stash gate
design -import gold -as gold
design -import gate -as gate
design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
# design -load gold
# stat
# design -load gate
# stat