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Added skeleton dff2dffe pass

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This commit is contained in:
Clifford Wolf 2014-12-08 14:10:52 +01:00
parent 7b62bbeee8
commit 97487fee32
3 changed files with 78 additions and 2 deletions
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1
passes/techmap/Makefile.inc
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@ -10,6 +10,7 @@ OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract.o
OBJS += passes/techmap/maccmap.o OBJS += passes/techmap/maccmap.o
OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/dff2dffe.o
endif endif
GENFILES += passes/techmap/techmap.inc GENFILES += passes/techmap/techmap.inc

4
passes/techmap/alumacc.cc
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@ -538,8 +538,8 @@ struct AlumaccPass : public Pass {
log("\n"); log("\n");
log(" alumacc [selection]\n"); log(" alumacc [selection]\n");
log("\n"); log("\n");
log("This pass translates arithmetic operations $add, $mul, $lt, etc. to $alu and\n"); log("This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu\n");
log("$macc cells.\n"); log("and $macc cells.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)

75
passes/techmap/dff2dffe.cc Normal file
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@ -0,0 +1,75 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct Dff2dffeWorker
{
RTLIL::Module *module;
SigMap sigmap;
Dff2dffeWorker(RTLIL::Module *module) : module(module), sigmap(module)
{
}
void run()
{
log("Transforming $dff to $dffe cells in module %s:\n", log_id(module));
}
};
struct Dff2dffePass : public Pass {
Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" dff2dffe [selection]\n");
log("\n");
log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n");
log("more feedback paths to a $dffe cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// if (args[argidx] == "-foobar") {
// foobar_mode = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);
for (auto mod : design->selected_modules())
if (!mod->has_processes_warn()) {
Dff2dffeWorker worker(mod);
worker.run();
}
}
} Dff2dffePass;
PRIVATE_NAMESPACE_END