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	Fixed a bug in "select %ci %co %x"
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					 1 changed files with 5 additions and 4 deletions
				
			
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					@ -376,6 +376,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
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		RTLIL::Module *mod = mod_it.second;
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							RTLIL::Module *mod = mod_it.second;
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		std::set<RTLIL::Wire*> selected_wires;
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							std::set<RTLIL::Wire*> selected_wires;
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							auto selected_members = lhs.selected_members[mod->name];
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		for (auto &it : mod->wires_)
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							for (auto &it : mod->wires_)
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			if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
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								if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
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					@ -389,9 +390,9 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
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			for (size_t i = 0; i < conn_lhs.size(); i++) {
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								for (size_t i = 0; i < conn_lhs.size(); i++) {
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				if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL)
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									if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL)
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					continue;
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										continue;
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				if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && lhs.selected_members[mod->name].count(conn_lhs[i].wire->name) == 0)
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									if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && selected_members.count(conn_lhs[i].wire->name) == 0)
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					lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--;
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										lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--;
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				if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && lhs.selected_members[mod->name].count(conn_rhs[i].wire->name) == 0)
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									if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && selected_members.count(conn_rhs[i].wire->name) == 0)
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					lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--;
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										lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--;
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			}
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								}
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		}
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							}
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					@ -418,10 +419,10 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
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			is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
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								is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first);
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			for (auto &chunk : conn.second.chunks())
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								for (auto &chunk : conn.second.chunks())
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				if (chunk.wire != NULL) {
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									if (chunk.wire != NULL) {
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					if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0)
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										if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && selected_members.count(cell.first) == 0)
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						if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
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											if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input))
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							lhs.selected_members[mod->name].insert(cell.first), sel_objects++, max_objects--;
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												lhs.selected_members[mod->name].insert(cell.first), sel_objects++, max_objects--;
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					if (max_objects != 0 && lhs.selected_members[mod->name].count(cell.first) > 0 && limits.count(cell.first) == 0 && lhs.selected_members[mod->name].count(chunk.wire->name) == 0)
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										if (max_objects != 0 && selected_members.count(cell.first) > 0 && limits.count(cell.first) == 0 && selected_members.count(chunk.wire->name) == 0)
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						if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
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											if (mode == 'x' || (mode == 'i' && is_input) || (mode == 'o' && is_output))
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							lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
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												lhs.selected_members[mod->name].insert(chunk.wire->name), sel_objects++, max_objects--;
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				}
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									}
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