mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-04 10:20:24 +00:00
Code Activity

verific: Fix conditions of SVAs with explicit clocks within procedures

Browse source 
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
This commit is contained in:
Jannis Harder 2022-05-03 13:22:18 +02:00
parent 11e75bc27c
commit 96f64f4788
4 changed files with 27 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

12
frontends/verific/verificsva.cc
View file

@ -1522,10 +1522,13 @@ struct VerificSvaImporter
if (inst == nullptr)
return false;
if (clocking.cond_net != nullptr)
if (clocking.cond_net != nullptr) {
trig = importer->net_map_at(clocking.cond_net);
else
if (!clocking.cond_pol)
trig = module->Not(NEW_ID, trig);
} else {
trig = State::S1;
}
if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY)
{
@ -1587,8 +1590,11 @@ struct VerificSvaImporter
SigBit trig = State::S1;
if (clocking.cond_net != nullptr)
if (clocking.cond_net != nullptr) {
trig = importer->net_map_at(clocking.cond_net);
if (!clocking.cond_pol)
trig = module->Not(NEW_ID, trig);
}
if (inst == nullptr)
{