mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 19:52:31 +00:00
Code Activity

verific: Fix conditions of SVAs with explicit clocks within procedures

Browse source 
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
This commit is contained in:
Jannis Harder 2022-05-03 13:22:18 +02:00
parent 11e75bc27c
commit 96f64f4788
4 changed files with 27 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.h
View file

@ -44,6 +44,7 @@ struct VerificClocking {
SigBit disable_sig = State::S0;
bool posedge = true;
bool gclk = false;
bool cond_pol = true;
VerificClocking() { }
VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false);